Coating Of Sidewall Patents (Class 438/696)
  • Patent number: 8735296
    Abstract: A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ryan O. Jung, Sivananda K. Kanakasabapathy
  • Publication number: 20140141617
    Abstract: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Shinya WATANABE
  • Publication number: 20140138797
    Abstract: A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20140138800
    Abstract: A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: May 22, 2014
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventor: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
  • Patent number: 8728932
    Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8728945
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Steven Alan Lytle
  • Patent number: 8728906
    Abstract: A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Tai Chang, Yi-Shan Chen, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8722535
    Abstract: According to one embodiment, a pattern forming method is disclosed. The method can include forming an insulating layer on a major surface of a substrate. The method can include forming first and second openings on the insulating layer. The first opening has a first length in a first direction along the major surface, and the second opening has a second length longer than the first length in the first direction. The method can include forming a first pattern in the first opening. The method can include forming a second pattern in the second opening. The method can include forming a self-assembled material film contacting the insulating layer, the first pattern and the second pattern. The method can include forming a third pattern with guidance of the second pattern. In addition, the method can include forming a fourth pattern contacting the first pattern based on the third pattern.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masafumi Asano
  • Patent number: 8722501
    Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: May 13, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Chien-Liang Lin, Chien-Ting Lin, Ssu-I Fu, Ying-Tsung Chen
  • Patent number: 8716133
    Abstract: A three photomask image transfer method. The method includes using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Ryan O. Jung, Neal V. Lafferty, Yunpeng Yin
  • Patent number: 8716135
    Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: May 6, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Judy Huckabay, Milind Weling, Abdurrahman Sezginer
  • Patent number: 8716136
    Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Berthold Reimer, Johannes von Kluge, Sven Beyer
  • Publication number: 20140120727
    Abstract: A method for etching a tungsten containing layer in an etch chamber is provided. A substrate is placed with a tungsten containing layer in the etch chamber. A plurality of cycles is provided. Each cycle comprises a passivation phase for forming a passivation layer on sidewalls and bottoms of features in the tungsten containing layer. Additionally, each cycle comprises an etch phase for etching features in the tungsten containing layer.
    Type: Application
    Filed: May 7, 2013
    Publication date: May 1, 2014
    Inventors: Ramkumar SUBRAMANIAN, Anne LE GOUIL, Yoko YAMAGUCHI
  • Publication number: 20140120728
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.
    Type: Application
    Filed: January 8, 2014
    Publication date: May 1, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Angelique Denise RALEY, Takuya MORI, Hirota OHTAKE
  • Patent number: 8709267
    Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chwen Yu, Fei-Gwo Tsai, Kai-Wen Cheng
  • Patent number: 8709947
    Abstract: A method for forming a pattern according to an embodiment, includes forming a first film pattern having a wide width dimension above a processed film; forming a second film pattern covering a portion of the first film pattern and a third film pattern connected to the second film pattern together above the processed film, the third film pattern having a width dimension narrower than the first film pattern, and to be a line pattern of a line and space pattern; forming a fourth film pattern on a side face of the first film pattern and a plurality of film patterns by the fourth film to be a line pattern of a line and space pattern on both side faces of the third film pattern; and removing the second film pattern and the third film pattern.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuji Kobayashi
  • Publication number: 20140106567
    Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Inventors: Jae-Ho Min, O-Ik Kwon, Bum-Soo Kim, Dong-Chan Kim, Myeong-Cheol Kim
  • Patent number: 8697557
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: April 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser, Frank Jakubowski
  • Patent number: 8697530
    Abstract: By modifying the dielectric liner for a spacer structure so as to exhibit an enhanced diffusion blocking characteristic, for instance by incorporating nitrogen, the out-diffusion of P-dopants, such as boron, into the dielectric material may be significantly reduced. Consequently, transistor performance, especially of P-type transistors, may be significantly enhanced while nevertheless a high degree of compatibility with conventional techniques may be maintained.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: April 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ekkehard Pruefer, Ralf Van Bentum, Klaus Hempel, Stephan Kruegel
  • Patent number: 8697538
    Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Winbond Electronics Corp.
    Inventor: Lu-Ping Chiang
  • Publication number: 20140097521
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Thoralf Kautzsch, Alessia Scire, Steffen Bieselt
  • Publication number: 20140099792
    Abstract: Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8691701
    Abstract: A method for forming etched features in a low-k dielectric layer disposed below the photoresist mask in a plasma processing chamber is provided. Features are etched into the low-k dielectric layer through the photoresist mask. The photoresist mask is stripped, wherein the stripping comprising at least one cycle, wherein each cycle comprises a fluorocarbon stripping phase, comprising flowing a fluorocarbon stripping gas into the plasma processing chamber, forming a plasma from the fluorocarbon stripping gas, and stopping the flow of the fluorocarbon stripping gas into the plasma processing chamber and a reduced fluorocarbon stripping phase, comprising flowing a reduced fluorocarbon stripping gas that has a lower fluorocarbon flow rate than the fluorocarbon stripping gas into the plasma processing chamber, forming the plasma from the reduced fluorocarbon stripping gas, and stopping the flow of the reduced fluorocarbon stripping gas.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: April 8, 2014
    Assignee: Lam Research Corporation
    Inventors: Bing Ji, Andrew D. Bailey, III, Maryam Moravej, Stephen M. Sirard
  • Patent number: 8691698
    Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 8, 2014
    Assignee: Lam Research Corporation
    Inventors: Qing Xu, William Thie, Camelia Rusu
  • Patent number: 8691697
    Abstract: A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8685859
    Abstract: Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Juengling Werner, Richard Lane
  • Patent number: 8679981
    Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: March 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Milind Weling, Judy Huckabay, Abdurrahman Sezginer
  • Patent number: 8673165
    Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sudharshanan Raghunathan, Sivananda Kanakasabapathy, Ryan O. Jung, Allen H Gabor, Sean D. Burns, Erin Catherine McLellan
  • Patent number: 8673778
    Abstract: A tungsten film forming method for forming a tungsten film on a surface of a substrate while heating the substrate in a depressurized atmosphere in a processing chamber includes forming an initial tungsten film for tungsten nucleation on the surface of the substrate by alternately repeating a supply of WF6 gas which is raw material of tungsten and a supply of H2 gas which is a reducing gas in the processing chamber while performing a purge in the processing chamber between the supplies of the WF6 gas and the H2 gas and adsorbing a gas containing a material for nucleation onto a surface of the initial tungsten film. The film forming method further includes depositing a crystallinity blocking tungsten film for blocking crystallinity of the initial tungsten film by supplying the WF6 gas and the H2 gas into the processing chamber.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: March 18, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Kohichi Satoh
  • Patent number: 8671878
    Abstract: An apparatus for forming spacers is provided. A plasma processing chamber is provided, comprising a chamber wall, a substrate support, a pressure regulator, an antenna, a bias electrode, a gas inlet, and a gas outlet. A gas source comprises an oxygen gas source and an anisotropic etch gas source. A controller comprises a processor and computer readable media. The computer readable media comprises computer readable code for placing a substrate of the plurality of substrates in a plasma etch chamber, computer readable code for providing a plasma oxidation treatment to form a silicon oxide coating over the spacer layer, computer readable code for sputtering silicon to form silicon oxide with the oxygen plasma, computer readable code for providing an anisotropic main etch, computer readable code for etching the spacer layer, computer readable code for removing the substrate from the plasma etch chamber after etching the spacer layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Qinghua Zhong, Sung Cho, Gowri Kamarthy, Linda Braly
  • Patent number: 8673785
    Abstract: A gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus is provided. The gas distribution system can include a gas supply section, a flow control section and a switching section. The gas supply section provides first and second gases, typically gas mixtures, to the flow control section, which controls the flows of the first and second gases to the chamber. The chamber can include multiple zones, and the flow control section can supply the first and second gases to the multiple zones at desired flow ratios of the gases. The gas distribution system can continuously supply the first and second gases to the switching section and the switching section is operable to switch the flows of the first and second gases, such that one of the first and second process gases is supplied to the chamber while the other of the first and second gases is supplied to a by-pass line, and then to switch the gas flows.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Zhisong Huang, Jose Tong Sam, Eric H. Lenz, Rajinder Dhindsa, Reza Sadjadi
  • Patent number: 8669186
    Abstract: In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: March 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Nicholas V. LiCausi
  • Patent number: 8664120
    Abstract: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Watanabe
  • Patent number: 8664102
    Abstract: A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: March 4, 2014
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: David L. O'Meara, Anthony Dip, Aelan Mosden, Pao-Hwa Chou, Richard A Conti
  • Publication number: 20140038416
    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 6, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David H. Wells, Mirzafer K. Abatchev
  • Patent number: 8642483
    Abstract: A substrate processing method that processes a substrate including a processing target layer, an intermediate layer, and a mask layer as stacked in that order. The intermediate layer includes an Si-ARC (Si-containing Anti-Reflection Coating) film and the mask layer has an opening exposing a part of the Si-ARC. The substrate processing method includes a shrink etching step during which an opening width reduction process and an etching process are performed concurrently. In the opening width reduction process, deposits are formed on a sidewall surface of the opening of the mask layer by a plasma generated from a gaseous mixture of an anisotropic etching gas and one of a depositive gas and H2 gas. And in the etching process, the Si-ARC film forming a bottom portion of the opening are etched.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: February 4, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Masanobu Honda
  • Publication number: 20140027878
    Abstract: A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Chiahsun Tseng, Chun-chen Yeh, Yunpeng Yin, Lei L. Zhuang
  • Patent number: 8629064
    Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: January 14, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Xiaoyang Li, Duan-Fu Stephen Hsu
  • Patent number: 8629052
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: January 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-ju Park, Jae-ho Min, Myeong-cheol Kim, Dong-chan Kim, Jae-hwang Sim
  • Patent number: 8629040
    Abstract: A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Tai Chang, Yi-Shan Chen, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8623770
    Abstract: A method for sidewall spacer line doubling uses thermal atomic layer deposition (ALD) of a titanium oxide (TiOx) spacer layer. A hardmask layer is deposited on a suitable substrate. A mandrel layer of diamond-like carbon (DLC) is deposited on the hardmask layer and patterned into stripes with tops and sidewalls. A layer of TiOx is deposited, by thermal ALD without the assistance of plasma or ozone, on the tops and sidewalls of the mandrel stripes. Thermal ALD of the TiO2, without energy assistance by plasma or ozone, has been found to cause no damage to the DLC mandrel stripes. After removal of the TiOx from the tops of the mandrel stripes and removal of the mandrel stripes, stripes of TiO2 are left on the hardmask layer and may be used as an etch mask to transfer the pattern into the hardmask layer.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 7, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: He Gao, Jeffrey S. Lille, Kanaiyalal Chaturdas Patel
  • Patent number: 8617975
    Abstract: Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: December 31, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Swarnal Borthakur, Richard L. Stocks
  • Patent number: 8614148
    Abstract: A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Soo Park, Jongchul Park, Cheolhong Kim, Seokwoo Nam, Kukhan Yoon
  • Patent number: 8609491
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eui-Seong Hwang
  • Patent number: 8609488
    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
  • Publication number: 20130323929
    Abstract: Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 5, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hongbin Zhu
  • Patent number: 8598037
    Abstract: A method of etching a silicon layer through a patterned mask is provided. The method uses an etch chamber in which the silicon layer is placed. The method includes (a) providing the silicon layer having the patterned mask formed thereon, (b) providing an etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas into the etch chamber in which the silicon layer has been placed, (c) generating a plasma from the etch gas, (d) etching features into the silicon layer through the patterned mask using the plasma, and (e) stopping the etch gas. The oxygen and hydrogen containing gas contains water vapor.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: December 3, 2013
    Assignee: Lam Research Corporation
    Inventors: Jaroslaw W. Winniczek, Robert P. Chebi
  • Publication number: 20130295770
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Application
    Filed: July 5, 2013
    Publication date: November 7, 2013
    Inventors: Mirzafer Abatchev, David Wells, Baosuo ` Zhou, Krupakar Murali Subramanian
  • Patent number: 8574447
    Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 5, 2013
    Assignee: Lam Research Corporation
    Inventors: Tsuyoshi Aso, Camelia Rusu
  • Patent number: 8568598
    Abstract: A manufacturing method of a tip type probe includes the steps of: forming on a substrate an etching mask of a shape similar to a shape of a top surface of a truncated pyramid; forming the truncated pyramid by subjecting the substrate to isotropic etching using the etching mask as a mask member; stopping the isotropic etching when an area of the top surface reaches an area capable of generating near-field light; and forming a metal film on at least some of the side surfaces of the truncated pyramid by allowing film forming particles to enter into a space between the etching mask and the side surfaces and adhere onto the truncated pyramid. The directivity of the film forming particles is controlled so that the metal film has a thickness that is reduced gradually from a bottom of the truncated pyramid toward the top surface.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: October 29, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Majung Park, Manabu Oumi