Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 ?m to ±100 ?m. Since with that warp device fabrication by photolithography is challenging, reducing the warp to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the warp. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the warp.

Abstract: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

Abstract: A method for manufacturing a bottom substrate of a liquid crystal display device by using only three masks is disclosed. The method includes the following steps. First, a patterned first metal layer, an insulating layer, a semiconductor layer and a second metal layer are formed subsequently on a substrate. Afterwards, the second metal layer is manufactured to have two different thicknesses by using a photolithographic process. After that, a planar layer is formed on the second metal layer and then the planar layer is etched until part of the second metal layer is exposed. Finally, a patterned transparent electrode layer is formed on the second metal layer.

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.

Abstract: The disclosure provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445) over a substrate (310), and then forming a layer of material (510) over the semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445). This method further includes selectively etching portions of the layer of material (510) based upon a density or size of the semiconductor features (405, 410, 415, 420, 425, 430, 435, 440, 445) located thereunder, and then polishing remaining portions of the layer of material (510).

Abstract: A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. In a preferred embodiment, the conductive or semiconductor features are pillars forming vertically oriented diodes. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.

Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.

Abstract: A method of forming an isolation layer of a semiconductor device is provided. A wafer having a polysilizane (PSZ) layer formed is loaded into a chamber while a loading temperature is maintained in the chamber. An oxygen gas is supplied to the chamber. After the loading, a temperature within the chamber is raised up to a process temperature. Subsequently, the PSZ layer is cured in the chamber maintaining the process temperature. During the curing step, vapor is supplied to the chamber such that a ratio of the oxygen gas and the vapor is set in the range of 1:1 to 50:1. The inside of the chamber is purged by supplying an inert gas to the chamber where the oxygen gas and the vapor are blocked to be supplied.

Abstract: A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step.

Abstract: In a method of chemically and mechanically polishing a layer, a substrate on which the layer having stepped portions is formed is prepared. The layer is primarily chemically and mechanically polished at a temperature of about 30° C. to about 80° C. to remove the stepped portions of the layer. The layer is secondarily chemically and mechanically polished without the stepped portions at a temperature of about 5° C. to about 25° C. to form a flat layer having a desired thickness. Thus, the stepped portions may be rapidly removed in an initial period so that the method may have an improved throughput.

Abstract: A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.

Abstract: A metal line of semiconductor device and a method of forming the same are provided. An interlayer dielectric (ILD) layer is formed on a semiconductor substrate including a lower line. A via hole is formed in the ILD layer, and a diffusion barrier layer is formed on the ILD layer where the via hole is formed. A copper seed layer and a copper plating layer are repeatedly formed and etched until the hole is completely filled.

Abstract: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for the patterning of the poly emitter in BiCMOS devices. The present invention also relates to a device prepared by a method of the invention.

Abstract: The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing scratches. The method includes the steps of: forming a substrate divided into a peripheral region and a cell region where a capacitor including a metal plate electrode on which particles with a pointed shape are generated is formed; forming an inter-layer insulation layer with a poor step coverage on the metal plate electrode, the particles with the pointed shape and a surface of the substrate in the peripheral region; etching a portion of the inter-layer insulation layer, thereby exposing predetermined portions of lateral sides of the particles with the pointed shape; selectively removing the exposed portions of the particles with the pointed shape to separate top portions of the particles with the pointed shape from the inter-layer insulation layer; and planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process.

Abstract: Alpha-amino acid containing chemical mechanical polishing compositions and slurries that are useful for polishing substrates including multiple layers of metals, or metals and dielectrics.

Abstract: A chemical mechanical polishing pad which has a storage elastic modulus E?(30° C.) at 30° C. of 120 MPa or less and an (E?(30° C.)/E?(60° C.)) ratio of the storage elastic modulus E?(30° C.) at 30° C. to the storage elastic modulus E?(60° C.) at 60° C. of 2.5 or more when the storage elastic moduli of a polishing substrate at 30° C. and 60° C. are measured under the following conditions: initial load: 100 g maximum bias: 0.01 % frequency: 0.2 Hz. A chemical mechanical polishing process makes use of the above chemical mechanical polishing pad. The chemical mechanical polishing pad can suppress the production of a scratch on the polished surface in the chemical mechanical polishing step and can provide a high-quality polished surface, and the chemical mechanical polishing process provides a high-quality polished surface by using the chemical mechanical polishing pad.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

Abstract: A process for fabricating a MEMS device comprises the steps of depositing and patterning on one side of a wafer a layer of material having a preselected electrical resistivity; bonding a substrate to the one side of the wafer using an adhesive bonding agent, the substrate overlying the patterned layer of material; selectively removing portions of the wafer from the side opposite the one side to define stationary and movable MEMS elements; and selectively removing the adhesive bonding agent to release the movable MEMS element, at least a portion of the layer of material being disposed so as to be attached to the movable MEMS element.

Abstract: A method and structure for forming a spring structure that avoids undesirable kinks in the spring is described. The method converts a portion of a release layer such that the converted portion resists etching. The converted portion then serves as an anchor region for a spring structure deposited over the release layer. When the non-converted portions of the release layer are etched, the spring curls out of the plane of a plane.

Abstract: A method for manufacturing a semiconductor device includes: a) forming a first single-crystalline semiconductor layer having a higher etching selection ratio than a semiconductor substrate, in a manner covering an exposed part of a single-crystalline region on an active surface of the semiconductor substrate; b) forming a second single-crystalline semiconductor layer having smaller etching selection ratio than the first single-crystalline semiconductor layer, in a manner covering the first single-crystalline layer; c) removing and opening the second single-crystalline semiconductor layer and the first single-crystalline semiconductor layer within a region, the region being adjacent to an element region formed of a part of the second single-crystalline semiconductor layer and sandwiching the element region, so as to form a recess for a support, the recess exposing the semiconductor substrate; d) forming a support precursor layer over the active surface of the semiconductor substrate in a manner filling the rec

Abstract: A method and apparatus to provide a low resistance interconnect. A void is defined in the sacrificial layer that is proximate to an active layer. An overgrowth layer is formed in the void and over portions of the sacrificial layer adjacent to the void. A ridge section is defined in the overgrowth layer and portions of the sacrificial layer are removed to define a shank section in the overgrowth layer under the ridge section. The ridge section having a greater lateral dimension than the shank section to reduce electrical resistance between the active layer and electrical interconnects to be electrically coupled to the ridge section.

Abstract: A method of smoothening a surface of a semiconductor structure comprises exposing the surface of the semiconductor structure to a reactant. A chemical reaction between a material of the semiconductor structure and the reactant is performed. In the chemical reaction, a layer of a reaction product is formed on at least a portion of the surface of the semiconductor structure. The layer of the reaction product is selectively and completely removed.

Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance. The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

Abstract: Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g.

Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

Abstract: A method is presented for fabricating a read head having a read head sensor and a hard bias/lead layer which includes depositing a strip of sensor material in a sensor material region, and depositing strips of fast-milling dielectric material in first and second fast-milling dielectric material regions adjacent to the sensor material region. A protective layer and a layer of masking material is deposited on the strip of sensor material and the strips of fast-milling dielectric material to provide masked areas and exposed areas. A shaping source, such as an ion milling source, is provided which shapes the exposed areas. Hard bias/lead material is then deposited on the regions of sensor material and fast-milling dielectric material to form first and second leads and a cap on each of these regions. The cap of hard bias/lead material and the masking material is then removed from each of these regions.

Abstract: In a hydrophilicity treatment method including the step of rotating, on a polishing cloth, a mirror surface of a silicon wafer subjected to mirror-polishing followed by rinsing treatment while the mirror surface is pushed onto the cloth under the application of a small load with the contact of the mirror surface with a hydrophilicity treatment liquid, thereby making the mirror surface hydrophilic, the hydrophilicity treatment liquid is an aqueous liquid which comprises an organic compound having at least one hydrophilic group and having a molecular weight of 100 or more, a basic nitrogen-containing organic compound and a surfactant, and which has a pH of 9.5 to 10.5.

Abstract: A semiconductor substrate including a first region, a second region larger than the first region and an isolation region is provided. A mask layer is selectively formed on the first and second regions. A trench is formed on the isolation region. A first isolation material is deposited on the entire surface so that the trench is filled with the first material and the first material covers the first and second regions. The first material is subjected to a chemical mechanical polish so that the mask layer formed on the first region is exposed while the mask layer formed on the second region is still covered by the first material. Then, a second insulation material is deposited on the exposed mask layer and the first material. Finally, the second material is subjected to the chemical mechanical polish so that mask layer formed on the first and second regions is substantially exposed.

Abstract: A phase change memory (PCM) cell and fabricating method thereof are provided. A phase change layer is etched into a tapered structure, and then a dielectric layer on the phase change layer is planarized, until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, when the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced; thereby the operation current is lowered.

Abstract: A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 ?m to ±100 ?m. Since with that warp device fabrication by photolithography is challenging, reducing the warp to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the warp. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the warp.

Abstract: A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.

Abstract: There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through hole conductor 5 and a grounding wiring layer 10, which are made of copper, become concave in a dish-like shape and lowered in level, causing a dishing portion 17 since they have a hardness lower than that of a through hole insulator 11 made of silicon nitride. The through hole insulator 11 is selectively etched by a reactive ion etching method until the through hole insulator 11 comes to have a height equal to the height of a bottom portion 19 of the dishing portion 17 of the through hole conductor 5. The through hole conductors 5 and 25 are aligned with each other, and the bonding surfaces 12 and 22 are bonded to each other in a solid state bonding manner.

Abstract: Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.

Abstract: The disclosure relates to a method for manufacturing a semiconductor device by performing a planarization process including a first CMP process using a slurry including 0.05˜0.5 wt % CeO2 or MnO2 as an abrasive and a second CMP process using a slurry including SiO2 as the other abrasive regardless of order of the processes.

Abstract: Provided is a method of manufacturing a semiconductor device. According to the present invention, it is possible that an interlayer insulating film is planarized by forming the interlayer insulating film using multiple simultaneous deposition-and-etch processes without carrying out a subsequent planarization process. In addition, smoothness can be variably controlled by adjusting the deposition and etch rate.

Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Abstract: During fabrication of a write head via holes are first opened in a gap layer, followed by formation of seed layers instead of the other way around. Moreover a first seed layer is formed, and without the first seed layer being used a second seed layer is formed. The second seed layer (which is the topmost layer) is used in plating to form coils (e.g. of copper) for the write head. After coil formation, the first seed layer is used for plating to form vias (e.g. of NiFe). The two seed layers may be formed in a single operation by using two different targets in a vacuum deposition chamber. Moreover, a single insulation layer is sufficient to insulate and protect all plated elements, regardless of whether they are formed by use of the first seed layer or the second seed layer.

Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.

Abstract: A method of fabricating three-dimensional structures from a plurality of adhered layers of at least a first and a second material wherein the first material is a conductive material and wherein each of a plurality of layers includes treating a surface of a first material prior to deposition of the second material. The treatment of the surface of the first material either (1) decreases the susceptibility of deposition of the second material onto the surface of the first material or (2) eases or quickens the removal of any second material deposited on the treated surface of the first material. In some embodiments the treatment of the first surface includes forming a dielectric coating over the surface and the second material is electrodeposited (e.g. using an electroplating or electrophoretic process). In other embodiments the first material is coated with a conductive material that doesn't readily accept deposits of electroplated or electroless deposited materials.

Abstract: The present invention provides a method of planarizing a substrate, the method including, forming, on the substrate, a patterned layer having a first shape associated therewith; and processing the patterned layer, with the first shape compensating for variations in the processing such that upon processing the patterned layer, the patterned layer comprises a substantially planar shape.

Abstract: A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions is formed over a substrate, and a second base layer having a plurality of voids is formed on the recessed portions of the first base layer. On the second base layer, a third base layer is formed and a semiconductor element is formed thereon. Then, by separating the second base layer at an intersecting surface with the voids, the semiconductor element is peeled off from the substrate.

Abstract: The invention provides an aqueous dispersion for chemical mechanical polishing that can limit scratches of a specific size to a specific number, even with interlayer insulating films with small elastic moduli (silsesquioxane, fluorine-containing SiO2, polyimide-based resins, and the like.). When using the aqueous dispersion for chemical mechanical polishing of an interlayer insulating film with an elastic modulus of no greater than 20 GPa as measured by the nanoindentation method, the number of scratches with a maximum length of 1 ?m or greater is an average of no more than 5 per unit area of 0.01 mm2 of the polishing surface. An aqueous dispersion for CMP or an aqueous dispersion for interlayer insulating film CMP according to another aspect of the invention contains a scratch inhibitor agent and an abrasive. The scratch inhibitor may be biphenol, bipyridyl, 2-vinylpyridine, salicylaldoxime, o-phenylenediamine, catechol, 7-hydroxy-5-methyl-1,3,4-triazaindolizine, and the like.

Abstract: A system for dished metal redevelopment by providing a metal deposition solution at an interface between a moving semiconductor wafer and a moving polishing pad, which deposits metal onto dished metal in trenches in a layer of an interlayer dielectric; and by polishing the wafer with a relatively reduced polishing pressure to polish metal being deposited. A polishing fluid is disclosed for use in a CMP polishing system, the polishing fluid being a metal deposition solution for dished metal redevelopment.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.

Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The device includes a substrate where a conductive region is formed and an interlayer insulating layer. The interlayer insulating layer is stacked on the substrate and has a contact hole exposing the conductive region. The contact hole is filled with a contact plug having a projection over the interlayer insulating layer. The projection of the contact plug is covered with a capacitor including a lower electrode, a ferroelectric layer pattern, and an upper electrode. A width of the projection is preferably greater than that of the contact hole and smaller than that of the lower electrode. The method includes forming lower and upper interlayer insulating layers on a substrate where a conductive region is formed. The lower and upper interlayer insulating layers have a contact hole exposing the conductive region.

Abstract: According to the present invention, a dummy wafer is formed by forming a masking film on a rear surface of a silicon wafer; spray coating aluminum and depositing an aluminum film on a front surface of the silicon wafer; spray coating ceramics or carbon and depositing a ceramic film or carbon film on the aluminum film so that the aluminum film may be completely covered; and removing the masking film formed on the rear surface. Also, a dummy wafer can be formed by using an aluminum wafer as a wafer substrate and subjecting it to anodic oxidation to form a film of aluminum oxide.