Abstract: An etching method is provided for etching a silicon-containing layer into a pattern of a mask that is formed by etching—from a block copolymer layer that includes a first polymer and a second polymer, that is layered on the silicon-containing layer of a process-target object via an intermediate layer, and that is enabled to be self-assembled—a region including the second polymer and the intermediate layer right under the region. The method includes forming a protective film on the mask by arranging upper and lower electrodes facing each other, by applying a negative DC voltage to the upper electrode in a processing chamber of a plasma processing apparatus in which the process-target object is provided, by applying high-frequency power to the upper or lower electrode, and by supplying a process gas including a hydrogen gas and an inert gas into the processing chamber to generate plasma.

Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.

Abstract: A process of forming a silicon nitride film on a nitride semiconductor layer as a passivation film is disclosed. The process first sets a temperature lower than 500° C. to load into a growth reactor, a wafer that provides the nitride semiconductor layer thereon. Then, the process raises the temperature to a deposition temperature higher than 750° C. while replacing the atmosphere in the reactor with pure ammonia (NH3), or a mixed gas of NH3 and N2 with a NH3 partial pressure greater than 0.2, and sets the pressure higher than 3 kPa. Finally, with the pressure lower than 100 Pa and di-chloro-silane (SiH2Cl2) supplied, the SiN is deposited on the nitride semiconductor layer.

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

Abstract: An image sensor includes a first photodiode formed in a first substrate. A first deep-trench isolation (DTI) structure is in the first substrate and surrounds the first photodiode. A first inter-dielectric layer having a first circuit structure is formed on the first substrate. A bonding layer is between the first inter-dielectric layer and a second inter-dielectric layer. The second-inter dielectric layer having a second circuit structure is on the bonding layer. A connection wall is disposed in the first inter-dielectric layer, the bonding layer, and the second inter-dielectric layer to physically connect the first circuit structure and the second circuit structure. A second substrate is disposed on the second inter-dielectric layer. A second photodiode is formed in the second substrate. A second DTI structure is in the second substrate and surrounds the second photodiode.

Abstract: A dry etching method, including: etching a silicon-containing thin film with a first gas by a first preset thickness; etching the silicon-containing thin film with a second gas by a second preset thickness, to remove etching residues generated after etching the silicon-containing thin film by the first preset thickness; after the etching residues are removed, etching the silicon-containing thin film with the first gas by a third preset thickness, which is less than the first preset thickness; wherein the first gas includes chlorine gas, and the second gas includes fluoride gas.

Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.

Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.

Abstract: Methods for manufacturing MEMS structures are provided. The method includes forming a first trench and a second trench in a MEMS substrate by performing a main etching process and etching the MEMS substrate through the first trench and the second trench to form a first through hole and an extended second trench by performing a first step of an over-etching process. The method further includes etching the MEMS substrate through the extended second trench to form a second through hole by performing a second step of the over-etching process. In addition, a width of the first trench is greater than a width of the second trench, and a height of the first trench is greater than ¾ of a height of the MEMS substrate, and a height of the second trench is smaller than ? of the MEMS substrate.

Abstract: The present invention relates to additive manufacturing methods, in which crystalline materials can be formed by using a liquid precursor. In particular embodiments, the crystalline material is a perovskite. The methods include the use of a thermal voxel, which can be translated to form any arbitrary pattern of initial crystalline seed structure(s). Then, the seed structure can be incubated to promote crystal growth and/or crystal dissolution, thereby providing a patterned crystalline material.

Abstract: The present invention pertains to a patterning method. By taking advantage of the etching loading effect due to different pattern densities in the memory cell region and the peripheral region, the first hard mask is not masked when anisotropically etching the first hard mask within the memory cell region.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.

Abstract: Capacitors and methods of forming the same include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.

Abstract: Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a perimeter of the gate, the vertical sidewall having a uniform thickness along its height. A power rail is formed in contact with the vertical sidewall.

Abstract: A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. The isolation structure includes a trench with a concave upper sidewall, a straight lower sidewall and a rounded top corner. A first dielectric layer fills a lower portion of the trench. A second dielectric layer covers a top surface of the first dielectric layer, the concave upper sidewall and the rounded top corner of the trench.

Abstract: A method for processing a stack with an etch layer below a mask is provided. The mask is treated by flowing a treatment gas, wherein the treatment gas comprises a sputtering gas and a trimming gas, providing pulsed TCP power to create a plasma from the treatment gas, and providing a pulsed bias, wherein the pulsed bias has a same period as the pulsed TCP power, wherein the pulsed TCP power and pulsed bias provide a first state with a first bias above a sputter threshold and a first TCP power, which causes species from the sputtering gas to sputter and redeposit material from the mask, and provide a second state with a second bias below the sputter threshold and a second TCP power, wherein the second TCP power is greater than the first TCP power, which causes species from the trimming gas to chemically trim the mask.

Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive sidewall spacer is on a sidewall of the opening and contacts the upper surface of the floating gate conductor.

Abstract: Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a non-planar film because of differences in area density of underlying structures (for example, open areas compared to closely spaced trenches). Etch processes are executed that use a reverse lag RIE process to planarize the initial film, and then another coat of the film material can be deposited, resulting in a planar surface. Such techniques can planarized substrates without using chemical mechanical polishing (CMP).

Abstract: Disclosed are methods of forming different shapes in different regions of a specific layer. In the methods, a first mask layer and an etch process are used to form first shapes in a first region. Subsequently, a second mask layer and additional etch process(es) are used to form second shapes in a second region. However, before the second shapes are formed, a sacrificial layer of a degradable material is deposited onto the first mask layer and within openings in the specific layer surrounding the first shapes, thereby protecting the first shapes during formation of the second shapes. After the second shapes are formed, the material of the sacrificial layer is degraded (e.g., oxidized, volatilized, burned-off, etc.) so as to selectively remove that material from surfaces of the first mask layer and the specific layer without impacting the profiles of either the first shapes or the second shapes.

Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A conductive element protrudes from the upper surface of the floating gate conductor into an opening. A dielectric material defines a reaction region. The reaction region overlies and extends below an upper surface of the conductive element.

Abstract: Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature.

Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; and forming an ultra-low-dielectric-constant (ULK) dielectric layer on a surface of the substrate. The method also includes etching the ultra-low-dielectric-constant dielectric layer to form a trench in the ultra-low-dielectric-constant dielectric layer; and performing an inert plasma treatment process on a side surface of the trench. Further, the method includes performing a carbonization process on the side surface of the trench; and performing a nitridation process on the side surface of the trench to form a SiCNH layer on the side surface of the trench.

Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.

Abstract: A method of processing a target object includes (a) exposing a resist mask to active species of hydrogen generated by exciting plasma of a hydrogen-containing gas within a processing vessel while the target object is mounted on a mounting table provided in the processing vessel; and (b) etching a hard mask layer by exciting plasma of an etchant gas within the processing vessel after the exposing of the resist mask to the active species of hydrogen. The plasma is excited by applying of a high frequency power for plasma excitation to an upper electrode. In the method, a distance between the upper electrode and the mounting table in the etching of the hard mask layer ((b) process) is set to be larger than a distance between the upper electrode and the mounting table in the exposing of the resist mask to the active species of hydrogen ((a) process).

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract: A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.

Abstract: A method of manufacturing a liquid ejection head includes forming, on the substrate, a metal layer formed of a first metal, forming a liquid flow path pattern formed of a second metal that is a metal of a different kind from that of the first metal and that is dissolvable in a solution that does not dissolve the first metal, the liquid flow path pattern being formed on at least a part of a surface of the metal layer, covering the metal layer and the pattern with an inorganic material layer to be formed as the nozzle layer, forming the ejection orifices in the inorganic material layer, and removing the pattern by the solution. A standard electrode potential E1 of the first metal and a standard electrode potential E2 of the second metal have a relationship of E1>E2.

Abstract: A first depression and a second depression are formed in an upper surface of a first metal layer. A dielectric layer is formed over the first metal layer. Subsequently, a wide trench is formed in the dielectric layer, the wide trench extending deeper in a first outer region and in a second outer region than in a central region located between the first outer region and the second outer region, the first outer region overlying the first depression and the second outer region overlying the second depression.

Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques.

Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.

Abstract: A composite wafer semiconductor device includes a first wafer and a second wafer. The first wafer has a first side and a second side, and the second side is substantially opposite the first side. The composite wafer semiconductor device also includes an isolation set is formed on the first side of the first wafer and a free space is etched in the isolation set. The second wafer is bonded to the isolation set. A floating structure, such as an inertia sensing device, is formed in the second wafer over the free space. In an embodiment, a surface mount pad is formed on the second side of the first wafer. Then, the floating structure is electrically coupled to the surface mount pad using a through silicon via (TSV) conductor.

Abstract: A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type; an emitter layer of a second conductive type opposite the first conductive type on the substrate; a first electrode electrically connected to the emitter layer; a passivation layer on the substrate; a second electrode conductive layer on the passivation layer, the second electrode conductive layer including at least one second electrode electrically connected to the substrate through the passivation layer; and a second electrode current collector electrically connected to the second electrode conductive layer.

Abstract: A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule.

Abstract: A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate to thereby define a plurality of fins in the substrate, forming a layer of insulating material in the trenches, performing an etching process sequence to remove at least a portion of one of the plurality of fins and thereby define a fin cavity, wherein the etching process sequence includes performing a first anisotropic etching process and, after performing the first anisotropic etching process, performing a second isotropic etching process. In this embodiment, the method concludes with the step of forming additional insulating material in the fin cavity.

Abstract: Semiconductor devices and methods for forming devices with ultraviolet curing. One method includes, for instance: obtaining a wafer; forming at least one mandrel; forming spacers adjacent to the at least one mandrel; performing an ultraviolet treatment to at least one set of spacers; and etching to form hard mask regions below at least the spacers. An intermediate semiconductor device includes, for instance: a substrate; a stop layer over the substrate; a first barrier layer over the stop layer; at least one first mandrel and at least one second mandrel on the first barrier layer; at least one first set of spacers positioned adjacent to the first mandrel; at least one second set of spacers positioned adjacent to the second mandrel; and a second barrier layer over the at least one first mandrel and the at least one first set of spacers.

Abstract: Provided is a blankmask with a light-shielding layer including a light block layer and an anti-reflective layer, and a hard mask film. The light block layer and the anti-reflective layer are formed by combining a layer formed of a MoSi compound and a layer formed of a MoTaSi compound. Thus, the blankmask enables formation of a pattern of 32 nm or less, since the light-shielding layer can be thinly formed to a thickness of 200 to 700 and a photomask having pattern fidelity corresponding to the resolution of the pattern can be formed. The light-shielding layer has an optical density of 2.0 to 4.0 at an exposure wavelength of 193 nm, chemical resistance, and a sufficient process margin for defect repair. Further, the hard mask film is formed to a thickness of 20 to 50 using a compound including tin (Sn) and chromium (Cr), thereby decreasing an etch rate of the hard mask film. Accordingly, a resist film can be formed as a thin film, thereby manufacturing a high-resolution blankmask.

Abstract: Etching interleaved structures of semiconductor material forming fins of finFETs and local isolation material interposed between the fins is performed alternately and cyclically by alternating etchants cyclically such as by alternating gases during reactive ion etching. Etchants are preferably alternated when one of the semiconductor material and the local isolation material protrudes above the other by a predetermined distance. Since protruding surfaces are etched more rapidly than recessed surfaces, the overall etching process is accelerated and completed in less time such that erosion of other materials to which the etchants are less than optimally selective is reduced and allow improved etching of trenches for improved isolation structures to be formed.

Abstract: An electrical resonator comprises a substrate comprising a cavity. The electrical resonator comprises a resonator stack suspended over the cavity. The resonator stack comprises a first electrode; a second electrode; a piezoelectric layer; and a temperature compensating layer comprising borosilicate glass (BSG).

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

Abstract: A method for fabricating a fin-type field-effect transistor (FinFET) device includes receiving a precursor. The precursor has a plurality of fins over a substrate and a dielectric layer filling in a space between each of fins and extending above the fins. The method also includes forming a patterned hard mask layer having an opening over the dielectric layer, etching the dielectric layer through the opening to form a trench with vertical profile. A subset of the fins is exposed in the trench. The method also includes performing an isotropic dielectric etch to enlarge the trench in a horizontal direction. The method also includes performing an anisotropic etch to recess the subset of fins in the trench and performing an isotropic fin etch to etch the recessed subset of fins.

Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

Abstract: A method of forming an integrated circuit structure includes providing a gate stack and a gate spacer on a sidewall of the gate stack. A contact etch stop layer (CESL) is formed overlying the gate spacer and the gate stack. The CESL includes a top portion over the gate stack, a bottom portion lower than the top portion, and a sidewall portion over a sidewall of the gate spacer. The top and bottom portions are spaced apart from each other by the sidewall portion. The sidewall portion has a thickness less than a thickness of the top portion or a thickness of the bottom portion.

Abstract: A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence.

Abstract: Various techniques are disclosed for an apparatus and a method to remove a layer from a substrate having a pattern formed on the layer. In one example, the apparatus comprises a stage configured to receive and hold the substrate. The apparatus may further comprise an irradiating device comprising a projection lens and configured to irradiate the surface of the substrate with pulses of laser light having a selected fluence to remove an interstitial portion of the layer between the pattern without removing the pattern for corresponding irradiated areas of the substrate. The pulses of laser light may be focused through the projection lens, and the stage and the projection lens may be configured to move continuously relative each other to irradiate a plurality of areas of the substrate with the pulses of laser light.

Abstract: A method for patterning a substrate is disclosed. Depressions are patterned into a resist layer over a substrate. A mask layer is deposited over the resist layer at least partially filling the depressions. The mask layer is etched to expose a top surface of the resist layer and leaving at least a portion of the mask layer in the depressions of the resist layer, wherein the mask layer over said top surface of the resist layer is etched at a faster rate than said mask layer in the depressions of the resist layer. Exposed portions of the resist layer are removed to expose portions of the substrate. Exposed portions of the substrate are etched.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.

Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.