Formation Of Groove Or Trench Patents (Class 438/700)
  • Patent number: 8847400
    Abstract: A semiconductor device comprises a material layer including a first surface and a trench with an opening in the first surface. The trench is formed in the material layer. The trench comprises a tapered portion and a vertical portion. The tapered portion is in contact with the opening and comprises a scalloping-forming trench. The vertical portion has a substantially vertical sidewall. A width of the scalloping-forming trench is larger than a width of the vertical portion.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: September 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Osamu Fujita, Yuki Togashi
  • Patent number: 8841190
    Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first space
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 23, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Changliang Qin, Huaxiang Yin
  • Patent number: 8841217
    Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive element on a sidewall of the opening and extending over an upper surface of the dielectric material.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 23, 2014
    Assignee: Life Technologies Corporation
    Inventors: Keith Fife, James Bustillo, Jordan Owens
  • Publication number: 20140273464
    Abstract: A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask patterns using a hard mask layer deposited over the dummy mandrel layer, wherein the hard mask patterns includes a first dimension adjusted by a predetermined value, depositing a first spacer layer over the hard mask patterns, wherein a thickness of the first spacer layer is adjusted by the predetermined value, forming a plurality of spacer fins in the dummy mandrel layer, wherein the spacer fins include a second dimension, a first space, and a second space, performing a first fin cut process to remove at least one spacer fin, adjusting the second dimension to a target dimension, performing a second fin cut process, and forming a plurality of fin structures in the substrate by etching the spacer fins.
    Type: Application
    Filed: May 13, 2013
    Publication date: September 18, 2014
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 8835293
    Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: September 16, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Rickie C. Lake
  • Patent number: 8835323
    Abstract: A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau, Shih-Ming Chang
  • Patent number: 8835328
    Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: September 16, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Wontae Hwang, Il Goo Kim, Dae-Han Choi, Sang Cheol Han
  • Publication number: 20140256078
    Abstract: Methods, systems, and devices are described for slicing and shaping materials using magnetically guided chemical etching. In one aspect, a method includes forming a pattern on a substrate by a mask, depositing a catalytic etcher layer on the patterned substrate, a magnetic guide layer on the etcher layer, and a protection layer on the guide layer, etching the substrate by applying an etching solution to the substrate that chemically reacts with the etcher layer and etches material from the substrate at exposed regions not covered by the mask, steering the composite etching structure into the substrate during the etching by an applied magnetic field that creates a force on the guide layer to direct the etching, in which the steering defines the shape of the sliced regions of the etched substrate, and removing the etched material, the mask, and the composite etching structure to produce a sliced material structure.
    Type: Application
    Filed: October 12, 2012
    Publication date: September 11, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Sungho Jin, Young Oh, Chulmin Choi, Dae-Hoon Hong, Tae Kyoung Kim
  • Patent number: 8828253
    Abstract: A method of lithography on a substrate uses a self-assembled polymer (SAP) layer deposited on the substrate, with first and second domains arranged in a pattern across the layer. A planarization layer is formed over the SAP and a development etch applied to substantially remove a portion of the planarization layer over the second domain leaving a cap of the planarization layer substantially covering the first domain. The uncapped second domain is then removed from the surface by a breakthrough etch leaving the capped first domain as a pattern feature on the surface. A transfer etch may then be used to transfer the pattern feature to the substrate using the capped first domain. The capping allows the second domain to be removed, e.g., without excessive loss of lateral feature width for the remaining first domain, even when the difference in etch resistance between the first and second domains is small.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 9, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Roelof Koole, Johan Frederik Dijksman, Sander Frederik Wuister, Emiel Peeters
  • Patent number: 8828877
    Abstract: The present invention provides an etching solution less affected by trench structures and also provides an isolation structure-formation process employing the solution. The etching solution contains hydrofluoric acid and an organic solvent. The organic solvent has a ?H value defined by Hansen solubility parameters in the range of 4 to 12 inclusive and the saturation solubility thereof in water is 5 wt % or more at 20° C. This solution can be adopted instead of known etching solutions used in conventional production processes of semiconductor elements.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: September 9, 2014
    Assignee: AZ Electronic Materials USA Corp.
    Inventor: Issei Sakurai
  • Patent number: 8828876
    Abstract: A combination of two lithographically patterned mandrels can be employed in conjunction with sidewall spacers to provide two spacers. The two spacers may intersect each other and/or contact sidewall surfaces of each other to provide a thickness that is a sum of the thicknesses of the two spacers. Further, the two spacers may be patterned to provide various patterns. In addition, portions of at least one of the two spacers may be etched employing an etch mask. Additionally or alternately, an additional material may be selectively added to portions of one of the two spacers.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Publication number: 20140246759
    Abstract: Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a base material, and a developable polymer resist material is applied over the grafted polymer brush material. The resist material is at least partially miscible in the grafted polymer brush material. As such, the resist material at least partially dissolves within the grafted polymer brush material to form an intertwined material of grafted polymer brush macromolecules and resist polymer macromolecules. Adhesion between the developable polymer resist and the base material may be thereby enhanced. Also disclosed are related semiconductor device structures.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8822328
    Abstract: A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wei Huang, Ming-Jui Chen, Ting-Cheng Tseng, Ping-I Hsieh
  • Patent number: 8822341
    Abstract: A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Ho Jeon, Dong-Hyun Kim, Je-Woo Han, Kyoung-Sub Shin
  • Patent number: 8822342
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 2, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ravi Prakash Srivastava, Oluwafemi. O. Ogunsola, Craig Child, Muhammed Shafi Kurikka Valappil Pallachalil, Habib Hichri, Matthew Angyal, Hideshi Miyajima
  • Publication number: 20140241682
    Abstract: Disclosed method and apparatus embodiments provide a photonic device with optical isolation from a supporting substrate. A generally rectangular cavity in cross section is provided below an element of the photonic device and the element may be formed from a ledge of the supporting substrate which is over the cavity.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Roy Meade
  • Patent number: 8816430
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Yanagisawa
  • Patent number: 8815743
    Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Uwe Hoeckele, Thomas Kunstmann, Uwe Seidel
  • Patent number: 8815745
    Abstract: A method of forming features in a porous low-k dielectric layer disposed below a patterned organic mask is provided. Features are etched into the porous low-k dielectric layer through the patterned organic mask, and then the patterned organic mask is stripped. The stripping of the patterned organic mask includes providing a stripping gas comprising COS, forming a plasma from the stripping gas, and stopping the stripping gas. A cap layer may be provided between the porous low-k dielectric layer and the patterned organic mask. The stripping of the patterned organic mask leaves the cap layer on the porous low-k dielectric layer.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: August 26, 2014
    Assignee: Lam Research Corporation
    Inventors: Sean S. Kang, Sang Jun Cho, Thomas S. Choi
  • Patent number: 8815694
    Abstract: Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber
  • Patent number: 8815742
    Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: August 26, 2014
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Coporation
    Inventors: Xiuyu Cai, Ruilong Xie, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 8802571
    Abstract: A method for etching features into a silicon based etch layer through a patterned hard mask in a plasma processing chamber is provided. A silicon sputtering is provided to sputter silicon from the silicon based etch layer onto sidewalls of the patterned hard mask to form sidewalls on the patterned hard mask. The etch layer is etched through the patterned hard mask.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: August 12, 2014
    Assignee: Lam Research Corporation
    Inventors: Wonchul Lee, Qian Fu
  • Publication number: 20140217066
    Abstract: A silicon substrate processing method includes forming an etching mask which has an opening portion, on a surface of a silicon substrate, forming an etching guide hole in the opening portion on the silicon substrate, and forming a through-hole which passes through the silicon substrate, by applying an etching treatment onto the silicon substrate in which the etching guide hole is formed. In the forming of the guide hole, the etching guide hole passing through the silicon substrate is formed by irradiating the opening portion with a laser beam a plurality of times, with a cooling period between each instance of irradiation with the laser beam.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 7, 2014
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kazuhiro GOMI
  • Patent number: 8796136
    Abstract: A semiconductor device is provided, which includes an annular insulation separation portion penetrating a semiconductor substrate, and an electrode penetrating the semiconductor substrate in a region surrounded by the annular insulation separation portion, wherein the insulation separation portion includes at least a first film that gives compressive stress in a depth direction on the side of a substrate, a second film that gives tensile stress in the depth direction is formed on the first film, and film thicknesses of the first and second films are adjusted so that the compressive stress and the tensile stress are almost balanced.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: August 5, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Satoru Sugiyama, Yuuta Nishioka
  • Patent number: 8796148
    Abstract: A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: François Leverd, Laurent Favennec, Arnaud Tournier
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Publication number: 20140206195
    Abstract: A method of removing carbon materials, preferably amorphous carbon, from a substrate includes dispensing a liquid sulfuric acid composition including sulfuric acid and/or its desiccating species and precursors and having a water/sulfuric acid molar ratio of no greater than 5:1 onto an material coated substrate in an amount effective to substantially uniformly coat the carbon material coated substrate. The liquid sulfuric acid composition is exposed to water vapor in an amount effective to increase the temperature of the liquid sulfuric acid composition above the temperature of the liquid sulfuric acid composition prior to exposure to the water vapor. In preferred embodiments, amorphous carbon is selectively removed as compared to a silicon oxide (e.g., silicon dioxide) and/or silicon nitride.
    Type: Application
    Filed: March 15, 2013
    Publication date: July 24, 2014
    Applicant: TEL FSI, Inc.
    Inventor: Jeffrey M. Lauerhaas
  • Patent number: 8785291
    Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiaojun Yu, Brian J. Greene, Yue Liang
  • Patent number: 8785326
    Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Ming Zhang, Lifang Xu
  • Patent number: 8785325
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8784974
    Abstract: Methods for fabricating sub-lithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Publication number: 20140199846
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method may comprise: etching a plurality of first openings in an interlayer dielectric layer on a substrate; forming an opening modifying layer in the plurality of first openings; and etching the opening modifying layer until the substrate is exposed, resulting in a plurality of second openings, wherein the second openings have a depth-to-width ratio greater than that of the first openings. In this way, a deep hole with a relatively large dimension can be formed in silicon oxide by conventional photolithography processes. After that, a film of silicon nitride can be deposited into the hole to achieve a desired CD, and then etched with the fluorocarbon gas(es) to implement an arrangement with a relatively great depth-to-width ratio.
    Type: Application
    Filed: September 5, 2012
    Publication date: July 17, 2014
    Inventor: Lingkuan Meng
  • Patent number: 8778194
    Abstract: A method is described for manufacturing a component having a through-connection. The method includes providing a substrate; forming a trench structure in the substrate, a substrate area which is completely surrounded by the trench structure being produced; forming a closing layer for closing off the trench structure, a cavity girded by the closing layer being formed in the area of the trench structure; removing substrate material from the substrate area surrounded by the closed-off trench structure; and at least partially filling the substrate area surrounded by the closed-off trench structure with a metallic material. A component having a through-connection is also described.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 15, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Yvonne Bergmann
  • Patent number: 8778715
    Abstract: A method of making a neutron detector such as a microstructured semiconductor neutron detector is provided. The method includes the step of providing a particle-detecting substrate having a surface and a plurality of cavities extending into the substrate from the surface. The method also includes filling the plurality of cavities with a neutron-responsive material. The step of filling including the step of centrifuging nanoparticles of the neutron-responsive material with the substrate for a time and a rotational velocity sufficient to backfill the cavities with the nanoparticles. The material is responsive to neutrons absorbed, thereby, for releasing ionizing radiation reaction products.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 15, 2014
    Assignee: Radiation Detection Technologies, Inc.
    Inventors: Steven L. Bellinger, Ryan G. Fronk, Douglas S. McGregor
  • Patent number: 8778805
    Abstract: In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 15, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Seiya Fujii
  • Patent number: 8772168
    Abstract: Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: July 8, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Ruilong Xie, Balasubramanian Pranatharthi Haran, David V. Horak, Su Chen Fan
  • Patent number: 8772180
    Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ya Ou, Shom Ponoth, Terry A. Spooner
  • Patent number: 8765615
    Abstract: A quart resonator for use in lower frequency applications (typically lower than the higher end of the UHF spectrum) where relatively thick quartz members, having a thickness greater than ten microns, are called for.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: July 1, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: David T. Chang, Frederic P. Stratton, Hung Nguyen, Randall L. Kubena
  • Patent number: 8765609
    Abstract: A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: July 1, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee, Wayne B. Grabowski
  • Patent number: 8765549
    Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Shin-Puu Jeng, Der-Chyang Yeh, Shang-Yun Hou, Wen-Chih Chiou
  • Patent number: 8765608
    Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 8765555
    Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Damon E. Van Gerpen
  • Patent number: 8759214
    Abstract: A method for anisotropically plasma etching a semiconductor wafer is disclosed. The method comprises supporting a wafer in an environment operative to form a plasma, such as a plasma reactor, and providing an etching mixture to the environment. The etching mixture comprises at least one etch component, at least one passivation component, and at least one passivation material removal component.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: June 24, 2014
    Assignee: Radiation Watch Limited
    Inventor: Russell Morgan
  • Patent number: 8759222
    Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: June 24, 2014
    Assignee: Sony Corporation
    Inventors: Tsutomu Shimayama, Takatoshi Kameshima, Masaki Okamoto
  • Patent number: 8759983
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Kazuyuki Higashi
  • Patent number: 8759223
    Abstract: A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: June 24, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kedar Sapre, Jing Tang, Ajay Bhatnagar, Nitin Ingle, Shankar Venkataraman
  • Patent number: 8753912
    Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: William Graham, Supratik Guha, Oki Gunawan, George S. Tulevski, Kejia Wang, Ying Zhang
  • Patent number: 8753966
    Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 17, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jum-Yong Park, Jong-Han Shin
  • Patent number: 8748261
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kei Takehara
  • Patent number: 8748280
    Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Gordon Haller