Compound Semiconductor Patents (Class 438/718)
  • Patent number: 6613681
    Abstract: Organic etch residues are often left within vias formed by etching through resist masks. Since the etch is designed to expose an underlying metal layer and is directional in order to produce vertical via sidewalls, the residue often incorporates metal. The present invention discloses a method of removing such etch residues while passivating exposed metal, including exposing the residue to ammonia. In the disclosed embodiment, ammonia and oxygen are mixed in a plasma step, such that the resist can be burned off at the same time as the residue treatment. The residue can thus be easily rinsed away.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Larry Hillyer, Max F. Hinerman
  • Patent number: 6613443
    Abstract: The present invention provides a silicon nitride ceramic substrate composed of a silicon nitride sintered body in which maximum size of pore existing in grain boundary phase of the sintered body is 0.3 &mgr;m or less, and having a thermal conductivity of 50 W/mK or more and a three point bending strength of 500 MPa or more, wherein a leak current is 1000 nA or less when an alternative voltage of 1.5 kV-100 Hz is applied to a portion between front and back surfaces of the silicon nitride sintered body under conditions of a temperature of 25° C. and a relative humidity of 70%. According to the above structure of the present invention, there can be provided a silicon nitride ceramic substrate capable of effectively suppressing a leak current generation when the above substrate is assembled into various power modules and circuit boards, and capable of greatly improving insulating property and operative reliability of power modules in which output power and capacity are greatly increased.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: September 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michiyasu Komatsu, Haruhiko Yamaguchi, Takayuki Naba, Hideki Yamaguchi
  • Patent number: 6613679
    Abstract: A method for fabricating a semiconductor device of the present invention comprises the steps of: a) depositing a masking film on a first compound semiconductor layer formed on a semiconductor substrate; b) patterning the masking film so that the film has an opening; c) etching away at least an uppermost part of the first semiconductor layer, which part is located inside the opening and includes a degraded layer formed in the step a) or b), using a first etchant and the masking film; and d) patterning the first semiconductor layer by etching away another part of the first layer using a second etchant and the masking film. That another part is located inside the opening and does not include the uppermost part with the degraded layer. The second etchant allows for etching the first layer at a rate lower than a rate realized by the first etchant.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: September 2, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toyoji Chino
  • Patent number: 6602432
    Abstract: A high-speed operation of an electroabsorption modulator is intended. A p-InGaAs contact layer 9 is formed not only in an optical modulation region MA but also in an optical coupling region CA, and an AlInAs oxide layer 7 is disposed in p-InP cladding layers 5 and 8 in a mesa MS portion of the optical coupling region CA.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: August 5, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Matsuyama
  • Patent number: 6599843
    Abstract: Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one mask material is a monocrystalline III-V semiconductor material. This makes possible an easy in-situ removal of the mask from the semiconductor material, which in turn makes possible the growing of additional layers.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: July 29, 2003
    Assignee: Infineon Technologies AG
    Inventors: Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Patent number: 6592771
    Abstract: A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polycrystalline silicon on the substrate is etched in vapor phase using reaction seeds or precursors thereof generated by contacting a reaction gas such as CF4 with a heated catalyst of for example tungsten.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: July 15, 2003
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Patent number: 6592770
    Abstract: This invention relates to a method of heating an insulating layer, such as is found in semiconductor devices, in which a formation has been etched through a layer of resist comprising reactive etching the resist, inhibiting absorption of or removing water vapor and/or oxygen at the exposed surfaces of the etched formation and filling the formation with conductive metal in the absence of said water vapor and/or oxygen.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: July 15, 2003
    Assignee: Trikon Holdings Limited
    Inventor: Christopher David Dobson
  • Patent number: 6589447
    Abstract: Provided is a compound semiconductor single crystal and a fabrication process for a compound semiconductor device capable of forming a prescribed pattern without requirement of many steps. A group V element component in a III-V compound semiconductor single crystal or a group VI element component in the II-VI compound semiconductor single crystal is reduced less than a composition ratio expressed by a chemical formula of a corresponding compound semiconductor single crystal in a pattern-shaped portion.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: July 8, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Junya Ishizaki, Nobuhiko Noto
  • Patent number: 6589805
    Abstract: A vertical cavity surface emitting laser (VCSEL) structure and fabrication method therefor are described in which a subsurface air, gas, or vacuum current confinement method is used to restrict the area of electrical flow in the active region. Using vertical hollow shafts to access a subsurface current confinement layer, a selective lateral etching process is used to form a plurality of subsurface cavities in the current confinement layer, the lateral etching process continuing until the subsurface cavities laterally merge to form a single subsurface circumferential cavity that surrounds a desired current confinement zone. Because the subsurface circumferential cavity is filled with air, gas, or vacuum, the stresses associated with oxidation-based current confinement methods are avoided. Additionally, because the confinement is achieved by subsurface cavity structures, overall mechanical strength of the current-confining region is maintained.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: July 8, 2003
    Assignee: Gazillion Bits, Inc.
    Inventors: Zuhua Zhu, Shih-Yuan Wang
  • Patent number: 6576113
    Abstract: By using electron beam lithography, chemically assisted ion beam etching, and electroplating, high aspect ratio magnetic columns, 60 nm-170 nm in diameter, which are embedded in an aluminum-gallium-oxide/gallium-arsenide (Al0.9Ga0.1)203/GaAs heterostructured substrate, are fabricated. Storage of data in electroplated Ni columns is realized in the form of tracks 0.5 &mgr;m and 0.25 &mgr;m in the down-track direction, and 1 &mgr;m in the cross-track direction, corresponding to areal densities of 1.3 and 2.6 Gbits/in2 respectively. The fabrication of patterned media samples, using dry etching and oxidation of AlGaAs, and electrodeposition of Ni into GaAs substrate is realized.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 10, 2003
    Assignee: California Institute of Technology
    Inventors: Axel Scherer, Joyce Wong
  • Publication number: 20030092279
    Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chia-Lin Hsu
  • Patent number: 6551943
    Abstract: A post-etch clean up process for OSG. After the trench (112)/via (114) etch in a dual damascene process, a wet chemistry comprising HF and H2O2 is used to remove residues without etching or damaging the OSG film in the ILD (108) or IMD (110).
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Mona M. Eissa, Troy A. Yocum
  • Patent number: 6544863
    Abstract: A method for fabricating semiconductor wafers as multiple-depth structure (i.e., having portions of varying height). The method includes patterning a first substrate and bonding a second substrate to the first. This process creates a subsurface patterned layer. Portions of the second substrate may then be etched, exposing the subsurface patterned layer for selective processing. For example, the layered structure may then be repeatedly etched to produce a multiple depth structure. Or, for example, exposed portions of the first substrate may have material added to them to create multiple-depth structures. This method of fabrication provides substantial advantages over previous methods.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: April 8, 2003
    Assignee: Calient Networks, Inc.
    Inventors: John M. Chong, Paul Waldrop, Tim Davis, Scott Adams
  • Publication number: 20030054659
    Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Therefore, a circuit device and a method for fabricating the same according to the invention solves the above-described and other problems by the structure, wherein an insulation resin sheet in which the first conductive layer 3 and the second conductive layer 4 are adhered to each other by insulation resin 2 is used, the first conductive path layer 5 is formed by the first conductive layer 3, the second conductive path layer 6 is formed by the second conductive layer 4, and both of the conductive path layers are connected by multi-layer connecting means 12.
    Type: Application
    Filed: June 14, 2002
    Publication date: March 20, 2003
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Patent number: 6524899
    Abstract: A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: February 25, 2003
    Assignee: TRW Inc.
    Inventors: Ronald W. Grundbacher, Richard Lai, Mark Kintis, Michael E. Barsky, Roger S. Tsai
  • Patent number: 6514832
    Abstract: A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor layer for impressing voltage on the active layer, and a concave portion which is cut from around the first electrode in a direction of the second semiconductor layer and the active layer and which subdivides the second semiconductor layer and the active layer to which the first electrode is connected as a region which functions as a Gunn diode. Since etching for defining a region that is to function as a Gunn diode is performed by self-alignment dry etching utilizing electrode layers formed above this region as masks, variations in characteristics are restricted.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: February 4, 2003
    Assignee: New Japan Radio Co., Ltd.
    Inventors: Atsushi Nakagawa, Kenichi Watanabe
  • Publication number: 20030017710
    Abstract: A method of forming a sloped staircase STI structure, comprising the following steps. a) A substrate having an upper surface is provided. b) A patterned masking layer is formed over the substrate to define an STI region. The patterned masking layer having exposed sidewalls. c) The substrate is etched a first time through the masking layer to form a first step trench within the STI region. The first step trench having exposed sidewalls. d) Continuous side wall spacers are formed on the exposed patterned masking layer and first step trench sidewalls. e) The substrate is etched a second time using the masking layer and the continuous sidewall spacers as masks to form a second step trench within the STI region. The second step trench having exposed sidewalls. f) Second side wall spacers are formed on the second step trench sidewalls. g) Steps e) and f) are repeated x more times to create x+2 total step trenches and x+2 total side wall spacers on x+2 total step trench sidewalls.
    Type: Application
    Filed: July 19, 2001
    Publication date: January 23, 2003
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Pan Yang, James Lee Yong Meng, Leung Ying Keung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan
  • Patent number: 6503840
    Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: January 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar, Kai Zhang, Richard Schinella, Philippe Schoenborn
  • Patent number: 6503769
    Abstract: A semiconductor device includes a substrate, a multi-layer structure provided on the substrate, a first-conductive-type etch stop layer of a III nitride provided on the multi-layer structure, and a second-conductive-type first semiconductor layer of a III nitride provided on the etch stop layer. A molar fraction of Al is lower in a composition of the III nitride included in the first semiconductor layer than in a composition of the III nitride included in the etch stop layer.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: January 7, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Shinji Nakamura, Masaaki Yuri, Kenji Orita
  • Patent number: 6503844
    Abstract: A notched gate configuration for high performance integrated circuits. The method of producing the notched gate configuration comprises forming a dielectric substrate and depositing a gate oxide layer, a conductive film layer, and a metal silicide layer over the gate oxide layer to form a conductive stack. A patterned silicon nitride mask layer is deposited over the conductive stack and over-etched to form a small notch in the metal silicide layer at each side of the patterned silicon nitride mask layer. This over-etching causes indentions to form in the conductive stack to result in decreased gate overlap between the gate and a source and drain which are later formed.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: January 7, 2003
    Assignee: Infineon Technologies, AG
    Inventor: Giuseppe Curello
  • Patent number: 6492309
    Abstract: A homogeneous compositions containing a fluorinated solvent, hydrogen fluoride, and an optional co-solvent, and the use of these compositions for etching of microelectromechanical devices is described.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: December 10, 2002
    Assignee: 3M Innovative Properties Company
    Inventors: Frederick E. Behr, Paul E. Rajtar, Lawrence A. Zazzera, Michael J. Parent, Silva K. Theiss, Billy L. Weaver
  • Publication number: 20020182873
    Abstract: Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one mask material is a monocrystalline III-V semiconductor material. This makes possible an easy in-situ removal of the mask from the semiconductor material, which in turn makes possible the growing of additional layers.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 5, 2002
    Inventors: Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Publication number: 20020182879
    Abstract: A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.
    Type: Application
    Filed: January 18, 2002
    Publication date: December 5, 2002
    Inventors: Bernd Borchert, Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Patent number: 6482747
    Abstract: Plasma treatment apparatus and method in which an influence on the treatment characteristics of reaction products in plasma treatment such as etching is offset, thereby enabling uniform treatment characteristics to be obtained in the plane of a substrate are provided. In a plasma treatment method of treating a substrate to be processed by using a gas plasma via a mask in a treatment chamber, plasma treatment is performed while optimizing an amount of deposition of a side wall protection layer, equalizing the optimized deposition amount in the center of the substrate and that in a peripheral part, and maintaining the uniformity in the plane of the side wall protection layer.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: November 19, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kazue Takahashi, Saburo Kanai, Yoshiaki Satou, Takazumi Ishizu
  • Publication number: 20020168863
    Abstract: In a process for treating a workpiece such as a semiconductor wafer, a processing fluid is selectively applied or excluded from an outer peripheral margin of at least one of the front or back sides of the workpiece. Exclusion and/or application of the processing fluid occurs by applying one or more processing fluids to the workpiece while the workpiece and a reactor holding the workpiece are spinning. The flow rate of the processing fluids, fluid pressure, and/or spin rate are used to control the extent to which the processing fluid is selectively applied or excluded from the outer peripheral margin.
    Type: Application
    Filed: June 26, 2002
    Publication date: November 14, 2002
    Applicant: Semitool, Inc.
    Inventors: Brian Aegerter, Curt T. Dundas, Michael Jolley, Tom L. Ritzdorf, Steven L. Peace, Gary L. Curtis, Raymon F. Thompson
  • Publication number: 20020164885
    Abstract: Transistor gate linewidths can be made to be effectively smaller by etching a notch at the bottom of the gate to reduce the effective linewidth. This can be done by etching at a layer interface, such as a silicon-germanium interface. in an over-etch step.
    Type: Application
    Filed: May 7, 2001
    Publication date: November 7, 2002
    Inventors: Thorsten B. Lill, Jitske Kretz
  • Patent number: 6458254
    Abstract: A method of making a low-resistance electrical contact between a metal and a layer of p-type CdTe surface by plasma etching and reactive ion etching comprising: a) placing a CdS/CdTe layer into a chamber and evacuating said chamber; b) backfilling the chamber with Argon or a reactive gas to a pressure sufficient for plasma ignition; and c) generating plasma ignition by energizing a cathode which is connected to a power supply to enable the plasma to interact argon ions alone or in the presence of a radio-frequency DC self-bias voltage with the p-CdTe surface.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: October 1, 2002
    Assignee: Midwest Research Institute
    Inventor: Timothy A. Gessert
  • Patent number: 6444540
    Abstract: First, a substrate, on which a plurality of semiconductor devices is formed, is provided. Next, a first etching treatment is carried out to the substrate with a first etching gas comprising CF4 to form a base trench having a rounded-off upper edge or tapered upper edge. A second etching treatment is carried out to the substrate to form a trench region at the base trench so that the trench region has a rounded-off upper edge. And then, an insulating layer is formed on the substrate to fill up the trench region therewith.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: September 3, 2002
    Assignee: Oki Electric Industry Co., LTD
    Inventors: Shinzi Kawada, Hiroyuki Kawano
  • Patent number: 6383918
    Abstract: A method is provided for reducing contact resistances in semiconductors. In the use of fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching, with the silicon dioxide(SiO2)/silicon nitride(Si3N4)/silicide(TiSix) layers, polymerization effects have been discovered to be crucial. The process includes using a high etch selective chemistry, to remove SiO2 first, then switching to another chemistry with high selectivity of Si3N4-to-TiSix. To obtain good etch selectivity of SiO2-to-Si3Nx, fluorocarbon plasmas containing high C/F ratio are employed. This results in the information of reactive unsaturated polymers which stick easily to contact sidewalls and bottoms. Fluorine from the polymer was discovered to severely degrade the etch selectivity of Si3N4-to-TiSix. Different polymer removing methods to restore etch selectivity of Si3N4-to-TiSix, are provided which can be applied to any highly selective etching of oxide versus nitride.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 7, 2002
    Assignee: Philips Electronics
    Inventors: Victor Ku, Delbert Parks
  • Publication number: 20020025680
    Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.
    Type: Application
    Filed: October 15, 2001
    Publication date: February 28, 2002
    Inventor: Daryl C. New
  • Publication number: 20020022375
    Abstract: A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 21, 2002
    Inventor: O-Sung Kwon
  • Patent number: 6346485
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 12, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6337284
    Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: January 8, 2002
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Kwangjo Hwang, Changwook Han
  • Publication number: 20010030026
    Abstract: A method of low-damage, anisotropic etching of substrates including mounting the substrate upon a mechanical support located within an ac or dc plasma reactor. The mechanical support is independent of the plasma reactor generating apparatus and capable of being electrically biased. The substrate is subjected to a plasma of low-energy electrons and a species reactive with the substrate. An additional structure capable of being electrically biased can be placed within the plasma to control further the extraction or retardation of particles from the plasma.
    Type: Application
    Filed: May 15, 2001
    Publication date: October 18, 2001
    Inventors: Kevin P. Martin, Harry P. Gillis, Dmitri A. Choutov
  • Patent number: 6294475
    Abstract: A method of processing III-Nitride epitaxial layer system on a substrate. The process includes exposing non-c-plane surfaces of the III-nitride epitaxial layer system, for example by etching to a selected depth or cleaving, and crystallographical etching the epitaxial layer system in order to obtain crystallographic plane surfaces. In an exemplary embodiment, the III-Nitride epitaxial layer system includes GaN. In accordance with one aspect of the exemplary embodiment, the etching step includes reactive ion etching in a chlorine-based plasma, PEC etching in a KOH solution or cleaving, and the crystallographical etching step includes immersing the epitaxial layer system in a crystallographic etching chemical, such as phosphoric acid, molten KOH, KOH dissolved in ethylene glycol, sodium hydroxide dissolved in ethylene glycol, tetraethyl ammonium hydroxide, or tetramethyl ammonium hydroxide.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: September 25, 2001
    Assignee: Trustees of Boston University
    Inventors: E. Fred Schubert, Dean A. Stocker
  • Publication number: 20010003677
    Abstract: A method of making a low-resistance electrical contact between a metal and a layer of p-type CdTe surface by plasma etching and reactive ion etching comprising:
    Type: Application
    Filed: September 25, 1997
    Publication date: June 14, 2001
    Inventor: TIMOTHY A. GESSERT
  • Patent number: 6221783
    Abstract: There is disclosed a method of manufacturing a heterojunction bipolar transistor.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: April 24, 2001
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Ho Park, Tae Woo Lee, Moon Pyung Park, Chul Soon Park
  • Patent number: 6200907
    Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: March 13, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
  • Patent number: 6187677
    Abstract: Integrated circuitry and methods of forming integrated circuitry are described. In one aspect, a hole is formed in a semiconductor wafer. In a preferred implementation, the hole extends through the entire wafer. Subsequently, conductive material is formed within the hole and interconnects with integrated circuitry which is formed proximate at least one of a front and back wafer surface. According to one aspect of the invention, integrated circuitry is formed proximate both front and back surfaces. In a preferred implementation, a plurality of holes are formed through the wafer prior to formation of the integrated circuitry. In accordance with a preferred implementation, formation of the conductive material within the hole takes place through formation of a first material within the hole. A second material is formed over the first material, with at least the second material being electrically conductive.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: February 13, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Kie Y. Ahn
  • Patent number: 6168726
    Abstract: A process for etching an oxidized organo-silane film exhibiting a low dielectric constant and having a most preferred atomic composition of 52% hydrogen, 8% carbon, 19% silicon, and 21% oxygen. The process of etching deep holes in the organo-silane film while stopping on a nitride or other non-oxide layer is preferably performed in an inductively coupled high-density plasma reactor with a main etching gas mixture of a fluorocarbon, such as C4F8, and argon while the pedestal electrode supporting the wafer is RF biased. For very deep and narrow holes, oxygen or nitrogen may be added to volatize carbon. In an integrated process in which an oxygen plasma is used either for the film etching or for post-etch treatments such as ashing or nitride removal, the oxygen plasma should be excited only when no RF bias is applied to the pedestal electrode, and thereafter the sample should be annealed in an inert environment to recover the low dielectric constant.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: January 2, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Zongyu Li, Jian Ding, Mehul Naik
  • Patent number: 6133145
    Abstract: A process for fabricating an aluminum based interconnect structure, using a plasma treated photoresist shape as an etch mask, has been developed. The process features treating a photoresist shape, to be used as an etch mask during RIE patterning procedures, in a nitrogen containing plasma. The plasma nitrogen treated photoresist shape is eroded at a decreased rate, when compared to counterpart non-treated photoresist shapes, during the RIE procedure used to fabricate the aluminum based interconnect structure. The increased etch rate ratio, between layers used for the interconnect structure, and the plasma treated photoresist shape, allows thinner photoresist shapes to be used, and therefore allows narrower lines and spaces to be achieved.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: October 17, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chao-Cheng Chen
  • Patent number: 6127274
    Abstract: There is disclosed a process for producing electronic devices from a semiconductor wafer. The process comprises forming separation regions with a spatial pattern on the semiconductor wafer to provide separation between electronic devices, and depositing a conductive contact layer on the wafer and patterning the contact layer in such a way that conductive terminals extend from the front side of the wafer over at least part of the cross section of the patterned separation regions. The terminals are bared by removing material of the wafer in the semiconductor regions starting from the backside of the wafer, and the terminals of adjacent electronic devices are separated.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: October 3, 2000
    Assignee: Micronas Intermetall GmbH
    Inventors: Guenter Igel, Martin Mall
  • Patent number: 6103543
    Abstract: A base layer of electode made of at least a metal selected from V, Nb, and Zr, or an alloy containing such metal on an n-type GaN compound semiconductor layer. Further, a main electrode layer made of other metal is formed on the base layer. Then, an n electrode is formed by subjecting the semiconductor layer, the base layer, and the main electrode layer to a heat treatment.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: August 15, 2000
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Naoki Shibata
  • Patent number: 6063300
    Abstract: A method of manufacturing a semiconductor device, including the steps of: cooling a semiconductor wafer to a predetermined temperature, the semiconductor wafer being mounted on a stage provided with cooling means and having a thin oxide film on a surface thereof; supplying energy to gas containing hydrogen and water vapor to excite the gas into a plasma state; adding nitrogen fluoride downstream into a flow of the gas in the plasma state; and introducing a flow of the gas, including the nitrogen fluoride, to the semiconductor wafer to etch the thin oxide film while maintaining the semiconductor wafer at the predetermined temperature.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: May 16, 2000
    Assignee: Fujitsu Limited
    Inventors: Miki Suzuki, Jun Kikuchi, Mitsuaki Nagasaka, Shuzo Fujimura
  • Patent number: 6051506
    Abstract: A method for forming a T-shape gate having a length below 0.25 .mu.m for use in ultra-frequency semiconductor devices is disclosed. The insulating layer is side-etched by using the gate mask pattern through a conventional photolithography, the length of the insulating layer being controlled by the side-etching. The length of the insulating layer determines the length of the T-shape gate for allowing the T-shape gate having the length below 0.25 .mu.m to be obtained.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: April 18, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Song-Kang Kim, Hyun-Ryong Cho, Sung-Moo Lim, Duck-Hyoung Lee
  • Patent number: 6051503
    Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: April 18, 2000
    Assignee: Surface Technology Systems Limited
    Inventors: Jyoti Kiron Bhardwaj, Huma Ashraf, Babak Khamsehpour, Janet Hopkins, Alan Michael Hynes, Martin Edward Ryan, David Mark Haynes
  • Patent number: 6013582
    Abstract: The present disclosure pertains to a method for plasma etching a semiconductor patterning stack. The patterning stack includes at least one layer comprising either a dielectric-comprising antireflective material or an oxygen-comprising material. In many instances the dielectric-comprising antireflective material will be an oxygen-comprising material, but it need not be limited to such materials. In one preferred embodiment of the method, the chemistry enables the plasma etching of both a layer of the dielectric-comprising antireflective material or oxygen-comprising material and an adjacent or underlying layer of material. In another preferred embodiment of the method, the layer of dielectric-comprising antireflective material or oxygen-comprising material is etched using one chemistry, while the adjacent or underlying layer is etched using another chemistry, but in the same process chamber.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: January 11, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Pavel Ionov, Sung Ho Kim, Dean Li
  • Patent number: 6010967
    Abstract: In but one aspect of the invention, a plasma etching method includes forming polymer material over at least some internal surfaces of a dual powered plasma etch chamber while first plasma etching an outer surface of a semiconductor wafer received by a wafer holder within the chamber. After the first plasma etching, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder effective to produce an ac peak voltage at the wafer surface of greater than zero and less than 200 Volts. In one implementation, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder of greater than zero Watts and less or equal to about 1 Watt/cm.sup.2 of wafer surface area on one side.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: January 4, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Donohoe, Richard L. Stocks
  • Patent number: 5968845
    Abstract: An etching method for performing dry-etching on a III-V group compound semiconductor or a II-VI group compound semiconductor in a dry-etching apparatus comprising a plasma source for creating a plasma of density of about 10.sup.10 cm.sup.-3 or greater, using a mixed gas containing a gas including a halogen element and a gas including nitrogon. The etching conditions are as follows: (a flow rate of the gas containing said halogen gas)/(a flow rate of said nitrogen gas) .gtoreq.1; and an internal pressure during etching reaction is about 1 mTorr or greater.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: October 19, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toyoji Chino, Yasuhito Kumabuchi, Isao Kidoguchi, Hideto Adachi
  • Patent number: 5952245
    Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: September 14, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yoshimi Torii, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara