Abstract: A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.

Abstract: A plasma processing apparatus used in semiconductor device manufacturing includes a process kit formed of insulating materials such as quartz and coated with a Y2O3 coating. The Y2O3 coating is a thin film formed using suitable CVD or PVD operations. The Y2O3 coating is resistant to degradation in fluorine etching chemistries commonly used to etch silicon in semiconductor manufacturing. The plasma processing apparatus may be used in etching, stripping and cleaning operations. Also provided in another embodiment is a plasma processing apparatus having a quartz process kit coated with a sapphire-like film.

Abstract: Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusion portion of the silicon film, forming a dummy film over the silicon film, etching the dummy film so that the dummy film is partially remained on sidewalls of the protrusion portion, etching the silicon film using the remaining dummy film to form a gate electrode, and performing ion implantation into the semiconductor substrate to form source/drain regions.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: An exposure mask and a method of forming a contact hole of a semiconductor device using the same, in which micro patterns can be formed are disclosed herein. In an aspect, an exposure mask method includes a mask substrate, a light-shield pattern formed on the mask substrate, and a transparent pattern in which a plurality of patterns, which are limited to the light-shield pattern and have different short-direction widths and long-direction widths, form a group which is repeatedly arranged. Accordingly, micro photoresist patterns can be formed uniformly.

Abstract: A translucent solar cell and a manufacturing method thereof are provided. The translucent solar cell at least includes a substrate, a front electrode layer, a photoconductive layer, and a back electrode layer stacked in order. Therein, a plurality of apertures are formed on the front electrode layer. In addition, a plurality of light-transmissive regions are formed on the back electrode layer and further extended in a depth direction so as to reach the plurality of apertures on the front electrode layer. Thus, the projected area of each light-transmissive region is within and smaller than that of the corresponding aperture.

Abstract: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Abstract: Disclosed is a plasma processing method that excels in mass production consistency as it suppresses the flaking of a reaction product deposited on a portion outside the effective range of a Faraday shield in a vacuum vessel. The plasma processing method, which plasma-processes a sample having a layer made of an etch-resistant material by using a plasma processing apparatus having a discharger and a processor, includes a first step of performing an aging process that is to be performed before etching the sample, a second step of performing etching by plasma-processing the layer that is made of an etch-resistant material and formed on the sample, a third step of stabilizing a film deposited on the inner wall of a chamber forming the processor by performing plasma processing after the second step, and an additional step of repeating the second step and the third step.

Abstract: The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.

Abstract: A method for repairing damage to a silicon based low-k dielectric layer with organic compounds, where damage replaces a methyl attached to silicon with a hydroxyl attached to silicon is provided. A repair gas comprising CH4 gas is provided. The repair gas is formed into a plasma, while maintaining a pressure below 50 mTorr. Hydroxyl attached to silicon is replaced with methyl from the plasma formed by the repair gas.

Abstract: A method of manufacturing a solar cell module, including: forming a laminated body including a first protective member, a first sealing member having a first melting point, a plurality of solar cells, a second sealing member having a second melting point higher than the first melting point, and the second protective member; heating the first sealing member to a temperature equal to or higher than the first melting point but lower than the second melting point; and heating the second sealing member to a temperature equal to or higher than the second melting point. In forming the laminated body, the second sealing member is arranged to form a surface including a plurality of convex portions faces the first sealing member.

Abstract: A method for manufacturing a semiconductor device includes: mounting a wafer having an exposed silicon nitride film, on an electrode received in a plasma chamber; dry-cleaning the chamber to remove reaction products accumulated on the wall and ceiling of the chamber, anisotropic-etching the silicon nitride film and an underlying silicon film for patterning; and removing the wafer from the chamber. The method repeats the treatment for a number of semiconductor wafers.

Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric layer having a plurality of contact holes over a substrate, forming a conductive layer by filling the contact holes to cover the interlayer dielectric layer, performing a first main etch process to partially etch the conductive layer to form a first conductive layer, performing a second main etch process to etch the first conductive layer using an etch gas having a slower etch rate with respect to the first conductive layer than an etch gas used in the first main etch process until an upper surface of the interlayer dielectric layer is exposed to form a second conductive layer, and performing an over-etch process to etch a certain portion of the second conductive layer, and at the same time, to etch a certain portion of the interlayer dielectric layer to form a landing plug.

Abstract: A method of manufacturing a semiconductor device in which a source contact plug and a drain contact plug are formed. The method includes the steps of etching part of the semiconductor substrate to form a step, thus forming an overlay vernier, and forming a hard mask on the step so that the step is maintained.

Abstract: A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x?890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5?x?22.1).

Abstract: A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.

Abstract: A semiconductor device manufacturing method includes: forming an etching mask having a predetermined circuit pattern on a surface of an etching target film disposed on a semiconductor substrate; etching the etching target film through the etching mask to form a groove or hole in the etching target film; removing the etching mask by a process including at least a process using an ozone-containing gas; and recovering damage of the etching target film caused before or in said removing the etching mask, while supplying a predetermined recovery gas.

Abstract: A method for fabricating a recess pattern in a semiconductor device includes defining an active region on a substrate, forming a first mask pattern over the active region in a line type structure, forming a second mask pattern comprising an open region over the active region, the open region exposing a portion where the active region and the first mask pattern intersect, and etching the active region of the substrate exposed by the first and second mask patterns to form recess patterns.

Abstract: A processing method includes a silicon oxide etching process of performing a plasma etching on a target layer mainly made up of silicon, a silicon oxide layer formed on the target layer and a target object having a previously patterned resist layer formed on the silicon oxide layer, the plasma etching of the silicon oxide layer being performed by using the resist layer as a mask; a deposits removing process of removing deposits generated in the silicon oxide etching process and stuck to the target object; and a silicon etching process of performing a plasma etching on the target layer by a plasma generated from a processing gas containing SF6, O2 and SiF4 while using the silicon oxide layer as a mask.

Abstract: An apparatus for controlling a plasma etching process includes plasma control structure that can vary a size of a plasma flow passage, vary a speed of plasma flowing through the plasma flow passage, vary plasma concentration flowing through the plasma flow passage, or a combination thereof.

Abstract: A method of dry developing a multi-layer mask having a silicon-containing anti-reflective coating (ARC) layer on a substrate is described. The method comprises forming the multi-layer mask on the substrate, wherein the multi-layer mask comprises a lithographic layer overlying the silicon-containing ARC layer. A feature pattern is then formed in the lithographic layer using a lithographic process. Thereafter, the feature pattern is transferred from the lithographic layer to the silicon-containing ARC layer using a dry plasma etching process, wherein the offset in the critical dimension (CD) bias is reduced between nested structures and isolated structures.

Abstract: A cleaning solution and methods of fabricating semiconductor devices using the same are provided. A cleaning solution used for cleaning a silicon surface and methods of fabricating a semiconductor device using the same are also provided. The cleaning solution may include 0.01 to 1 wt % of fluoric acid, 20 to 50 wt % of oxidizer and 50 to 80 wt % of water. The cleaning solution may further include 1 to 20 wt % of acetic acid. The cleaning solution may be used to clean a silicon surface exposed during fabrication processes of a semiconductor device. The cleaning solution may reduce damage of other material layers (e.g., a tungsten layer or a silicon oxide layer) and enable the silicon surface to be selectively etched.

Abstract: A layer system is described including a silicon layer and a passivation layer which is applied at least regionally to the silicon layer's surface, the passivation layer having a first, at least largely inorganic partial layer and a second partial layer, the second partial layer being made of an organic compound including silicon or containing such a material. In particular, the second partial layer is structured in the form of a “self-assembled monolayer.” Furthermore, a method is described for creating a passivation layer on a silicon layer, a first, inorganic partial layer being created on the silicon layer and a second partial layer, containing an organic compound including silicon or being made thereof, being created at least in certain areas on the first partial layer. Both partial layers form the passivation layer. The described layer system or the described method is particularly suited for creating self-supporting structures in silicon.

Abstract: To form an isolation structure in a semiconductor substrate, at least two trenches are formed with a rib therebetween in the semiconductor substrate, and then the semiconductor material in the area of the trenches and particularly the rib is converted to an electrically insulating material. For example, this is accomplished by thermal oxidation of silicon semiconductor material of the rib.

Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.

Abstract: A method for manufacturing a substrate for a liquid discharge head provided with a silicon substrate and a supply port, including: providing the silicon substrate having an insulating layer on a first surface and an etching mask layer having a plurality of apertures on a second surface which is a rear surface of the first surface, wherein the insulating layer is provided in a region ranging from a position opposing the apertures to a position opposing a portion between the adjacent apertures of the mask layer; and forming holes by etching a silicon part of the silicon substrate so that an etched region reaches a portion of the insulating layer opposing the apertures, wherein the silicon wall provided between the adjacent holes is etched so that the portion in the first surface side thereof can be thinner than the portion in the second surface side thereof.

Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.

Abstract: A method of making a microstructure with thin wall portions (T1-T3) includes a step of performing a first etching process to a material substrate having a laminate structure including a first conductive layer (11) and a second conductive layer (12) having a thickness of the thin wall portions (T1-T3), where the etching is performed from the side of the first conductive layer (11) thereby forming in the second conductive layer (12) pre thin wall portions (T1?-T3?) which has a pair of side surfaces apart from each other in an in-plane direction of the second conductive layer (12) and contact the first conductive layer (11). The method also includes a step of performing a second etching process from the side of the first conductive layer (11) for removing part of the first conductive layer (11) contacting the pre thin wall portions (T1?-T3?) to form the thin wall portions.

Abstract: The invention provides a process for texturing a surface of a semiconductor material, the process comprising: applying a layer of a protective substance on said surface wherein said layer is sufficiently thin that it has a plurality of apertures therethrough; and contacting said layer and said semiconductor material with an etchant capable of etching said semiconductor material faster than said protective substance, said etchant making contact with said semiconductor material at least through said apertures, for a time and under conditions in which said semiconductor material is etched by said etchant in the vicinity of said apertures to produce a textured surface on said semiconductor material, but said protective substance is substantially unetched.

Abstract: Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.

Abstract: A plasma etching apparatus is arranged to perform main etching for etching a poly-crystalline silicon film by use of Cl2/SF6/N2 plasma obtained by exciting Cl2 gas, SF6 gas, and N2 gas, and over etching for etching the poly-crystalline silicon film by use of Cl2/HBr/CF4 plasma obtained by exciting Cl2 gas, HBr gas, and CF4 gas. In the main etching, N2 gas is added to suppress formation of roughness on a poly-crystalline silicon surface and attain a sufficient etching rate.

Abstract: A method and a device suitable for implementing this method for etching a substrate (10), a silicon body in particular, using an inductively coupled plasma (14) are proposed. For this purpose, a radio-frequency electromagnetic alternating field is generated with an ICP source (13), the alternating field generating an inductively coupled plasma (14) of reactive particles in a reactor (15). The inductively coupled plasma (14) arises by the action of the radio-frequency electromagnetic alternating field on a reactive gas. Furthermore, a device is provided with which a plasma power injected into the inductively coupled plasma (14) via the radio-frequency electromagnetic alternating field with the ICP source (13) is capable of being pulsed so that at least from time to time a pulsed radio-frequency power can be injected into the inductively coupled plasma (14) as a pulsed radio-frequency power.

Abstract: The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.

Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

Abstract: The invention relates to a method for making an actuation system for an optical component comprising: etching of a first face of a component, to form pads on it, etching of a second face of the component, to expose a membrane made of the same material as the pads, production of the actuation means of the pads and the membrane.

Abstract: HF-originated radicals generated in a plasma-forming chamber are fed to a treatment chamber via feed holes, while HF gas molecules as the treatment gas are supplied to the treatment chamber from near the radical feed holes to suppress the excitation energy, thereby increasing the selectivity to Si to remove a native oxide film. Even with the dry-treatment, the surface treatment provides good surface flatness equivalent to that obtained by the wet-cleaning which requires high-temperature treatment, and further attains growth of Si single crystal film on the substrate after the surface treatment. The surface of formed Si single crystal film has small quantity of impurities of oxygen, carbon, and the like. After sputtering Hf and the like onto the surface of the grown Si single crystal film, oxidation and nitrification are applied thereto to form a dielectric insulation film such as HfO thereon, thus forming a metal electrode film.

Abstract: Methods for fabrication of high aspect ratio micropillars and nanopillars are described. Use of alumina as an etch mask for the fabrication methods is also described. The resulting micropillars and nanopillars are analyzed and a characterization of the etch mask is provided.

Abstract: In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.

Abstract: An etching method and an etching system are adapted to produce a high etch selectivity for a mask, an excellent anisotropic profile and a large etching depth. An etching system according to the invention comprises a floating electrode arranged vis-à-vis a substrate electrode in a vacuum chamber and held in a floating state in terms of electric potential, a material arranged at the side of the floating electrode facing the substrate electrode to form an anti-etching film and a control unit for intermittently applying high frequency power to the floating electrode.

Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that include flowing a backside process gas between a substrate and a substrate support assembly, and cyclically etching a layer on the substrate.

Abstract: A method for providing substantially similar chamber condition before each wafer process operation in a semiconductor process chamber is provided. The method allows for prevention of transport of particle and metal contamination from chamber surfaces to the processed wafer. The method initiates with depositing a silicon containing layer over an inner surface of an empty semiconductor process chamber. Then, a wafer is introduced into the semiconductor process chamber after depositing the silicon containing layer. Next, a process operation is performed on the wafer. The process operation deposits a residue on the silicon containing layer. Next, an in-situ cleaning process is initiated upon completion of the processing operation and removal of the wafer.

Abstract: Provided herein are methods for preventing the formation and accumulation of surface-associated charges, and deleterious effects associated therewith, during the manufacture of a MEMS device. In some embodiments, methods provided herein comprise etching a sacrificial material in the presence of an ionized gas, wherein the ionized gas neutralizes charged species produced during the etching process and allows for their removal along with other etching byproducts. Also disclosed are microelectromechanical devices formed by methods of the invention, and visual display devices incorporating such devices.

Abstract: The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate.

Abstract: A thin film transistor (TFT) array panel and method of manufacturing the same are provided. The method includes forming a semiconductor layer and an ohmic contact layer over a gate line, forming a conductive layer on the ohmic contact layer, forming a first photosensitive layer pattern on the conductive layer, etching the conductive layer using the first photosensitive layer pattern as an etching mask, etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern, and etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.

Abstract: Etching and protective-film deposition operations E and D are in alternation repeatedly executed on a silicon substrate carried on a platform within a processing chamber. With gas inside the processing chamber having been exhausted to pump down the chamber interior, in the etching operation E, the substrate is etched by supplying etching gas into the chamber and converting it into plasma and applying a bias potential to the platform, and in the protective-film deposition operation D, a protective film is formed on the silicon substrate by supplying protective-film deposition gas into the processing chamber and converting it into plasma. When a predetermined time prior to the close of operations E and D (time intervals indicated by reference marks Ee and De) is reached, the supply of etching or protective-film deposition gas is halted, and the exhaust flow rate of gas exhausted from the chamber is made greater than that previously.

Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh