Electrically Conductive Material (e.g., Metal, Conductive Oxide, Etc.) Patents (Class 438/720)
  • Patent number: 8633117
    Abstract: In one embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines. In another embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, wherein the layer of conductive metal is an intermediate layer in the multi-layer structure, etching the multi-layer structure to expose the conductive metal, sputter etching conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines, forming a liner that surrounds the conductive lines, subsequent to the sputter etching, and depositing a dielectric layer on the multi-layer structure.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Benjamin L. Fletcher, Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 8629063
    Abstract: A method includes forming a cavity in a substrate, depositing a layer of conductive material in the cavity and over exposed portions of the substrate, removing portions of the conductive material to expose portions of the substrate using a planarizing process, and removing residual portions of the conductive material disposed on the substrate using a reactive ion etch (RIE) process.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Danielle L. DeGraw, Candace A. Sullivan
  • Patent number: 8623670
    Abstract: A method of making a thermally-assisted recording (TAR) disk includes etching an initial layer of generally spherically shaped FePt grains encapsulated by shells of graphitic carbon layers. The etching partially or completely removes the carbon layers on the tops of the shells, exposing the FePt grains while leaving carbon segregant material between the FePt grains. Additional Fe, Pt and C are then simultaneously deposited. The additional Fe and Pt grow on the exposed FePt grains and increase the vertical height of the grains, resulting in growth of columnar FePt grains. The additional C forms on top of the grains that together with the intergranular carbon form larger carbon shells. The resulting FePt grains thus have a generally columnar shape with perpendicular magnetic anisotropy, rather than a generally spherical shape. Lateral grain isolation is maintained by the carbon segregant remaining between the grains.
    Type: Grant
    Filed: July 15, 2012
    Date of Patent: January 7, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Oleksandr Mosendz, Simone Pisana, James William Reiner, Franck Dreyfus Rose
  • Patent number: 8623230
    Abstract: The present method relates to processes for the removal of a material from a sample by a gas chemical reaction activated by a charged particle beam. The method is a multiple step process wherein in a first step a gas is supplied which, when a chemical reaction between the gas and the material is activated, forms a non-volatile material component such as a metal salt or a metaloxide. In a second consecutive step the reaction product of the first chemical reaction is removed from the sample.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 7, 2014
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Nicole Auth, Petra Spies, Tristan Bret, Rainer Becker, Thorsten Hofmann, Klaus Edinger
  • Patent number: 8617998
    Abstract: Methods of forming integrated circuit devices utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. A target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is removed to define an opening between the sidewall spacers. The first mask layer is selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. The target material layer is selectively etched using the third pattern as an etching mask.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-ho Min, Seong-soo Lee, Ki-jeong Kim
  • Patent number: 8614151
    Abstract: Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue of C2F4.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: December 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Russell A. Benson, Ted Taylor, Mark Kiehlbauch
  • Patent number: 8609546
    Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: December 17, 2013
    Assignee: Lam Research Corporation
    Inventors: Wonchul Lee, Qian Fu, Shenjian Liu, Bryan Pu
  • Patent number: 8598039
    Abstract: This invention relates to a method and apparatus by integrating semiconductor manufacturing processes of stress free electrochemical copper polishing (SFP), removal of the Tantalum oxide or Titanium oxide formed during SFP process and XeF2 gas phase etching barrier layer Ta/TaN or Ti/TiN process. Firstly, at least portion of plated copper film is polished by SFP. Secondly the barrier metal oxide film formed during SFP process is etched away by etchant. Finally, the barrier layer Ta/TaN or Ta/TiN is removed with XeF2 gas phase etching. The apparatus accordingly consists of three sub systems: stress free copper electropolishing system, barrier layer oxide film removal system and barrier layer Ta/TaN or Ti/TiN gas phase etching system.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 3, 2013
    Assignee: ACM Research (Shanghai) Inc.
    Inventors: Jian Wang, Zhaowei Jia, Junping Wu, Liangzhi Xie, Hui Wang
  • Patent number: 8580675
    Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: James Walter Blatchford, Scott William Jessen
  • Patent number: 8575020
    Abstract: An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: James Walter Blatchford
  • Patent number: 8569179
    Abstract: A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the amorphous carbon organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the amorphous carbon organic hardmask with the plasma, with the amorphous carbon organic hardmask being at a temperature in excess of 200° C., to remove the amorphous carbon organic hardmask without substantially harming the underlying substrate.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 29, 2013
    Assignee: Novellus Systems, Inc.
    Inventor: Wesley P. Graff
  • Patent number: 8563438
    Abstract: A manufacturing method of a semiconductor device of which cost can be suppressed by using a nanoimprinting method is provided. In the invention, a gate insulating film, a conductive film, and a resist are formed in sequence over a semiconductor film and a resist is hardened while pressing a mold formed with a pattern to the resist. Therefore, the pattern is transferred to the resist, the surface of the resist to which the pattern is transferred is ashed until a part of the conductive film is exposed, the resist having the ashed surface is used a mask, and the conductive film is etched.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shinji Maekawa
  • Patent number: 8557710
    Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of metal-containing material is described. In particular, the GCIB etch processing includes forming a GCIB that contains a halogen element.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: October 15, 2013
    Assignee: TEL Epion Inc.
    Inventors: Yan Shao, Martin D. Tabat, Christopher K. Olsen, Ruairidh Maccrimmon
  • Patent number: 8536062
    Abstract: Methods are provided for removing an oxide layer from a metal pad on an integrated circuit in order to reduce contact resistance. In one embodiment, aluminum oxide, on the surface of a bond pad substantially comprised of aluminum, is reacted with a first chemical agent to form an inorganic salt, and the inorganic salt is then reacted with a second chemical agent leaving a substantially bare, that is, unoxidized, aluminum surface.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: September 17, 2013
    Assignee: Advanced Inquiry Systems, Inc.
    Inventor: Jens Ruffler
  • Patent number: 8524607
    Abstract: An anisotropically conductive member has an insulating base material, and conductive paths composed of a conductive material which pass in a mutually insulated state through the insulating base material in a thickness direction thereof and which are provided in such a way that a first end of each conductive path is exposed on a first side of the insulating base material and a second end of each conductive path is exposed on a second side of the insulating base material. The conductive paths have a density of at least 2 million paths/mm2 and the insulating base material is a structure composed of an anodized aluminum film having micropores therein.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: September 3, 2013
    Assignee: FUJIFILM Corporation
    Inventors: Yoshinori Hotta, Takashi Touma, Yusuke Hatanaka
  • Patent number: 8501023
    Abstract: An apparatus for use with a digital micromirror device includes a hinge layer that is disposed outwardly from a substrate. The hinge layer including a hinge that is capable of at least partially supporting a micromirror that is disposed outwardly from the hinge. In one particular embodiment, the hinge and the substrate are separated by a first air gap. The device also including a first hinge support that is disposed outwardly from the substrate and inwardly from at least a portion of the hinge layer. The first hinge support being capable of transmitting a voltage to the hinge. At least a portion of the hinge support coupled to at least the portion of the hinge layer. In one particular embodiment, the first hinge support is formed in a process step that is different than a process step that forms the hinge layer.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: August 6, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Brett A. Mangrum
  • Patent number: 8501628
    Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 6, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Vinh Hoang Luong, Hiroyuki Takahashi, Akiteru Ko, Asao Yamashita, Vaidya Bharadwaj, Takashi Enomoto, Daniel J. Prager
  • Patent number: 8501608
    Abstract: The present invention relates to a method for processing semiconductor devices with a fine structure, and more particularly, to a processing method suitable for miniaturizing semiconductor devices with a so-called high-k/metal gate structure. In an embodiment of the present invention, a deposited film, which includes an insulating film made of Hf or Zr and a material of Mg, Y or Al existing on, under or in the insulating film, is formed on a Si substrate and is removed by repeating a dry etching process and a wet etching process at least one time. The wet etching process is performed prior to the dry etching process.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: August 6, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tetsuo Ono, Tetsu Morooka
  • Patent number: 8501620
    Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: August 6, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun
  • Patent number: 8491799
    Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ki Jung
  • Patent number: 8481434
    Abstract: To remove the deposit including a high dielectric constant film deposited on an inside of a processing chamber, by using a cleaning gas activated only by heat. The method includes the steps of: loading a substrate or a plurality of substrates into the processing chamber; performing processing to deposit the high dielectric constant film on the substrate by supplying processing gas into the processing chamber; unloading the processed substrate from the inside of the processing chamber; and cleaning the inside of the processing chamber by supplying a halide gas and an oxygen based gas into the processing chamber, and removing the deposit including the high dielectric constant film deposited on the inside of the processing chamber, and in the step of cleaning the inside of the processing chamber, the concentration of the oxygen based gas in the halide gas and the oxygen based gas is set to be less than 7%.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: July 9, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Hironobu Miya, Eisuke Nishitani, Yuji Takebayashi, Masanori Sakai, Hirohisa Yamazaki, Toshinori Shibata, Minoru Inoue
  • Patent number: 8480911
    Abstract: A read sensor for a read transducer is fabricated. The read transducer has field and device regions. A read sensor stack is deposited. A mask covering part of the stack corresponding to the read sensor is provided. The read sensor having inboard and outboard junction angles is defined from the stack in a track width direction. A critical junction (CJ) focused ion beam scan (FIBS) polishing that removes part of the read sensor based on the junction angles is performed. A hard bias structure is deposited and the transducer planarized. A remaining portion of the mask is removed. A stripe height mask covering part of the read sensor and hard bias structure in a stripe height direction is provided. The read sensor stripe height is defined. A tunneling magnetoresistance (TMR) FIBS polishing that removes part of the stack in the field region is performed. An insulating layer is provided.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 9, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Masahiro Osugi, Guanghong Luo, Lily Yao, Ming Jiang
  • Patent number: 8475872
    Abstract: Simplified patterning of layers of a thin film is disclosed. In some embodiments, the patterning can include patterning a first conductive layer using a patterned dielectric layer as a mask and patterning a second conductive layer using a patterned passivation layer as another mask. In other embodiments, the patterning can include patterning a first conductive layer using a removable photosensitive layer as a mask, patterning a black mask layer using a removable photo mask, and patterning a second conductive layer using a patterned passivation layer as another mask. In still other embodiments, the patterning can include patterning a first conductive layer using a patterned black mask layer as a mask and patterning a second conductive layer using a patterned passivation layer as another mask. An exemplary device utilizing the thin film so patterned can include a touch sensor panel.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: July 2, 2013
    Assignee: Apple Inc.
    Inventors: Sunggu Kang, Lili Huang, Steven Porter Hotelling, John Z. Zhong
  • Patent number: 8461038
    Abstract: An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: June 11, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: James Walter Blatchford
  • Patent number: 8440513
    Abstract: In a semiconductor that has a structure in which a work function controlling metal conductor is provided on a high dielectric insulation film, fine processing is performed without deteriorating a device. In a method of semiconductor processing, in which the semiconductor has an insulation film containing Hf or Zr formed on a semiconductor substrate and a conductor film containing Ti or Ta or Ru formed on an insulation film, and the conductor film is processed by using a resist formed on the conductor film under a plasma atmosphere, the resist is removed under the plasma atmosphere of gas that contains hydrogen and does not contain oxygen.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: May 14, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tetsuo Ono, Go Saito
  • Patent number: 8440574
    Abstract: A method for ashing hardened resist from a photoresist patterned chromium alloy post etch using a plasma ashing chemistry which contains no gaseous source of hydrogen and contains a gaseous source of oxygen and a gaseous source of nitrogen with an oxygen to nitrogen atomic ratio of at least 5.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: May 14, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Abbas Ali
  • Patent number: 8435895
    Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: May 7, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
  • Patent number: 8426316
    Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: John Michael Cotte, Nils Deneke Hoivik, Christopher Vincent Jahnes, Robert Luke Wisnieff
  • Patent number: 8415249
    Abstract: A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: April 9, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 8404590
    Abstract: There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: March 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Sung Tae Lee, Kazuya Dobashi
  • Patent number: 8404558
    Abstract: In a preferred method of formation embodiment, a metal foil or film is obtained or formed with micro-holes. The foil is anodized to form metal oxide. One or more self-patterned metal electrodes are automatically formed and buried in the metal oxide created by the anodization process. The electrodes form in a closed circumference around each microcavity in a plane(s) transverse to the microcavity axis, and can be electrically isolated or connected. Preferred embodiments provide inexpensive microplasma device electrode structures and a fabrication method for realizing microplasma arrays that are lightweight and scalable to large areas. Electrodes buried in metal oxide and complex patterns of electrodes can also be formed without reference to microplasma devices—that is, for general electrical circuitry.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: March 26, 2013
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: J. Gary Eden, Sung-Jin Park, Kwang-Soo Kim
  • Patent number: 8404597
    Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being different from the second etchant.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: March 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Lothar Brencher, Dirk Meinhold, Michael Hartenberger, Georg Seidemann, Wolfgang Dickenscheld
  • Publication number: 20130043516
    Abstract: A method for manufacturing a semiconductor device includes forming a contact etch stop layer on an active area of a substrate that has a gate stack formed thereon. The gate stack includes a metal gate and a metal oxide. The contact etch stop layer includes a silicon oxide layer sandwiched between a first and a silicon nitride layers, the second silicon nitride layer is disposed on the active area. The method further includes forming a contact hole extending through an interlayer dielectric layer on the first silicon nitride layer using the first silicon nitride layer as a protection for the active area, removing a portion the first silicon nitride layer disposed at the bottom of the contact hole using the silicon oxide layer as a protection for the active area, and removing the metal oxide using the second silicon nitride layer as a protection for the active area.
    Type: Application
    Filed: December 14, 2011
    Publication date: February 21, 2013
    Applicant: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Qiuhua Han, Xinpeng Wang, Yi Huang
  • Patent number: 8377318
    Abstract: A method for manufacturing a magnetic device that obtains sufficient processing accuracy without increasing mask removal steps. A first mask layer is formed above a magnetic layer using one selected from the group consisting of Ti, Ta, W, and an oxide or a nitride thereof. A second mask layer is formed on the first mask layer using Ru or Cr. A resist pattern is formed on the second mask layer. A second mask pattern is formed by performing reactive ion etching with reactive gas containing oxygen on the second mask layer using the resist pattern. A first mask pattern is formed by performing reactive ion etching with reactive gas containing halogen gas on the first mask layer using the second mask pattern. A magnetic pattern is formed by performing reactive ion etching with reactive gas containing oxygen on the magnetic layer using the first mask pattern.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: February 19, 2013
    Assignee: ULVAC, Inc.
    Inventor: Tadashi Yamamoto
  • Patent number: 8372743
    Abstract: An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: James Walter Blatchford
  • Patent number: 8338311
    Abstract: A method for the production of a structured metal layer (7) made from an alloy composed of titanium and nickel includes the following process steps: a sacrificial layer composite (3) is provided, which comprises a second sacrificial layer (2) applied onto a first sacrificial layer (1), the first sacrificial layer (1) is subjected for the purpose of structuring to a wet-chemical etching process in such a manner that undercutting of the sacrificial layer (1) occurs, a metal layer (7) of the alloy is applied indirectly or directly to the structured sacrificial layer composite (3). The first sacrificial layer (1) is at a greater distance from the metal layer (7). The second sacrificial layer (2) facing the metal layer (7) to be deposited is subjected to a dry etching process prior to wet-chemical etching of the first sacrificial layer (1) so that the second sacrificial layer (2) is provided with a structure that corresponds to the desired structure of the metal layer (7).
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: December 25, 2012
    Assignee: Acandis GmbH & Co. KG
    Inventors: Eckhard Quandt, Clemens Schmutz, Christiane Zamponi
  • Patent number: 8338914
    Abstract: The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: December 25, 2012
    Assignee: Intersil Americas Inc.
    Inventors: John T. Gasner, John Stanton, Dustin A. Woodbury, James D. Beasom
  • Patent number: 8334215
    Abstract: A substrate can be appropriately oxidized, while oxidation of the substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen(O2) or oxygen/containing gas supplied to a processing chamber to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the processing chamber to form a plasma discharge, and processing the substrate by the hydrogen plasma.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: December 18, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Tatsushi Ueda, Tadashi Terasaki, Unryu Ogawa, Akito Hirano
  • Patent number: 8298955
    Abstract: This invention relates to a method for conducting an etching process which uses a plasma of a process gas. This etching process is conducted on a wafer W including a substrate 101, an underlying film 102, 103 formed on the substrate, and a film 104 to be etched that is formed on the underlying film. A main etching gas formed up of a chlorine-containing gas and an oxygen-containing gas, and a nitrogen-containing gas are used as the process gas. In this etching method, etching is conducted under a condition that an N2+/N2 intensity ratio of N2+ to N2, derived from emission spectra of the plasma, is at least 0.6.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: October 30, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Tetsuya Nishizuka
  • Patent number: 8273614
    Abstract: To reduce variation among TFTs in manufacture of a semiconductor device including n-type thin film transistors and p-type thin film transistors. Further, another object of the present invention is to reduce the number of masks and manufacturing steps, and manufacturing time. A method of manufacturing a semiconductor device includes forming an island-shaped semiconductor layer of a first thin film transistor, then, forming an island-shaped semiconductor layer of the second thin film transistor. In the formation of the island-shaped semiconductor layer of the second thin film transistor, a gate insulating film in contact with the island-shaped semiconductor layer of the second thin film transistor is used as a protection film (an etching stopper film) for the island-shaped semiconductor layer of the first thin film transistor.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: September 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kunio Hosoya, Saishi Fujikawa
  • Publication number: 20120238103
    Abstract: A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions, and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the metal-containing layer at a higher etch rate than the reactive gas etches the silicon oxide layer.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 20, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin Ingle
  • Publication number: 20120231561
    Abstract: Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, and exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 13, 2012
    Inventors: Brian Dolan, Robert J. Hanson, Chan Lim
  • Patent number: 8258063
    Abstract: A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO2 on a silicon substrate; depositing a high K dielectric film on the interfacial layer; performing a rapid thermal anneal of the high K dielectric film; depositing a TaN metal gate electrode film on the high K dielectric film; depositing a polysilicon gate layer on the TaN metal gate electrode film, and then depositing a hard mask layer; patterning a photoresist mask, and performing an anisotropic etching of the hard mask layer; removing the photoresist mask, and etching the polysilicon by reactive ion etching with the hard mask as masking layer using a mixed gas of Cl2/HBr; and etching the TaN metal gate electrode/high K dielectric gate stack by reactive ion etching with the hard mask as masking layer using BCl3-based etchant gas.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: September 4, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Yongliang Li
  • Patent number: 8236701
    Abstract: A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on a surface thereof a film composed of a metal of the same kind as the metal substance, is processed and particles of the metal are deposited on an inner wall of said processing chamber.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: August 7, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masahiro Sumiya, Motohiro Tanaka, Kousa Hirota
  • Patent number: 8232214
    Abstract: A liquid crystal display device includes a plurality of gate lines and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistors, each disposed in one of the pixel regions, and a plurality of pixel electrodes, each disposed in one of the pixel regions, wherein the thin film transistor includes at least one Ti layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 31, 2012
    Assignee: LG Display Co., Ltd
    Inventors: Gee-Sung Chae, Yong-Sup Hwang
  • Publication number: 20120168704
    Abstract: A method of etching a programmable memory microelectronic device (10) having a substrate covered with at least one of the following layers in succession: a first electrode (2) based on a first metallic element; a layer (4) of chalcogenide doped with a second metallic element; a second electrode (5) based on a third metallic element; a diffusion barrier type electrically-conductive layer (6); and a hard mask (7); is provided. The method includes etching, using an inert gas plasma, at least the hard mask (7), the electrically-conductive layer (6), the second electrode (5) and the chalcogenide layer (4), where the etching step is carried out by cathode sputtering at a temperature strictly less than 150° C., preferably at a temperature of at most 120° C., and particularly preferably at a temperature of at most 100° C.
    Type: Application
    Filed: December 16, 2011
    Publication date: July 5, 2012
    Inventor: Stéphane Cholet
  • Publication number: 20120164839
    Abstract: There is provided a substrate processing method capable of increasing an etching rate of a copper member without using a halogen gas. A Cu layer 40 having a smoothened surface 50 is obtained, and then, a processing gas produced by adding a methane gas to a hydrogen gas is introduced into an inner space of a processing chamber 15. Plasma is generated from this processing gas. In the inner space of the processing chamber 15, there exist oxygen radicals 52 generated when an oxide layer 42 is etched, and carbon radicals 53 generated from methane. The oxygen radicals 52 and the carbon radicals 53 are compounded to generate an organic acid, and the organic acid makes a reaction with copper atoms of the Cu layer 40. As a result, a complex of the organic acid having the copper atoms is generated, and the generated organic acid complex is vaporized.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Eiichi Nishimura
  • Patent number: 8198197
    Abstract: The present invention is a plasma etching method for etching a surface of a substrate in which a metal nitride film and a silicon film have been respectively formed on a first base film and a second base film that had been side-by-side arranged, with surfaces of the metal nitride film and the silicon film being exposed. At least a surface area of the silicon film is nitrided. A first etching plasma is supplied onto the surface of the substrate so as to etch the metal nitride film and to expose the first base film. A second etching plasma is supplied onto the surface of the substrate so as to etch the silicon film and to expose the second base film.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: June 12, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Yosuke Sakao, Hiroyuki Takahashi
  • Patent number: 8198196
    Abstract: A field effect transistor (FET) includes a trench extending into a semiconductor region. A conductive electrode is disposed in the trench, and the conductive electrode is insulated from the semiconductor region by a dielectric layer. The conductive electrode includes a conductive liner lining the dielectric layer along opposite sidewalls of the trench. The conductive liner has tapered edges such that a thickness of the conductive liner gradually increases from a top surface of the conductive electrode to a point in lower half of the conductive electrode. The conductive electrode further includes a conductive fill material sandwiched by the conductive liner. The FET further includes a drift region of a first conductivity type in the semiconductor region, and a body region of a second conductivity type extending over the drift region. Source regions of the first conductivity type extend in the body region adjacent the trench.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: June 12, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James J. Murphy, Hui Chen, Eileen Valdez
  • Patent number: 8193095
    Abstract: A method for forming a silicon trench, comprises the steps of: defining an etching area at a silicon substrate; forming metal catalysts at the surface of the etching area; immersing the silicon substrate in a first etching solution thereby forming anisotropic silicon nanostructures in the etching area; immersing the silicon substrate in a second etching solution thereby resulting in the silicon nanostructures being side-etched and detached from the silicon substrate, thus forming the silicon trench.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: June 5, 2012
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Shih-Che Hung, Shu-Jia Syu