Electrically Conductive Material (e.g., Metal, Conductive Oxide, Etc.) Patents (Class 438/720)
  • Patent number: 8173523
    Abstract: To provide a method of removing a heavy metal contained in a thinned semiconductor substrate. A method of removing a heavy metal in a semiconductor substrate of the present invention comprises: attaching, to a rear surface of the semiconductor substrate, a material that lowers a potential barrier of the rear surface of the semiconductor substrate, on a front surface of which a circuit is to be formed or is formed; applying a thermal treatment to the semiconductor substrate under a condition based on a thickness and a resistivity of the semiconductor substrate; and, depositing the heavy metal in the semiconductor substrate on the rear surface.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: May 8, 2012
    Assignee: Sumco Corporation
    Inventors: Noritomo Mitsugi, Masataka Hourai, Shuichi Samata, Kiyoshi Nagai, Kei Matsumoto
  • Patent number: 8143163
    Abstract: A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: March 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Seung Choi
  • Patent number: 8138095
    Abstract: Substrate processing apparatus 100 includes supporting table 103 for not only supporting a target substrate W but also heating the target substrate W; processing chamber 101 having the supporting table disposed therein; and gas supply unit 102 for supplying a processing gas into the processing chamber 101. The processing gas includes organic acid metal complex or organic acid metal salt.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: March 20, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Hidenori Miyoshi
  • Patent number: 8133325
    Abstract: This dry cleaning method for a plasma processing apparatus is a dry cleaning method for a plasma processing apparatus that includes: a vacuum container provided with a dielectric member; a planar electrode and a high-frequency antenna that are provided outside the dielectric member; and a high-frequency power source that supplies high-frequency power to both the high-frequency antenna and the planar electrode, to thereby introduce high-frequency power into the vacuum container via the dielectric member and produce an inductively-coupled plasma, the method comprising the steps of: introducing a gas including fluorine into the vacuum container and also introducing high-frequency power into the vacuum container from the high-frequency power source, to thereby produce an inductively-coupled plasma in the gas including fluorine; and by use of the inductively-coupled plasma, removing a product including at least one of a precious metal and a ferroelectric that is adhered to the dielectric member.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 13, 2012
    Assignee: ULVAC, Inc.
    Inventors: Masahisa Ueda, Yutaka Kokaze, Mitsuhiro Endou, Koukou Suu
  • Patent number: 8129270
    Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: March 6, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun
  • Patent number: 8124541
    Abstract: An etchant gas and a method for removing at least a portion of a late transition metal structure. The etchant gas includes PF3 and at least one oxidizing agent, such as at least one of oxygen, ozone, nitrous oxide, nitric oxide and hydrogen peroxide. The etchant gas provides a method of uniformly removing the late transition metal structure or a portion thereof. Moreover, the etchant gas facilitates removing a late transition metal structure with an increased etch rate and at a decreased etch temperature. A method of removing a late transition metal without removing more reactive materials proximate the late transition metal and exposed to the etchant gas is also disclosed.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8114782
    Abstract: A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the amorphous carbon organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the amorphous carbon organic hardmask with the plasma, with the amorphous carbon organic hardmask being at a temperature in excess of 200° C., to remove the amorphous carbon organic hardmask without substantially harming the underlying substrate.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: February 14, 2012
    Assignee: Novellus Systems, Inc.
    Inventor: Wesley P. Graff
  • Patent number: 8105951
    Abstract: A method for fabricating a device pattern includes the following steps. A first pattern having a first density is formed in a pre-determined region on a substrate. The first pattern includes a base portion along a first direction and at least two protruding portions along a second direction and connected to the base portion. A spacer is formed on a sidewall of each protruding portion. The spacers do not connect with the base portion, and the spacers between two adjacent protruding portions do not connect with each other, so as to form a gap between the two adjacent protruding portions. Then, a second pattern is formed on the substrate and located in the gap, such that a third pattern having a second density is formed in the pre-determined region by the first pattern and the second pattern.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: January 31, 2012
    Assignee: Nanya Technology Corporation
    Inventor: Yu-Yao Chang
  • Patent number: 8101526
    Abstract: A method for fabricating diamond nanopillars includes forming a diamond film on a substrate, depositing a metal mask layer on the diamond film, and etching the diamond film coated with the metal mask layer to form diamond nanopillars below the mask layer. The method may also comprise forming diamond nuclei on the substrate prior to forming the diamond film. Typically, a semiconductor substrate, an insulating substrate, a metal substrate, or an alloy substrate is used.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: January 24, 2012
    Assignee: City University of Hong Kong
    Inventors: Shuit-Tong Lee, Wenjun Zhang, Igor Bello, You-Sheng Zou
  • Publication number: 20110306215
    Abstract: Methods of processing substrates having metal layers are provided herein. In some embodiments, a method of processing a substrate comprising a metal layer having a patterned mask layer disposed above the metal layer, the method may include etching the metal layer through the patterned mask layer; and removing the patterned mask layer using a first plasma formed from a first process gas comprising oxygen (O2) and a carbohydrate. In some embodiments, a two step method with an additional second process gas comprising chlorine (Cl2) or a sulfur (S) containing gas, may provide an efficient way to remove patterned mask residue.
    Type: Application
    Filed: January 27, 2011
    Publication date: December 15, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: GUOWEN DING, HERRICK NG, TEH-TIEN SU, BENJAMIN SCHWARZ, ZHUANG LI
  • Publication number: 20110281438
    Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.
    Type: Application
    Filed: November 18, 2008
    Publication date: November 17, 2011
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Wonchul Lee, Qian Fu, Shenjian Liu, Bryan Pu
  • Publication number: 20110275220
    Abstract: The present invention is directed to a method and apparatus for etching various metals that may be used in semiconductor or integrated circuit processing through the use of non-halogen gases such as hydrogen, helium, or combinations of hydrogen and helium with other gases such as argon. In one exemplary embodiment of the present invention, in a reaction chamber, a substrate having a metal interconnect layer deposited thereon is exposed to a plasma formed of non-halogen gas. The plasma generated is maintained for a certain period of time to provide for a desired or expected etching of the metal. In some embodiments, the metal interconnect layer may be copper, gold or silver.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 10, 2011
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: FANGYU WU, DENNIS W. HESS, GALIT LEVITIN
  • Patent number: 8049345
    Abstract: An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: November 1, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chin-Cheng Yang, Chih-Hao Huang
  • Patent number: 8043515
    Abstract: A thin film magnetic head has a configuration in which a main magnetic pole film having a magnetic pole end portion on a medium opposing surface (ABS) side facing a magnetic disk, a write shield film facing the magnetic pole end portion so as to form a recording gap film on the medium opposing surface side, and a thin film coil wound around at least a part of the write shield film are laminated. Further, the thin film magnetic head has an upper yoke magnetic pole film whose size is larger than that of the main magnetic pole film at a part more distant from the ABS than the recording gap film, and this upper yoke magnetic pole film is bonded to the side of the main magnetic pole film close to the thin film coil. In the upper yoke magnetic pole film, an end portion on the ABS side is retracted in a direction apart from the ABS in accordance with an increase in film thickness which is measured from the surface of the main magnetic pole film.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: October 25, 2011
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Itoh, Takehiro Kamigama, Tatsushi Shimizu
  • Patent number: 8030207
    Abstract: A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuo Kawamura, Hisaya Sakai, Hirofumi Watatani, Kazuya Okubo
  • Publication number: 20110237084
    Abstract: A method for etching a differential metal gate structure on a substrate is described. The differential metal gate structure includes a metal gate layer overlying a high dielectric constant (high-k) dielectric layer, wherein the metal gate layer comprises a different thickness at different regions on the substrate. The metal gate layer is patterned by using a plasma etching process, wherein at least one etch step includes forming plasma using a halogen-containing gas and at least one etch step includes forming plasma using an additive gas having as atomic constituents C, H, and F.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Vinh Hoang LUONG, Hiroyuki TAKAHASHI, Akiteru KO, Asao YAMASHITA, Vaidyanathan BALASUBRAMANIAM, Takashi ENOMOTO, Daniel J. PRAGER
  • Patent number: 8026118
    Abstract: The present invention provides a gallium nitride based compound semiconductor light-emitting device having high light emission efficiency and a method of manufacturing the same. The gallium nitride based compound semiconductor light-emitting device includes: a substrate 11; an n-type semiconductor layer 13, a light-emitting layer 14, and a p-type semiconductor layer 15 that are composed of gallium nitride based compound semiconductors and formed on the substrate 11 in this order; a transparent positive electrode 16 that is formed on the p-type semiconductor layer 15; a positive electrode bonding pad 17 that is formed on the transparent positive electrode 16; a negative electrode bonding pad 18 that is formed on the n-type semiconductor layer 13; and an uneven surface that has random convex portions formed thereon and is provided on at least a portion of the surface 16a of the transparent positive electrode 16.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: September 27, 2011
    Assignee: Showa Denko K.K.
    Inventors: Hironao Shinohara, Hiroshi Osawa
  • Patent number: 7981734
    Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: July 19, 2011
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Patent number: 7977244
    Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 12, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Patent number: 7936569
    Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
  • Patent number: 7927960
    Abstract: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape. The trenches are overfilled with a first metal layer, the excess of which is removed so that the height of the metal is level with the height of the oxide. An overlay setting is then obtained between a photoresist mask and the filled trenches before depositing a second metal layer over the oxide and trenches. The second metal layer is coated with the photoresist according to the overlay setting.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: April 19, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chin Cheng Yang, Chih Hao Huang
  • Patent number: 7923374
    Abstract: In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are controlled as predetermined, to deposit the Cu component of the precursor on the substrate, thereby forming a film of Cu. In this apparatus, Cl* is formed in an excitation chamber of a passage communicating with the interior of the chamber to flow a Cl2 gas, and the Cl* is supplied into the chamber to withdraw a Cl2 gas from the precursor adsorbed onto the substrate, thereby promoting a Cu film formation reaction. The apparatus has a high film formation speed, can use an inexpensive starting material, and can minimize impurities remaining in the film.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: April 12, 2011
    Assignee: Canon Anelva Corporation
    Inventors: Hitoshi Sakamoto, Naoki Yahata, Toshihiko Nishimori, Yoshiyuki Ooba, Hiroshi Tonegawa, Ikumasa Koshiro, Yuzuru Ogura
  • Patent number: 7915162
    Abstract: A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric layer. A first and second trench is formed within the first dielectric layer and the first hard mask. The second trench is wider than the first trench. A first conformal liner is deposited over the first hard mask and within the first and second trenches, a portion of which is removed, leaving a remaining portion of the first conformal liner in direct physical contact with the substrate, the first dielectric layer, and the first hard mask, and not on the first hard mask. Copper is deposited over the first conformal liner to overfill fill the first and second trenches and is planarized to remove an excess thereof to form a planar surface of the copper.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Jeffrey P. Gambino, Anthony K. Stamper
  • Patent number: 7915174
    Abstract: Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7901586
    Abstract: A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-kyeong Yoo, Soo-hwan Jeong, Sun-ae Seo, In-sook Kim
  • Patent number: 7897516
    Abstract: Methods for resputtering and plasma etching include an operation of generating an ultra-high density plasma using an ultra-high magnetic field. For example, a plasma density of at least about 1013 electrons/cm3 is achieved by confining a plasma using a magnetic field of at least about 1 Tesla. The ultra-high density plasma is used to create a high flux of low energy ions at the wafer surface. The formed high density low energy plasma can be used to sputter etch a diffusion barrier or a seed layer material in the presence of an exposed low-k dielectric layer. For example, a diffusion barrier material can be etched with a high etch rate to deposition rate (E/D) ratio (e.g., with E/D>2) without substantially damaging an exposed dielectric layer. Resputtering and plasma etching can be performed, for example, in iPVD and in plasma pre-clean tools, equipped with magnets configured for confining a plasma.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: March 1, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Ronald L. Kinder, Anshu A. Pradhan
  • Patent number: 7880204
    Abstract: A Silicon photodetector contains an insulating substrate having a top surface and a bottom surface. A Silicon layer is located on the top surface of the insulating substrate, where the Silicon layer contains a center region, the center region being larger in thickness than the rest of the Silicon layer. A top Silicon dioxide layer is located on a top surface of the center region. A left wing of the center region and a right wing of the center region are doped. The Silicon photodetector also has an active region located within the center region, where the active region contains a tailored crystal defect-impurity combination and Oxygen atoms.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: February 1, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael W. Geis, Steven J. Spector, Donna M. Lennon, Matthew E. Grein, Robert T. Schulein, Jung U. Yoon, Franz Xaver Kaertner, Fuwan Gan, Theodore M. Lyszczarz
  • Patent number: 7863151
    Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 4, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Manabu Takei
  • Publication number: 20100323523
    Abstract: A platinum-comprising material is plasma etched by being exposed to a plasma etching chemistry that includes CHCl3, CO2 and O2. In one embodiment, a method of processing a semiconductor substrate in the fabrication of integrated circuitry includes forming metallic platinum-comprising nanoparticles over a material. A portion of the nanoparticles is masked and another portion of the nanoparticles is unmasked. The unmasked portion of the metallic platinum-comprising nanoparticles is plasma etched using a plasma etching chemistry comprising CHCl3, CO2 and O2. Other embodiments are disclosed.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 23, 2010
    Inventors: Hongbin Zhu, Mark Kiehlbauch, Alex Schrinsky
  • Patent number: 7836587
    Abstract: An electrical element can be attached and electrically connected to a substrate by a conductive adhesive material. The conductive adhesive material can electrically connect the electrical element to a terminal or other electrical conductor on the substrate. The conductive adhesive material can be cured by directing a flow of heated gas onto the material or by heating the material through a support structure on which the substrate is located. A non-conductive adhesive material can attach the electrical element to the substrate with a greater adhesive strength than the conductive adhesive. The non-conductive adhesive material can also be cured by directing a flow of heated gas onto the material or by heating the material through the support structure on which the substrate is located. The non-conductive adhesive material can cover the conductive adhesive material.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: November 23, 2010
    Assignee: FormFactor, Inc.
    Inventor: Tae Ma Kim
  • Patent number: 7838433
    Abstract: A method and apparatus for process integration in manufacture of a photomask are disclosed. In one embodiment, a cluster tool suitable for process integration in manufacture of a photomask including a vacuum transfer chamber having coupled thereto at least one hard mask deposition chamber and at least one plasma chamber configured for etching chromium. In another embodiment, a method for process integration in manufacture of a photomask includes depositing a hard mask on a substrate in a first processing chamber, depositing a resist layer on the substrate, patterning the resist layer, etching the hard mask through apertures formed in the patterned resist layer in a second chamber; and etching a chromium layer through apertures formed in the hard mask in a third chamber.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Ajay Kumar
  • Patent number: 7829457
    Abstract: In some embodiments, after depositing conductive material on substrates in a deposition chamber, a reducing gas is introduced into as the chamber in preparation for unloading the substrates. The deposition chamber can be a batch CVD chamber and the deposited material can be a metal nitride, e.g., a transition metal nitride such as titanium metal nitride. As part of the preparation for unloading substrates from the chamber, the substrates may be cooled and the chamber is backfilled with a reducing gas to increase the chamber pressure. It has been found that oxidants can be introduced into the chamber during this time. The introduction of a reducing gas has been found to protect exposed metal-containing films from oxidation during the backfill and/or cooling process. The reducing gas is formed of a reducing agent and a carrier gas, with the reducing agent being a minority component of the reducing gas.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: November 9, 2010
    Assignee: ASM International N.V.
    Inventors: Tatsuya Yoshimi, Rene de Blank, Jerome Noiray
  • Patent number: 7799698
    Abstract: A deposition/etching/deposition process is provided for filling a gap in a surface of a substrate. A liner is formed over the substrate so that distinctive reaction products are formed when it is exposed to a chemical etchant. The detection of such reaction products thus indicates that the portion of the film deposited during the first etching has been removed to an extent that further exposure to the etchant may remove the liner and expose underlying structures. Accordingly, the etching is stopped upon detection of distinctive reaction products and the next deposition in the deposition/etching/deposition process is begun.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 21, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Lin Zhang, Xiaolin Chen, DongQing Li, Thanh N. Pham, Farhad K. Moghadam, Zhuang Li, Padmanabhan Krishnaraj
  • Patent number: 7799691
    Abstract: A method and apparatus for anisotropically etching a recess in a silicon substrate is disclosed. Generally, a plasma is used for energetic excitation of a reactive etching gas, wherein the reactive etching gas is a constituent of a continuous gas flow. A recess is anisotropically etched in a silicon substrate using the reactive etching gas, during which time the recess id deepened by at least fifty micrometers without interrupting the gas flow of the reactive etching gas.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: September 21, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Hanewald, Andreas Hauser, Ingold Janssen, Kai-Olaf Subke
  • Patent number: 7781348
    Abstract: A method of forming an organic light-emitting display (OLED) includes the steps of providing a substrate, forming a black matrix on the substrate, forming a buffer layer on the black matrix, forming an active layer on the buffer layer, simultaneously patterning the black matrix and the buffer layer, and forming a display electrode and a thin film transistor over the buffer layer.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: August 24, 2010
    Assignee: AU Optronics Corp.
    Inventors: Hsin-hung Lee, Ming-chang Shih
  • Patent number: 7776753
    Abstract: A method of fabricating a semiconductor device includes the steps of forming (or providing) a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used during etching operations when forming contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: August 17, 2010
    Assignees: University of Connecticut, Opel, Inc.
    Inventors: Geoff W. Taylor, Scott W. Duncan
  • Patent number: 7767585
    Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: August 3, 2010
    Assignees: Sony Corporation, Mitsubishi Gas Chemical Company, Inc.
    Inventors: Koichiro Saga, Kenji Yamada, Tomoyuki Azuma, Yuji Murata
  • Patent number: 7758762
    Abstract: An electron-emitting device comprises a pair of electrodes and an electroconductive film arranged between the electrodes and including an electron-emitting region carrying a graphite film. The graphite film shows, in a Raman spectroscopic analysis using a laser light source with a wavelength of 514.5 nm and a spot diameter of 1 ?m, peaks of scattered light, of which 1) a peak (P2) located in the vicinity of 1,580 cm?1 is greater than a peak (P1) located in the vicinity of 1,335 cm?1 or 2) the half-width of a peak (P1) located in the vicinity of 1,335 cm?1 is not greater than 150 cm?1.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: July 20, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Fumio Kishi, Masato Yamanobe, Takeo Tsukamoto, Toshikazu Ohnishi, Keisuke Yamamoto, Sotomitsu Ikeda, Yasuhiro Hamamoto, Kazuya Miyazaki
  • Patent number: 7754616
    Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer on a layer that is to be subjected to etching and contains at least one of silicon carbonate, silicon oxide, sapphire, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum nitride, the mask layer having an opening and including a nickel chrome film, a gold film, and a nickel film in this order when seen from the layer to be subjected to etching; and performing etching on the layer to be subjected to etching, with the mask layer serving as a mask.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: July 13, 2010
    Assignee: Eudyna Devices Inc.
    Inventors: Toshiyuki Kosaka, Masaomi Emori
  • Patent number: 7745342
    Abstract: A display substrate having a low-resistance metallic layer and a method of manufacturing the display substrate. The gate conductors are extended in a first direction. The source conductors are extended in a second direction crossing the first direction including a lower layer of molybdenum or a molybdenum alloy, and an upper layer of aluminum or an aluminum alloy. The pixel areas are defined by the gate conductors and the source conductors. A switching element is formed in each of the pixel areas and includes a gate electrode extended from the gate conductor and a source electrode extended from the source conductor. The pixel electrode includes a transparent conductive material, and is electrically connected to a drain electrode of the switching element.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Han Kim, Min-Seok Oh, Jun-Young Lee, Sung-Wook Kang
  • Patent number: 7745341
    Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Won Kim, Yong-Sun Ko, Ki-Jong Park, Kyung-Hyun Kim
  • Patent number: 7723235
    Abstract: After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21) (step S3). Then, a passivation film (23) is deposited on the antireflection film (21) so as to cover the resist pattern (22) by plasma using fluorocarbon gas while a bias voltage is being applied to the semiconductor substrate (step S4). Then, the passivation film (23) and the antireflection film (21) are etched by plasma using gas containing oxygen gas (step S5). Thereafter, the polycrystalline silicon film (5) is etched using the resist pattern (22) with reduced line edge roughness as an etching mask to form a gate electrode (step S6).
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Masaru Kurihara, Masaru Izawa
  • Patent number: 7709343
    Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: May 4, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Thomas A. Figura, Kevin G. Donohoe, Thomas Dunbar
  • Patent number: 7709393
    Abstract: A method for manufacturing a semiconductor device is provided. In particular, a method for removing unwanted material layers from an edge and lower bevel region of a wafer is provided. The method includes performing a first etch of an edge region of a wafer having material layers formed thereon, coating the wafer with a photoresist layer, and patterning the photoresist layer to expose at least the edge and an upper bevel region of the wafer for etching the material layers remaining after performing the first etch.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 4, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: In Su Kim
  • Patent number: 7704890
    Abstract: A method for fabricating a TFT is provided. First, a poly-silicon layer is formed over a substrate. A photoresist layer is formed on the poly-silicon layer, wherein the photoresist layer has a pattern for exposing parts of the poly-silicon layer, and the pattern has a varied thickness. The poly-silicon layer is patterned by using the photoresist layer as an etching mask to define a poly-silicon island. Thereafter, a part of the thickness of the photoresist layer is removed for exposing a part of the poly-silicon island. Then, a first ion implanting is performed on the exposed part of the poly-silicon island to form a source and a drain thereby. After removing the residue photoresist layer; a gate insulating layer, a gate, a patterned dielectric layer and a conductive layer are formed on the substrate sequentially.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: April 27, 2010
    Assignee: AU Optronics Corp.
    Inventor: Chi-Wen Yao
  • Patent number: 7696100
    Abstract: A manufacturing method of a semiconductor device of which cost can be suppressed by using a nanoimprinting method is provided. In the invention, a gate insulating film, a conductive film, and a resist are formed in sequence over a semiconductor film and a resist is hardened while pressing a mold formed with a pattern to the resist. Therefore, the pattern is transferred to the resist, the surface of the resist to which the pattern is transferred is ashed until a part of the conductive film is exposed, the resist having the ashed surface is used a mask, and the conductive film is etched.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: April 13, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shinji Maekawa
  • Patent number: 7678642
    Abstract: A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to fill the contact holes. Forming a hard mask layer on the conductive layer and etching the hard mask layer and the conductive layer to form contact plugs in the contact holes. Finally, forming a conductive layer pattern that is located on the contact plug and portions of the first interlayer dielectric adjacent to the contact plug and having a hard mask thereon.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: March 16, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Heon Yong Chang
  • Publication number: 20100062591
    Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on substrate; forming a patterned photoresist layer on the first material layer; applying an etching process to the first material layer using the patterned photoresist layer as a mask; and applying a nitrogen-containing plasma to the substrate to remove the patterned photoresist layer.
    Type: Application
    Filed: March 9, 2009
    Publication date: March 11, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu Chao Lin, Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin
  • Patent number: 7670941
    Abstract: A method for production of semiconductor devices which includes the steps of forming, on an interlayer insulating film formed on a substrate, a copper-containing conductive layer in such a way that its surface is exposed, performing heat treatment with a reducing gas composed mainly of hydrogen on the surface of the conductive layer, performing plasma treatment with a reducing gas on the surface of the conductive layer, thereby permitting the surface of the conductive layer to be reduced and the hydrogen adsorbed by the heat treatment to be released, and forming an oxidation resistance film that covers the surface of the conductive layer such that the surface of the conductive layer is not exposed to an oxygen-containing atmospheric gas after the plasma treatment.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 2, 2010
    Assignee: Sony Corporation
    Inventors: Koji Kawanami, Kiyotaka Tabuchi
  • Patent number: 7659210
    Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: February 9, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Ramakanth Alapati, Paul Morgan, Max Hineman