Making Electromagnetic Responsive Array Patents (Class 438/73)
  • Patent number: 8778721
    Abstract: An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Piero Giorgio Fallica
  • Patent number: 8779484
    Abstract: An image sensor includes a plurality of color filters and an anti-reflective layer. The color filters are located on a substrate. The anti-reflective layer is located between the substrate and the color filters, and parts of the anti-reflective layer corresponding to at least two of the color filters have different thicknesses. Moreover, an image sensing process including the following steps is also provided. An anti-reflective layer is formed on a substrate. A plurality of color filters is formed on the anti-reflective layer, wherein parts of the anti-reflective layer right below at least two of the color filters have different thicknesses.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 15, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Xu Yang Shen, Seng Wah Liau, Yuheng Liu, Qin Li, Kiet Houng Chow
  • Publication number: 20140191195
    Abstract: Pixels in a focal plane array are defined by controlled variation of the Fermi energy at the surface of the detector array. Varying the chemical composition of the semiconductor at the detector surface produces a corresponding variation in the surface Fermi energy which produces a corresponding variation in the electric field and electrostatic potential in the bulk semiconductor below the surface. This defines pixels by having one Fermi energy at the surface of each pixel and a different Fermi energy at the surface between pixels. Fermi energy modulation can also be controlled by applying an electrostatic potential voltage V1 to the metal pad defining each pixel, and applying a different electrostatic potential voltage V2 to an interconnected metal grid covering the gaps between all the pixel metal pads. Methods obviate the need to etch deep trenches between pixels, resulting in a more manufacturable quasi-planar process without sacrificing performance.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 10, 2014
    Inventors: Mani Sundaram, Axel Reisinger
  • Publication number: 20140190557
    Abstract: A method of producing a solar cell module including forming a silicon oxide layer by coating a paint containing at least one of silicate hydrolysis products and silica particles on at least one side of a base film; and adhering said silicon oxide layer with a silicone sealing material layer.
    Type: Application
    Filed: August 28, 2012
    Publication date: July 10, 2014
    Applicants: TORAY ADVANCED FILM CO., LTD., TORAY INDUSTRIES, INC.
    Inventors: Shunsuke Kameda, Takashi Arai, Takao Amioka, Yuuka Ashida
  • Patent number: 8772844
    Abstract: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the effective channel width by distributing, in the vicinity of the channel of the reset transistor and the boundary line between an active region and an element isolation region, ions which enhance the generation of carriers of an opposite polarity to the channel.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 8, 2014
    Assignee: Wi Lan, Inc.
    Inventors: Motonari Katsuno, Ryouhei Miyagawa, Masayuki Matsunaga
  • Publication number: 20140183366
    Abstract: Thermo-optical array devices and methods of processing thermo-optical array devices are disclosed. One method of processing thermo-optical array devices includes forming an (001) oriented titanium dioxide material on a bolometer material, and forming a vanadium dioxide material on the (001) oriented titanium dioxide material. One thermo-optical array device includes a bolometer material, a titanium dioxide material on the bolometer material, and a vanadium dioxide material on the titanium dioxide material, wherein the vanadium dioxide material has an optical transition temperature of less than 67 degrees Celsius.
    Type: Application
    Filed: December 29, 2012
    Publication date: July 3, 2014
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventor: Honeywell International Inc.
  • Publication number: 20140183675
    Abstract: Exemplary embodiments are directed to imagining detectors and methods of fabricating the imagining detectors for use in medical imagining systems. In exemplary embodiments, a detector for an imaging device include a continuous unpatterned photoelectric material that forms a portion of a photosensor and an electrode disposed with respect to the photoelectric material to form an anode or cathode of the photosensor. Data readout lines connected to the outputs of transistors of the detector can be susceptible electronic noise from capacitive coupling between the electrode of the photosensor. In exemplary embodiments of the present disclosure, a lateral offset and/or vertical offset between the electrode and the data readout lines can be formed to control the capacitive coupling between the electrode and the data readout line.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Applicant: General Electric Company
    Inventors: Aaron Judy Couture, Gautam Parthasarathy, Jie Jerry Liu
  • Patent number: 8765361
    Abstract: A reticle includes a repetition pattern and a peripheral pattern, one of which has a first side in a first direction and the other a second side in the first direction. The first side has a first length that is n times the second length of the second side, where n is an integer equal to or larger than 1. The first pattern has at least one of first misalignment measurement patterns provided at positions distant by a third length and ((the third length)+(n?1).times.(the second length)) from an upper end of the first pattern. The third length is equal to or smaller than the second length. The second pattern has a second misalignment measurement pattern provided at a position distant by the third length from an upper end of the second pattern.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Taro Moriya
  • Patent number: 8766389
    Abstract: A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: July 1, 2014
    Assignee: Sony Corporation
    Inventor: Naoyuki Sato
  • Patent number: 8766392
    Abstract: The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises a photodiode array and method of manufacturing a photodiode array that provides for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: July 1, 2014
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8765517
    Abstract: A method of fabricating an image sensor device includes forming an insulating layer on a substrate including a photodiode therein, and forming a wiring structure on the insulating layer. The wiring structure includes at least one wiring layer and at least one insulating interlayer. A cavity is formed extending into the wiring structure over the photodiode to expose a surface of the at least one insulating interlayer. The surface of the at least one insulating interlayer exposed by the cavity is modified to define a hydrophobic surface. Related systems and devices are also discussed.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-jin Ahn, Min-young Jung
  • Publication number: 20140179051
    Abstract: A method of forming an organic light-emitting display in which a pixel electrode is formed by extending from source and drain electrodes, a capacitor including a thin upper capacitor electrode formed below the pixel electrode and constituting a metal-insulator-metal (MIM) CAP structure, thereby simplifying manufacturing processes, increasing an aperture ratio, and improving a voltage design margin.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 26, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: June-Woo Lee
  • Patent number: 8759934
    Abstract: An image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident through a first side of the image sensor to collect an image charge. The stress adjusting layer is disposed over the first side of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: June 24, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hsin-Chih Tai, Howard E. Rhodes, Wei Zheng, Vincent Venezia, Yin Qian, Duli Mao
  • Patent number: 8759141
    Abstract: A backside illuminated image sensor is provided which includes a substrate having a front side and a backside, a sensor formed in the substrate at the front side, the sensor including at least a photodiode, and a depletion region formed in the substrate at the backside, a depth of the depletion region is less than 20% of a thickness of the substrate.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Han-Chi Liu, Ching-Chun Wang
  • Publication number: 20140167046
    Abstract: A method of fabricating a pixelated imager includes providing a substrate with bottom contact layer and sensing element blanket layers on the contact layer. The blanket layers are separated into an array of sensing elements by trenches isolating adjacent sensing elements. A sensing element electrode is formed adjacent each sensing element overlying a trench and defining a TFT. A layer of metal oxide semiconductor (MOS) material is formed on a dielectric layer overlying the electrodes and on an exposed upper surface of the blanket layers defining the sensing element adjacent each TFT. A layer of metal is deposited on each TFT and separated into source/drain electrodes on opposite sides of the sensing element electrode. The metal forming one of the S/D electrodes contacts the MOS material overlying the exposed surface of the semiconductor layer, whereby each sensing element in the array is electrically connected to the adjacent TFT by the MOS material.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Inventors: Chan- Long Shieh, Gang Yu
  • Publication number: 20140167124
    Abstract: A solid-state imaging apparatus includes a transfer gate electrode formed on a semiconductor substrate; a photoelectric conversion unit including an electric charge storage area that is formed from a surface side of the semiconductor substrate in a depth direction, a transfer auxiliary area formed of a second conductive type impurity area that is formed in such a manner as to partially overlap the transfer gate electrode, and a dark current suppression area that is a first dark current suppression area formed in an upper layer of the transfer auxiliary and formed so as to have positional alignment in such a manner that the end portion of the transfer auxiliary area on the transfer gate electrode side is at the same position as the end portion of the transfer auxiliary area; and a signal processing circuit configured to process an output signal output from the solid-state imaging apparatus.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: Sony Corporation
    Inventors: Mikiko Kobayashi, Sanghoon Ha
  • Publication number: 20140167200
    Abstract: According to embodiments of the present invention, a photodetector is provided. The photodetector includes a substrate having a first side and a second side opposite to the first side, the substrate being adapted to receive light incident on the photodetector on the first side of the substrate, a plurality of cells formed in the substrate, and at least one trench defined by a first sidewall and a second sidewall, wherein a spacing between the first sidewall and the second sidewall increases in a direction from the first side of the substrate towards the second side, wherein a respective trench of the at least one trench is arranged in between adjacent cells of the plurality of cells. According to further embodiments of the present invention, a method for forming a photodetector is also provided.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 19, 2014
    Applicant: Agency for Science, Technology and Research
    Inventors: Fei Sun, Ning Duan, Patrick Guo-Qiang Lo
  • Publication number: 20140170801
    Abstract: A method of processing a semiconductor assembly is presented. The method includes fabricating a photovoltaic module including a semiconductor assembly. The fabrication step includes performing an efficiency enhancement treatment on the semiconductor assembly, wherein the efficiency enhancement treatment includes light soaking the semiconductor assembly, and heating the semiconductor assembly. The semiconductor assembly includes a window layer having an average thickness less than about 80 nanometers, wherein the window layer includes cadmium and sulfur. A related system is also presented.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: First Solar, Inc.
    Inventors: Bastiaan Arie Korevaar, Jinbo Cao, Adam Fraser Halverson, Scott Daniel Feldman-Peabody, Mark Jeffrey Pavol, Douglas Garth Jensen
  • Patent number: 8753915
    Abstract: The invention relates to the production of solar panels which comprise solar cells connected to one another. In this case, various layers are stacked onto one another, such as a film layer, bonding agent, insulating film, solar cells and a support layer. Combining all these layers to form the final panel is carried out on a carrier which stabilizes and supports the stack while it is conveyed past the various treatment stations. The turning over of the stack can also be carried out in a reliable manner by means of such a carrier without shifts between the various components with respect to one another occurring.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 17, 2014
    Assignee: Eurotron B.V.
    Inventors: Jan Bakker, Abraham Jan Verschoor, Simon Den Hartigh
  • Patent number: 8748957
    Abstract: A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co3O4(111). Other magnetic materials and oxides may be employed. A few ML field of graphene is deposited on the cobalt (III) oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: June 10, 2014
    Assignee: Quantum Devices, LLC
    Inventors: Jeffry Kelber, Peter Dowben
  • Patent number: 8748218
    Abstract: A solar cell and a method for manufacturing the same are discussed. The solar cell includes a substrate of a first conductive type, an emitter layer of a second conductive type opposite the first conductive type, a plurality of first electrodes each including a first electrode layer connected to the emitter layer and a second electrode layer positioned on the first electrode layer, at least one first current collector connected to the plurality of first electrodes, and a second electrode connected to the substrate. The emitter layer forms a p-n junction along with the substrate. The first electrode layer has a first width and the second electrode layer has a second width less than the first width of the first electrode layer.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: June 10, 2014
    Assignee: LG Electronics Inc.
    Inventors: Sungjin Kim, Youngsung Yang, Taeyoung Kwon, Seongeun Lee
  • Patent number: 8748952
    Abstract: A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tsung Chen, Hsun-Ying Huang, Yung-Cheng Chang, Yung-Fu Yeh, Yu-Ping Chen, Chi-Yuan Liang, Shou Shu Lu, Juan-Lin Chen, Jia-Ren Chen, Horng-Daw Shen, Chi-Hsun Hsieh
  • Publication number: 20140151835
    Abstract: A backside illuminated image sensor includes a substrate with a substrate depth, where the substrate includes a pixel region and a peripheral region. The substrate further includes a front surface and a back surface. The backside illuminated image sensor includes a first isolation structure formed in the pixel region of the substrate, where a bottom of the first isolation structure is exposed at the back surface of the substrate. The backside illuminated image sensor includes a second isolation structure formed in the peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. The backside illuminated image sensor includes an implant region adjacent to at least a portion of sidewalls of each isolation structure in the pixel region.
    Type: Application
    Filed: February 4, 2014
    Publication date: June 5, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Chieh HUANG, Chih-Jen WU, Chen-Ming HUANG, Dun-Nian YAUNG, An-Chun TU
  • Publication number: 20140151768
    Abstract: A pixel circuit including: a differential detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, the antenna being configured to be sensitive to terahertz radiation, and wherein: a first main conducting node of the first transistor is coupled to a first of the differential output nodes of the antenna; and a first main conducting node of the second transistor is coupled to a second of said differential output nodes of the antenna, wherein second main conducting nodes of the first and second transistors are formed by a common semiconductor region.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 5, 2014
    Inventors: Ullrich Pfeiffer, Hani Sherry, Andreia Cathelin
  • Patent number: 8741681
    Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Hideshi Abe, Masanori Ohashi, Atsushi Masagaki, Atsuhiko Yamamoto, Masakazu Furukawa
  • Patent number: 8742527
    Abstract: According to one embodiment, a solid state imaging device includes a sensor substrate curved such that an upper face having a plurality of pixels formed is recessed and an imaging lens provided on the upper face side.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Suzuki, Risako Ueno, Honam Kwon, Mitsuyoshi Kobayashi, Hideyuki Funaki
  • Patent number: 8742528
    Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: June 3, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
  • Publication number: 20140144482
    Abstract: When a tab wire 20 is connected to a busbar electrode 12 on a surface side of a photovoltaic cell 6, the bonding strength at the connection part can be improved and electric resistance can be reduced without reducing the amount of received light. The busbar electrode 12 and the tab wire 20 are bonded via conductive resin 22 having light-transmission property. This conductive resin 22 covers at least a part of a side face of the busbar electrode 12, and preferably reaches the surface of the photovoltaic cell 6. The tab wire 20 may have a width smaller than a width of the busbar electrode 12.
    Type: Application
    Filed: February 3, 2014
    Publication date: May 29, 2014
    Applicant: JX NIPPON OIL & ENERGY CORPORATION
    Inventors: Noriyo Ishimaru, Shigeki Kondo, Kiyoshi Murata, Yasushi Fukuda
  • Patent number: 8736009
    Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung Jun Park, Yong Woo Lee, Chang Rok Moon
  • Patent number: 8735208
    Abstract: A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) forming, from the front surface of the substrate, areas of same conductivity type as the substrate but of higher doping level, extending deep under the front surface, these areas being bordered with insulating regions orthogonal to the front surface; b) thinning the substrate from the rear surface to the vicinity of these areas and all the way to the insulating regions; c) partially hollowing out the insulating regions on the rear to surface side; and d) performing a laser surface anneal of the rear surface of the substrate.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: May 27, 2014
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Michel Marty
  • Patent number: 8735212
    Abstract: A silicon solar cell is manufactured by providing a carrier plate, and by applying a first contact pattern to the carrier plate. The first contact pattern includes a set of first laminar contacts. The silicon solar cell is further manufactured by applying a multitude of silicon slices to the first contact pattern, and by applying a second contact pattern to the multitude of silicon slices. Each first laminar contact of the set of first laminar contacts is in spatial laminar contact with maximally two silicon slices. The second contact pattern includes a set of second laminar contacts. Each second laminar contact of the set of second laminar contacts is in spatial laminar contact with maximally two silicon slices.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Rainer Klaus Krause, Gerd Pfeiffer, Hans-Juergen Eickelmann, Thorsten Muehge
  • Publication number: 20140137940
    Abstract: A solar cell module is obtained by the following method. In a step of sealing a solar cell module using laminated glass, a solar cell and a translucent intermediate film layer which seals the solar cell are interposed between a front side glass substrate and a rear side glass substrate. A sealing member in which an insertion part and an exterior part are formed by folding a sealing sheet having a bonding surface on one side, is employed in the module peripheral edge. The insertion part is inserted between the front side glass substrate and the rear side glass substrate, and bonding surfaces thereof are bonded to the front side glass substrate and the rear side glass substrate. A bonding surface of the exterior part is bonded to an end face of at least either of the front side glass substrate and the rear side glass substrate.
    Type: Application
    Filed: June 18, 2012
    Publication date: May 22, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazuyo Endo, Katsuhiro Imada, Jun Fujita
  • Patent number: 8728853
    Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: May 20, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Akie Yutani, Yasutaka Nishioka
  • Patent number: 8728852
    Abstract: A solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: May 20, 2014
    Assignee: Sony Corporation
    Inventors: Keiji Tatani, Takuji Matsumoto, Yasushi Tateshita, Fumihiko Koga, Takashi Nagano, Takahiro Toyoshima, Tetsuji Yamaguchi, Keiichi Nakazawa, Naoyuki Miyashita, Yoshihiko Nagahama
  • Publication number: 20140134779
    Abstract: Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. A method of producing an epitaxial silicon wafer includes a first step of irradiating a silicon wafer free of dislocation clusters and COPs with cluster ions to form a modifying layer formed from a constituent element of the cluster ions in a surface portion of the silicon wafer; and a second step of forming an epitaxial layer on the modifying layer of the silicon wafer.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 15, 2014
    Applicant: SUMCO CORPORATION
    Inventor: Takeshi Kadono
  • Publication number: 20140134780
    Abstract: Provided is an epitaxial silicon wafer with reduced metal contamination achieved by higher gettering capability and a method of efficiently producing the same. The method of producing an epitaxial wafer includes a wafer production step of pulling a single crystal silicon ingot having a COP formation region by Czochralski process, and subjecting the obtained single crystal silicon ingot to slicing, thereby producing a silicon wafer 10 including COPs; a cluster ion irradiation step of irradiating the produced silicon wafer 10 with cluster ions 16 to form a modifying layer 18 formed from a constituent element of the cluster ions 16, contained as a solid solution in a surface portion 10A of the silicon wafer 10; and an epitaxial layer formation step of forming an epitaxial layer 20 on the modifying layer 18 of the silicon wafer 10.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 15, 2014
    Applicant: SUMCO CORPORATION
    Inventor: Takeshi Kadono
  • Patent number: 8724366
    Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: May 13, 2014
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
  • Publication number: 20140124889
    Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Hsin-Chih Tai, Tiejun Dai, Duli Mao, Cunyu Yang, Howard E. Rhodes
  • Publication number: 20140128972
    Abstract: A prosthetic retina for implantation in an eye having a defective retina is formed from an array of nanowires having a predetermined spatial distribution, density, size and shape implanted in close proximity to the retina. An electrical conductor is formed at a first end of all nanowires in the array of nanowires and placed in contact with a bias source which biases the array. A plurality of electrodes is located on a second end of each of one nanowire or a bundle of nanowires in the array. Each nanowire produces a photocurrent at a corresponding electrode in response to detection of light impinging on the array of nanowires and the photocurrent stimulates one or more neurons adapted for visual perception. In the preferred embodiment, the predetermined spatial distribution mimics a distribution of rods and cones in a normal eye.
    Type: Application
    Filed: June 21, 2011
    Publication date: May 8, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Massoud L. Khraiche, Gabriel Silva, Gert Cauwenberghs, Yu-Hwa Lo, Deli Wang, William Freeman
  • Patent number: 8716821
    Abstract: A semiconductor device contains a photodiode which includes a buried collection region formed by a bandgap well to vertically confine photo-generated minority carriers. the bandgap well has the same conductivity as the semiconductor material immediately above and below the bandgap well. A net average doping density in the bandgap well is at least a factor of ten less than net average doping densities immediately above and below the bandgap well. A node of the photodiode, either the anode or the cathode, is connected to the buried collection region to collect the minority carriers, the polarity of the node matches the polarity of the minority carriers. The photodiode node connected to the buried collection region occupies less lateral area than the lateral area of the buried collection region.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: May 6, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Dimitar Trifonov Trifonov
  • Publication number: 20140120654
    Abstract: Disclosed herein is a method of manufacturing a bonded substrate, including the steps of: forming a first bonding layer on a surface on one side of a semiconductor substrate; forming a second bonding layer on a surface on one side of a support substrate; adhering the first bonding layer and the second bonding layer to each other; a heat treatment for bonding the first bonding layer and the second bonding layer to each other; and thinning the semiconductor substrate from a surface on the other side of the semiconductor substrate to form a semiconductor layer.
    Type: Application
    Filed: January 3, 2014
    Publication date: May 1, 2014
    Applicant: Sony Corporation
    Inventor: Nobutoshi Fujii
  • Patent number: 8710501
    Abstract: An electro-optical device includes a light-emitting layer provided with a white light-emitting element; and a reflective filter layer that is located at one side of the light-emitting layer and is provided with a reflective color filter.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: April 29, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Takashi Miyazawa
  • Publication number: 20140110762
    Abstract: A method for producing a solid-state imaging element which has photoconversion pixels, the method including forming an impurity region of the first conduction type and a second impurity region of the second conduction type on the impurity region of the first conduction type by ion implantation by using the same mask; forming on the surface of the semiconductor substrate a transfer gate constituting the charge transfer section which extends over the second impurity region of the second conduction type; forming a charge accumulating region of the first conduction type constituting the sensor section by ion implantation; and forming a first impurity region of the second conduction type, which has a higher impurity concentration than the second impurity region of the second conduction type, by ion implantation.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 24, 2014
    Applicant: Sony Corporation
    Inventors: Sanghoon Ha, Hiroaki Ishiwata
  • Publication number: 20140110809
    Abstract: According to one embodiment, a method of manufacturing a solid-state imaging device includes a trench forming process, a concave portion forming process, a coating process, and a burying process. In the trench forming process, a trench is formed at the position to isolate a plurality of photoelectric conversion elements. In the concave portion forming process, a concave portion is formed at the position to form a light shielding film of shielding at least part of subject light incident on an adjustment photoelectric conversion element used for an image quality adjustment of an imaged image. In the coating process, inner circumferential surfaces of the trench and the concave portion are coated with an insulating film. In the burying process, a light shielding member is buried inside the trench and the concave portion whose inner circumferential surface are coated with the insulating film.
    Type: Application
    Filed: April 22, 2013
    Publication date: April 24, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KITAMURA, Hisashi AIKAWA, Kazunori KAKEHI
  • Patent number: 8703520
    Abstract: Disclosed are: a printing plate having improved productivity; and a method for manufacturing a solar cell element, which uses the printing plate. A printing plate according to one embodiment of the present invention comprises: a metal plate; a buffer layer that is arranged on one main surface of the metal plate; and a slit that penetrates through the metal plate and the buffer layer. The slit has a first penetrating part that is located in the metal plate, a second penetrating part that is located in the buffer layer, and a bridge that is arranged inside and across the first penetrating part. When viewed in plan from the above-mentioned main surface side, the buffer layer-side opening edge of the first penetrating part is inside the metal plate-side opening edge of the second penetrating part.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 22, 2014
    Assignee: Kyocera Corporation
    Inventors: Yuta Shinike, Tomonari Sakamoto
  • Patent number: 8704324
    Abstract: A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 22, 2014
    Assignee: Sony Corporation
    Inventors: Susumu Hiyama, Kazufumi Watanabe
  • Patent number: 8703525
    Abstract: A solar cell includes; a substrate; a first electrode disposed on the substrate, and including a first groove formed therein, a semiconductor layer disposed on the first electrode, and including a second groove formed therein, and a second electrode disposed on the semiconductor layer and connected to the first electrode via the second groove, wherein a third groove passing through the first electrode, the semiconductor layer, and the second electrode is formed in a first region, a fourth groove passing through only the semiconductor layer and the second electrode is formed in a second region, and the first region and the second region are alternately disposed along a direction of extension of the third groove.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 22, 2014
    Assignees: Samsung SDI Co., Ltd., Samsung Display Co., Ltd.
    Inventor: Joong-Hyun Park
  • Publication number: 20140102520
    Abstract: A microsystems-enabled multi-junction photovoltaic (MEM-PV) cell includes a first photovoltaic cell having a first junction, the first photovoltaic cell including a first semiconductor material employed to form the first junction, the first semiconductor material having a first bandgap. The MEM-PV cell also includes a second photovoltaic cell comprising a second junction. The second photovoltaic cell comprises a second semiconductor material employed to form the second junction, the second semiconductor material having a second bandgap that is less than the first bandgap, the second photovoltaic cell further comprising a first contact layer disposed between the first junction of the first photovoltaic cell and the second junction of the second photovoltaic cell, the first contact layer composed of a third semiconductor material having a third bandgap, the third bandgap being greater than or equal to the first bandgap.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: Sandia Corporation
    Inventor: Sandia Corporation
  • Patent number: 8697477
    Abstract: Disclosed herein is a method for producing a solid-state imaging element which has pixels, each including a sensor section that performs photoelectric conversion and a charge transfer section that transfers charges generated by the sensor section. The method includes: forming an impurity region of the first conduction type and a second impurity region of the second conduction type on the impurity region of the first conduction type by ion implantation by using the same mask; forming on the surface of the semiconductor substrate a transfer gate constituting the charge transfer section which extends over the second impurity region of the second conduction type; forming a charge accumulating region of the first conduction type constituting the sensor section by ion implantation; and forming a first impurity region of the second conduction type, which has a higher impurity concentration than the second impurity region of the second conduction type, by ion implantation.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: April 15, 2014
    Assignee: Sony Corporation
    Inventors: Sanghoon Ha, Hiroaki Ishiwata
  • Patent number: 8697478
    Abstract: A removable cover system for protecting solar cells from exposure to moisture during fabrication processes. The cover system includes a cover having a configuration that complements the configuration of a solar cell substrate to be processed in an apparatus where moisture is present. A resiliently deformable seal member attached to the cover is positionable with the cover to engage and seal the top surface of the substrate. In one embodiment, the cover is dimensioned and arranged so that the seal member engages the peripheral angled edges and corners of the substrate for preventing the ingress of moisture beneath the cover. An apparatus for fabricating a solar cell using the cover and associated method are also disclosed.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 15, 2014
    Assignee: TSMC Solar Ltd.
    Inventors: Chih-Wei Huang, Keng-Hsin Chi, Chien-Nan Lin, Hua-Tso Wei