Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

Abstract: Wafer-level processing of wafer assemblies with transducers is described herein. A method in accordance with some embodiments includes forming a solid state transducer device by forming one or more trenches to define solid state radiation transducers. An etching media is delivered in to the trenches to release the transducers from a growth substrate used to fabricate the transducers. A pad can hold the radiation transducers and promote distribution of the etching media through the trenches to underetch and release the transducers.

Abstract: A method for producing a structure including an active part with a first and a second suspended zone. The method includes machining the front face of a first substrate to define the lateral contours of at least one first suspended zone according to a first thickness less than that of the first substrate forming a stop layer of etching of the first suspended zone under the suspended zone, forming on the front face of the first substrate a sacrificial layer, machining from the rear face of the first substrate up to releasing the sacrificial layer to form at least one second suspended zone to reach the stop layer of the first suspended zone, and releasing the first and second suspended zones.

Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm?2 to about 2000 cm?2.

Abstract: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of the substrate from an oblique direction with respect to the surface of the polishing pad.

Abstract: A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction.

Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.

Abstract: A method for treating silicon to form pillars, especially for use as the active anode material in Li-ion batteries, is disclosed. The process is simple to operate on a commercial scale since it uses a solution containing only a small number of ingredients whose concentration needs to be controlled and it can be cheaper to operate than previous processes. The solution includes: 0.01 to 5M HF 0.002 to 0.2M of metal ions capable of nucleating on and forming a porous layer comprising regions of elemental metal on the silicon surface; 0.001 to 0.7M of an oxidant selected from the group O2, O3, H2O2, the acid, ammonium or alkali metal salt of NO3?, S2O82?, NO2?, B4O72? and ClO4? or a mixture thereof. The treated silicon is suitably removed from the solution.

Abstract: A method for removing poly-silicon dummy gate structures using an ammonium hydroxide-hydrogen peroxide-water (APM) solution with concentrations between 1:10:20 and 1:1:2 and at temperatures between 20 C and 80 C for times between 1 minute and 60 minutes.

Abstract: A substrate processing apparatus includes a first processing chamber and a second processing chamber, a first substrate holding unit that holds a substrate in the first processing chamber, a chemical solution supply unit that supplies a chemical solution containing an etching component and a thickening agent to the substrate held by the first substrate holding unit, a substrate transfer unit that transfers the substrate from the first processing chamber to the second processing chamber in a state in which the chemical solution is held on the substrate, and a second substrate holding unit that holds a plurality of substrates on each of which the chemical solution is held in the second processing chamber.

Abstract: A quart resonator for use in lower frequency applications (typically lower than the higher end of the UHF spectrum) where relatively thick quartz members, having a thickness greater than ten microns, are called for.

Abstract: Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include hydantoin compounds and derivatives thereof in combination with alkoxylated glycols to inhibit the formation of flat areas between pyramid structures to improve the light absorption.

Abstract: A method of metal deposition may include chemically modifying a surface of a substrate to make the surface hydrophobic. The method may further include depositing a layer of metal over the hydrophobic surface and masking at least a portion of the deposited metal layer to define a conductive metal structure. The method may also include using an etching agent to etch unmasked portions of the deposited metal layer.

Abstract: A method of forming a metal pattern on a display substrate includes blanket depositing a copper-based layer having a thickness between about 1,500 ? and about 5,500 ? on a base substrate, and forming a patterned photoresist layer on the copper-based layer. The copper-based layer is over-etched by an etching composition containing an oxidizing moderating agent where the over-etch factor is between about 40% and about 200% while using the patterned photoresist layer as an etch stopping layer, and where the etching composition includes ammonium persulfate between about 0.1% by weight and about 50% by weight, includes an azole-based compound between about 0.01% by weight and about 5% by weight and a remainder of water. Thus, reliability of the metal pattern and that of manufacturing a display substrate may be improved.

Abstract: Methods are provided for producing a pristine hydrogen-terminated silicon wafer surface with high stability against oxidation. The silicon wafer is treated with high purity, heated dilute hydrofluoric acid with anionic surfactant, rinsed in-situ with ultrapure water at room temperature, and dried. Alternatively, the silicon wafer is treated with dilute hydrofluoric acid, rinsed with hydrogen gasified water, and dried. The silicon wafer produced by the method is stable in a normal clean room environment for greater than 3 days and has been demonstrated to last without significant oxide regrowth for greater than 8 days.

Abstract: The present disclosure suggests apparatus and methods that can be used to chemically process microfeature workpieces, e.g., semiconductor wafers. One implementation of the invention provides a method in which a surface of a microfeature workpiece is contacted with an etchant liquid. The wall of the processing chamber may be highly transmissive of an operative wavelength range of radiation, but the etchant liquid is absorptive of the operative wavelength range. The etchant liquid is heated by delivering radiation through the wall of a processing chamber. This permits processing chambers to be formed of materials (e.g., fluoropolymers) that cannot be used in conventional systems that must conduct heat through the wall of the processing chamber.

Abstract: The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least in the edge region and partially between the semiconductor components and the carrier system. The aim of the invention is to provide a detachable arrangement of electronic semiconductor components on a mechanically stable carrier system for safely handling the semiconductor components during the production process, wherein the capillarity of the gap between the semiconductor components and the carrier system is reduced in a controlled manner, thus preventing the damaging effect of a liquid medium seeping into the gap. To this end, the surface of the carrier system is shaped in such a way that the gap is widened along the entire edge region thereof.

Abstract: The present disclosure includes a texture formulation that includes an aliphatic diol, an alkaline compound and water which provides a consistent textured region across a silicon surface suitable for solar cell applications. Processes for texturing a crystalline silicon substrate using these formulations are also described.

Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.

Abstract: An LED array includes a substrate and a plurality of LEDs formed on the substrate. The LEDs are electrically connected with each other. Each of the LEDs includes a connecting layer, an n-type GaN layer, an active layer, and a p-type GaN layer formed on the substrate in sequence. The connecting layer is etchable by alkaline solution. A bottom surface of the n-type GaN layer which connects the connecting layer has a roughened exposed portion. The bottom surface of the n-type GaN layer has an N-face polarity. A method for manufacturing the LED array is also provided.

Abstract: A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.

Abstract: A method of forming a fine pattern includes forming first line mask patterns on a mask layer to extend along a direction, forming second line mask patterns to extend along a diagonal direction with respect to the first line mask patterns, anisotropically etching the mask layer exposed by the first and second line mask patterns to form elliptical openings, and isotropically etching the mask layer provided with the openings to form a mask pattern with enlarged openings.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.

Abstract: A metal plate having a pattern of protrusions on a first surface thereof is produced; photoresist is provided on a second surface of the metal plate; the photoresist is removed from a portion of the metal plate corresponding to a loop shaped outer peripheral cutout region that contacts the outer periphery of a mold region of the metal plate; and the metal plate is etched using the remaining photoresist as a mask, in a method for producing and a method for cutting a processing a master mold having a pattern of protrusions and recesses corresponding to data to be transferred on a surface thereof.

Abstract: There are provided a liquid processing method and a liquid processing apparatus capable of providing a high etching rate and a high etching selectivity for silicon nitride against silicon oxide, and a storage medium storing the method thereon. In the method for etching, by an etching solution, a substrate on which silicon nitride and silicon oxide are exposed, the etching solution is produced by mixing a fluorine ion source material, water and a boiling point adjusting agent; the produced etching solution is heated to a substrate processing temperature equal to or higher than 140° C.; after a temperature of the etching solution reaches the substrate processing temperature, the temperature of the etching solution is maintained at the substrate processing temperature for a first preset time; and after a lapse of the first preset time, the substrate is etched by the etching solution maintained at the substrate processing temperature.

Abstract: A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

Abstract: The present invention relates to a method of preparing a porous silicon nanorod structure composed of columnar bundles having a diameter of 50-100 nm and a length of 2-5 ?m, and a lithium secondary cell using the porous silicon nanorod structure as an anode active material. The present invention provides a high-capacity and high-efficiency anode active material for lithium secondary cells, which can overcome the low conductivity of silicon and improve the electrode deterioration attributable to volume expansion because it is prepared by electrodepositing the surface of silicon powder with metal and simultaneously etching the silicon powder partially using hydrofluoric acid.

Abstract: According to one embodiment, an etching method includes: supplying an etching-resistant material; and etching the silicon nitride film. The supplying includes supplying the etching-resistant material to a processing surface including a surface of a silicon nitride film and a surface of a non-etching film, the non-etching film including a material different from the silicon nitride film. The etching includes etching the silicon nitride film using an etchant in a state of the etching-resistant material being formed relatively more densely on the surface of the non-etching film than on the surface of the silicon nitride film.

Abstract: A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

Abstract: Disclosed are a liquid processing method, a liquid processing apparatus, and a recording medium that can prevent convex portions of a target substrate from collapsing when a rinsing liquid is dried. A base surface of a target substrate is hydrophilized and the surfaces of convex portions become water-repellent by surface-processing the target substrate which includes a main body, a plurality of convex portions protruding from the main body, and a base surface formed between the convex portions on the substrate main body. Next, a rinsing liquid is supplied to the target substrate which has been subjected to the surface processing. Thereafter, the rinsing liquid is removed from the target substrate.

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract: A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone.

Abstract: A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.

Abstract: A protective chuck is disposed on a substrate with a gas layer between the bottom surface of the protective chuck and the substrate surface. The gas layer protects a surface region against a fluid layer covering the substrate surface. In some embodiments, the pressure fluctuation at the gas layers is monitored, and through the dynamic feedback, the gas flow rate can be adjusted to achieve a desired operation regime. The dynamic control of operation regime setting can also be applied to high productivity combinatorial systems having an array of protective chucks.

Abstract: Disclosed is a thin-film transistor (10) manufacturing method that includes a process for forming a nitrate film (12x) that includes residual nickel (22) on a surface thereof, by bringing a nitric acid solution into contact with a polysilicon layer (11x); and a process for removing the nitrate film (12x) that includes residual nickel (22) from the polysilicon layer (11x) surface. With this surface treatment process, a polysilicon layer (11) with reduced concentration of a surface residual nickel (22) is provided, and a thin-film transistor (10) having excellent surface smoothness is attained.

Abstract: A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers.

Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.

Abstract: A protective chuck is disposed on a substrate with a gas bearing layer between the bottom surface of the protective chuck and the substrate surface. The gas bearing layer protects a surface region against a fluid layer covering the substrate surface. The protection of the gas bearing is a non-contact protection, reducing or eliminating potential damage to the substrate surface due to friction. The gas bearing can enable combinatorial processing of a substrate, providing multiple isolated processing regions on a single substrate with different material and processing conditions.

Abstract: Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.

Abstract: In some embodiments, the present invention discloses an etchant solution hydrochloric acid and nitric acid to etch doped polysilicon at low etch rates. The doped polysilicon can be doped with Ge, In, B and Ga. Preferably, the concentration of hydrochloric acid can be greater than 1 vol %, and the concentration of nitric acid is greater than 15 vol %.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.

Abstract: An organic light-emitting display device including a substrate; at least one thin-film transistor (TFT) formed on the substrate; a planarizing layer covering the TFT; a pixel electrode, which is formed on the planarizing layer and is connected to the TFT; a protective layer surrounding an edge of the pixel electrode; a pixel defining layer (PDL), which has an overhang (OH) structure protruding more than the top surface of the protective layer, covers the protective layer and the edge of the pixel electrode, and exposes a portion of the pixel electrode surrounded by the protective layer; a counter electrode facing the pixel electrode; and an intermediate layer, which is interposed between the pixel electrode and the counter electrode and includes a light-emitting layer and at least one organic layer, where the thickness of the intermediate layer is greater than the thickness of the protective layer.

Abstract: A method comprises: forming a first array of fins and a second array of fins on a substrate; masking off the first array of fins from the second array of fins with a first mask; depositing a dielectric layer on the second array of fins and on the first mask on the first array of fins; masking off the dielectric layer deposited on the second array of fins with a second mask; removing the dielectric layer and the first mask from the first array of fins; removing the second mask from the second array of fins to expose the dielectric layer on the second array of fins; and depositing a chemox layer on the first array of fins. The chemox layer is thinner than the dielectric layer on the second array of fins.

Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.

Abstract: A wafer recycling method comprises varying a temperature and pressure conditions to remove a first semiconductor layer deposited on a wafer, removing a remaining semiconductor layer on the wafer through a chemical or physical process, and washing the wafer.

Abstract: A manufacturing method of a magnetic recording medium according to one embodiment includes forming a mask layer having a pattern regularly arranged in a longitudinal direction on a magnetic recording medium containing a substrate and a magnetic recording layer, forming a recording portion having a magnetic pattern and a non-recording portion by patterning the magnetic recording layer, and submitting the mask layer to a peeling liquid to peel the mask layer. The mask layer contains a lamination layer of a lift-off layer, a first hard mask, and a second hard mask. The second hard mask is formed of a material that is different from the material of the first hard disk and the material is dissolvable in the same peeling liquid as the peeling liquid that dissolves the lift-off layer.

Abstract: A method for removing a plurality of dielectric materials from a supporting substrate by providing a substrate with a plurality of materials, contacting the substrate at a first temperature with a solution to more quickly remove a first dielectric material than a second dielectric material at the first temperature, and then contacting the substrate at a second temperature with a solution to more quickly remove the second dielectric material than the first dielectric material at the second temperature. Thus, the dielectric materials exhibit different etch rates when etched at the first and second temperatures. The solutions to which the first and second dielectric materials are exposed may contain phosphoric acid. The first dielectric material may be silicon nitride and the second dielectric material may be silicon oxide. Under these conditions, the first temperature may be about 175° C., and the second temperature may be about 155° C.

Abstract: A method for forming a contact opening, such as a via hole, is provided. In the method, a sacrificial layer is deposited over a damascene feature prior to exposing a conductor formed in a substrate at a bottom of the opening. The sacrificial layer is provided to prevent damage or contamination of materials used. Even after the conductor has been exposed once or more times, the sacrificial layer can be deposited over the damascene feature to protect it from further damage or contamination by a subsequent process that will further expose the conductor at the contact opening bottom. The exposing step may form a recess in the conductor. By further forming a trench feature over the contact opening, a dual damascene feature can be fabricated.

Abstract: A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.