Abstract: A method of processing III-Nitride epitaxial layer system on a substrate. The process includes exposing non-c-plane surfaces of the III-nitride epitaxial layer system, for example by etching to a selected depth or cleaving, and crystallographical etching the epitaxial layer system in order to obtain crystallographic plane surfaces. In an exemplary embodiment, the III-Nitride epitaxial layer system includes GaN. In accordance with one aspect of the exemplary embodiment, the etching step includes reactive ion etching in a chlorine-based plasma, PEC etching in a KOH solution or cleaving, and the crystallographical etching step includes immersing the epitaxial layer system in a crystallographic etching chemical, such as phosphoric acid, molten KOH, KOH dissolved in ethylene glycol, sodium hydroxide dissolved in ethylene glycol, tetraethyl ammonium hydroxide, or tetramethyl ammonium hydroxide.

Abstract: A porous semiconductor is created by electrochemical etching. Selected regions of a semiconductor are first treated to reduce the threshold potential at which pore formation occurs, and then an electrochemical etch is carried out on the semiconductor at a potential at least equal to the reduced threshold potential for the selected regions and less than the threshold potential for untreated regions. The selective treatment preferably involves implantation with the same ions as the semiconductor, i.e. Si ions for silicon. The treatment results in the formation of highly defined etch patterns or patterns of porous material depending on the process conditions.

Abstract: After an Si wafer is anisotropically etched through an etching mask having an opening in an anisotropically etching solution, an etching face of the Si wafer emerged by the anisotropic etching is subjected to anodic oxidation by applying a positive voltage for anodic oxidation on the Si wafer. As a result, the etching face of the Si wafer is isotropically etched due to the anodic oxidation in the anisotropic etching solution. By the isotropic etching thus performed, a sharp corner formed at an end portion of a recess portion formed in the Si wafer by the anisotropic etching, is rounded. Because the isotropic etching reaction progresses very slowly in comparison with the anisotropic etching, control of the etching can be made easy and accurately. As a result, the thickness of the diaphragm can be prevented from being dispersed.

Abstract: In accordance with the present invention, a method for expanding trenches includes the steps of forming a trench in a substrate, preparing surfaces within the trench by etching the surfaces with a wet etchant to provide a hydrogen terminated silicon surface and anisotropically wet etching the trench to expand the trench.

Abstract: A method of protecting a tungsten plug from corroding. After a tungsten plug is formed in a substrate, a wire is formed on the substrate to couple with the tungsten plug. The substrate is dipped into an electrolyte solution. The electrolyte solution is acid or alkaline enough to discharge charges accumulated on the wire. Then, a wet cleaning process is performed to remove polymer formed on the wire.

Abstract: The inventive method provides a wet cleaning of semiconductor devices on semiconductor wafers after photoresist is stripped. Semiconductor wafers are placed into a centrifuge carriage of a processing chamber. The centrifuge carriage rotates the semiconductor wafers. N-methylpyrrolidine heated to a temperature between 65° C. and 85° C. is sprayed onto the semiconductor wafers. Next N-methylpyrrolidine at room temperature is sprayed onto the semiconductor wafers. Finally, water at room temperature is sprayed onto the semiconductor wafers. The inventive method provides high throughput cleaning without undue corrosion or damage to metal layers.

Abstract: Disclosed are improved and simplified methods of forming trench isolation regions. A photoresist pattern having an opening therein is directly formed on a bare semiconductor substrate. The bare semiconductor substrate is etched through the opening in the photoresist pattern to form a trench in the substrate. The photoresist pattern is then isotropically etched to enlarge the size of the opening. A spin-on material layer is coated overlying the substrate surface to fill the trench and the enlarged opening, and then etched back until the photoresist pattern is exposed. After removing the photoresist pattern, the spin-on material layer is cured to form a trench isolation region which are less susceptible to edge defects.

Abstract: A method of forming selected Group III-nitride regions uses a masking layer to cause differential growth between single crystal Group III-nitride material and polycrystalline Group III-nitride material. The epitaxial process is chosen to provide vertical growth so as to allow for replication of the mask edges at the defined limits for the selected regions. By using an etchant that is selective between polycrystalline and single crystal Group III-nitride material, the polycrystalline material (that grew over the mask layer) can be removed, leaving only the single crystal Group III-nitride (that grew over the exposed substrate material).

Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.

Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.

Abstract: In order to improve the quality of a semiconductor product, mapping of the critical dimensions of predetermined features such as ring oscillators, test transistors, turning forks WET transistors etc., is carried out at various stages of the manufacturing process. For example, a reticle is mapped, the etch mask which is produced from the effect of the image on the resist layer, and the results of the etching are respectively mapped. Using the data gleaned from these mappings, it is determined if any of the control variables of a new etch process require adjustment to improve the quality of the end product. Therefore, when an etch process is introduced to the process, it is possible to run the diagnostic process and then work back via the collected critical dimension data to determine what changes in the control parameters are appropriate to improve the resulting product.

Abstract: A new method of pre-oxidation cleaning of a substrate surface is described. The surface of a semiconductor substrate of a wafer is cleaned using a multiple step cleaning process wherein the final step of the cleaning process comprises cleaning with a solution of H2SO4 and H2O2 whereby a chemical oxide initial layer is formed on the surface of the wafer. Thereafter, the surface of the wafer is oxidized to form a thermal oxide layer wherein the chemical oxide layer and the thermal oxide layer together form a gate oxide layer in the fabrication of an integrated circuit.

Abstract: A method for forming a capacitor on a substrate is disclosed herein. The method according to the present invention can increase the capacitance of a capacitor in one interface-etching process, the method mention above includes the following step. The first step is to form a storage node in a dielectric layer on the substrate, wherein the bottom of a cubic portion of the storage node faces the substrate is buried in the dielectric layer, and the storage node is coupled to the substrate. Next, interface-etching the dielectric layer to expose the surface including the bottom of the cubic portion of the storage node. In etching the dielectric layer made of BPSG, the buffer oxide etching (B.O.E) is utilized. Then an insulating layer is formed on the exposed surface including the bottom of the cubic portion of the storage node. Finally, a conductive layer is formed on the insulating layer. The storage node, the insulating layer, and the conductive layer constitute the capacitor.

Abstract: A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide layer and the gates, (c) forming a second oxide layer on the first dielectric layer, and (d) removing a portion of the second oxide layer for forming first spacers alongside each of the gates.

Abstract: A wafer cleaning process is disclosed for quenching etch reactions while rinsing etch reactants and etch products from the wafer. Holes are etched through an insulating layer by reactive ion etch, for example. The holes might comprise contact openings over a semiconductor substrate, or vias through insulating layers between metal lines. An organic or polymer residue left in the holes is cleaned by a wet process. The cleaning process continues to attack sidewalls of the holes, undesirably widening them. The wafer is therefore rinsed with a rinse agent below 0° C., thermally quenching further etching of the sidewalls and affording greater control over the hole dimensions. At the same time, the rinse agent allows relatively rapid diffusion of etchants and etch products from narrow and deep openings. An exemplary rinse agent for such low temperature rinsing is dilute ethylene glycol (C2H6O2).

Abstract: A microfabrication process for making enclosed, subsurface microfluidic tunnels, cavities, channels, and the like within suspended beams includes etching a single crystal silicon wafer to produce trenches defining a beam. The trench walls are oxidized, and the interior of the beam is etched through a channel via on the top of the beam to form a hollow beam with oxide sidewalls.

Abstract: In a wet-chemical treatment of a semiconductor substrate with a chemical treatment fluid containing ammonia and hydrogen peroxide, an experiment is carried out in a system where the concentrations of chemical species are known, to experimentally previously determine a relation between an etching rate of an SiO2 film with a mixture of ammonia and hydrogen peroxide and the concentrations of the dissolved chemical species (calculated by a chemical equilibrium analysis) or the temperature of the chemical treatment fluid, and the determined relation is then expressed. The concentrations of the chemical species are calculated by the chemical equilibrium analysis on the basis of values measured by a chemical treatment fluid composition monitor at a suitable interval and values measured by a fluid temperature sensor, and in accordance with the expressed relation, the etching rate of the SiO2 film with the chemical treatment fluid is calculated at the suitable interval.

Abstract: A new method is provided for the creation of a pre-molded chip carrier. The invention teaches putting magnetic inserts into the upper mold. The magnetic inserts attract the lead fingers that are inserted into the upper mold during the process of filling the cavity with a compound pressing the lead fingers tightly against the surface of the magnet. The possibility of mold compound spilling over the lead fingers and forming resin depositions on the surface of the lead fingers is thereby voided.

Abstract: A process for producing a semiconductor device includes the following sequential steps: producing a semiconductor body having an Al.sub.x Ga.sub.1-x As layer with an upper surface, where x.ltoreq.0.40; applying a contact metallization made of a non-noble metallic material to the Al.sub.x Ga.sub.1-x As layer; precleaning a semiconductor surface to produce a hydrophilic semiconductor surface; roughening the upper surface of the Al.sub.x Ga.sub.1-x As layer by etching with an etching mixture of hydrogen peroxide.gtoreq.30% and hydrofluoric acid.gtoreq.40% (1000:6) for a period of from 1 to 2.5 minutes; and re-etching with a dilute mineral acid. According to another embodiment, 0.ltoreq.x.ltoreq.1 and the upper surface of the Al.sub.x Ga.sub.1-x As layer is roughened by etching with nitric acid 65% at temperatures of between 0.degree. C. and 30.degree. C.

Abstract: A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.

Abstract: The present invention is directed to wet processing methods for the manufacture of electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, this invention relates to methods, for example, prediffusion cleaning, stripping, and etching of electronic component precursors using sequential chemical processing techniques.

Abstract: A method for forming a single cavity in a substrate, which may extend approximately the length of a device located on top of the substrate, and device produced thereby. The device has a length and a width, and may extend approximately the length of the substrate. After locating the device on the surface of the substrate, a first etchant is applied through openings on the surface of the substrate. Subsequently, a second etchant is applied through the same openings on the surface of the substrate. As a result, a single cavity is formed beneath the surface of the device, suspending the device and minimizing electrical coupling.

Abstract: The present invention provides a method of forming a dual damascene structure on a semiconductor wafer. The semiconductor wafer comprises a substrate, and a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a photoresist layer sequentially formed on the substrate. A dry-etching process is performed first to vertically remove a specific portion of the second silicon oxide layer down to the silicon nitride layer so as to form a hole. Then the photoresist layer is removed and the portion of the silicon nitride layer positioned under the hole is removed using a phosphoric acid solution. A lithographic process is then performed to form a photoresist layer on the second silicon oxide layer, the photoresist layer comprising a line-shaped opening positioned above the hole with a width larger than the diameter of the hole. Then an etching process is performed along the line-shaped opening to vertically remove the second silicon oxide layer and the first silicon oxide layer.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon. The process comprising the steps of aligning said area of said wafer, such as an alignment mark on the wafer, to an etchant dispensing apparatus, placing the surface of the wafer adjacent at least a portion of an annular portion of the etchant dispensing apparatus, dispensing at least one etchant onto said area of said wafer, such as an alignment mark, and removing the at least one etching from the wafer.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate following at least one etch back process associated with a spacer formation and/or subsequent resistor protect etching process or processes. The method eliminates the need to use HF acid in the stripping process by substantially reducing the thickness of the BARC during each of the etching back processes, such that, only a thin layer of BARC material remains that can be easily removed with phosphoric acid.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H.sub.2 SO.sub.4, H.sub.3 PO.sub.4, HNO.sub.3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: A process for etching silicon nitride from a multilayer structure which uses an etchant gas including a fluorocarbon gas, a hydrogen source, and a weak oxidant. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas. The fluorocarbon gas is selected from CF.sub.4, C.sub.2 F.sub.6, and C.sub.3 F.sub.8 ; the hydrogen source is selected from CH.sub.2 F.sub.2, CH.sub.3 F, and H.sub.2 ; and the weak oxidant is selected from CO, CO.sub.2, and O.sub.2.

Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.

Abstract: A micromachining method is disclosed for forming a suspended micromechanical structure from {111} crystalline silicon. The micromachining method is based on the use of anisotropic dry etching to define lateral features of the structure which are etched down into a {111}-silicon substrate to a first etch depth, thereby forming sidewalls of the structure. The sidewalls are then coated with a protection layer, and the substrate is dry etched to a second etch depth to define a spacing of the structure from the substrate. A selective anisotropic wet etchant (e.g. KOH, EDP, TMAH, NaOH or CsOH) is used to laterally undercut the structure between the first and second etch depths, thereby forming a substantially planar lower surface of the structure along a {111} crystal plane that is parallel to an upper surface of the structure.

Abstract: A process for etching nitride layers in three steps is disclosed. The process comprises selecting a process chemistry of CF.sub.4 to CHF.sub.3 to set a predetermined critical dimension bias; conducting a primary etch of the process chemistry which will have a high etch rate; and conducting a secondary etch of ion bombardment having a lower etch rate and high selectivity to pad oxide. In selecting the process chemistry, selecting greater amounts of CHF.sub.3 will result in higher polymer concentration on the etched sidewall. Varying the pressure and power can also be used to vary the polymer concentration. This in turn is used to select the desired critical dimension bias. The secondary etch uses a mixture of NF.sub.3 and HBr and is performed at a high pressure and a low power to promote high nitride to oxide selectivity.

Abstract: A solar cell comprising multi-crystalline silicon or an alloy thereof, having a surface that is to receive light radiation, wherein said silicon surface includes a multi-tude of pits of depth lying in the range 0.10 .mu.m to 10 .mu.m and of diameter lying in the range 0.1 .mu.m to 10 .mu.m, and in which the ratio of said depth to said diameter is greater than 1, the area of said holes occupying more than half the area of said silicon surface.

Abstract: A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.

Abstract: A method for forming a contact hole in a phosphosilicate glass layer includes the steps of forming a phosphosilicate glass layer, reflowing the phosphosilicate glass layer, removing a surface portion of the phosphosilicate glass layer, and forming the contact hole in the phosphosilicate glass layer. In particular, the surface portion of the phosphosilicate glass layer can be on the order of about 1000 .ANG. thick, and the step of removing the surface portion can include etching the surface portion. Furthermore, the step of forming the contact hole can include the step of selectively wet etching the phosphosilicate glass layer followed by the step of selectively dry etching the phosphosilicate glass layer.

Abstract: A method is provided to remove crystal regions from silicon wafers which are damaged as a consequence of mechanical machining of the silicon wafers. The silicon wafers are pretreated with an aqueous solution containing hydrogen fluoride. Then the wafers are etched in an aqueous solution exposed to ultrasound and containing alkali metal hydroxide at temperatures from 55.degree. C. to 95.degree. C.

Abstract: Trench structures (12,32,35,46) are formed in single crystal silicon substrates (10,30) that have either a (110) or (112) orientation. A selective wet etch solution is used that removes only the exposed portions of the single crystal silicon substrates (10,30) that are in the (110) or (112) crystal planes. The trench structures (12,32,35,46) are defined by the {111} crystal planes in the single crystal silicon substrate (10,30) that are exposed during the selective wet etch process. Trench structures (32,35) can be formed on both sides of a single crystal silicon substrate (30) to form an opening (34). Opening (34) can be used as an alignment mark to align front side processing to backside and vice versa. Trench structures can also be use to form a microstructure (41,61) for a sensor (40,60).

Abstract: A method of removing inorganic contamination (contamination 104 of FIGS. 2a-2b) from a layer (layer 102) overlying a substrate (substrate 100), the method comprising the steps of: removing the layer overlying the substrate with at least one removal agent; reacting the inorganic contamination with at least one conversion agent, thereby converting the inorganic contamination; removing the converted inorganic contamination by subjecting it to at least one solvent agent, the solvent agent included in a first supercritical fluid; and wherein the converted inorganic contamination is more highly soluble in the solvent agent than the inorganic contamination.

Abstract: A method of fabricating a specimen for analyzing defects of a semiconductor device is disclosed. The method includes the steps of: cutting a wafer to be adjacent to a defective portion that exists in a patterned layer formed on a substrate; molding the first specimen with a resin; grinding the substrate of the first specimen with a predetermined slope; and etching the ground face to expose the defective layer, wherein the wafer includes a semiconductor substrate and patterned layers where memory devices are formed on the semiconductor substrate.

Abstract: This is a method for improving contact openings during the manufacture of an integrated circuit. The process of forming a contact in an integrated circuit is often carried out rapidly, with imperfect control. As a result, incomplete removal of the insulating material may occur within the contact opening. In addition, the substrate material may be damaged to some extent within the contact opening by the contact formation process. In either case, high electrical resistance within the contact may result. Photo-resist may leave residue within the contact opening, low surface dopant concentrations, and insulative layer discontinuities may cause increased electrical resistance within the contact. A sequential application of two types of aqueous etchants will smooth the contact sidewall and remove a thin layer of relatively low dopant concentration at the surface of the substrate and other debris which may remain from the contact formation process and thereby allow lower resistance contacts to be formed.

Abstract: A hybrid stamp structure for lithographic processing of features below 1 micron is described, comprising a deformable layer (14) for accommodating unevenness of the surface of a substrate, and a patterned layer on the deformable layer in which a lithographic pattern is engraved. The stamp structure is further enhanced by comprising a third layer (16), which acts as rigid support for the stamp, thus preventing an undesired deformation of the stamp under load.

Abstract: A method for fabricating an integrated circuit device includes the steps of forming an insulating layer on a substrate and forming a plurality of parallel conductive lines on the insulating layer. An etch barrier is formed on each of the parallel conductive lines, and contact holes are formed between the etch barriers. The contact holes expose portions of the substrate without exposing the plurality of parallel conductive lines. In particular, the contact holes can be formed by forming a patterned mask layer on the insulating layer and etch barriers, and etching exposed portions of the insulating layer. The patterned mask layer selectively exposes a plurality of parallel strips orthogonal to the plurality of parallel conductive lines. Related structures are also discussed.