Layers Formed Of Diverse Composition Or By Diverse Coating Processes Patents (Class 438/763)
  • Patent number: 8623750
    Abstract: A film of silicon dioxide is formed on the silicon-germanium layer, and a high dielectric constant film is further formed on the film of silicon dioxide. First irradiation from a flash lamp is performed on the semiconductor wafer to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 3 milliseconds to 1 second. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 3 milliseconds to 1 second. This promotes the crystallization of the high dielectric constant film while suppressing the alleviation of distortion in the silicon-germanium layer.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: January 7, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Kazuhiko Fuse, Shinichi Kato
  • Publication number: 20140001607
    Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chi CHUANG, Kun-Ming HUANG, Hsuan-Hui HUNG, Ming-Yi LIN
  • Patent number: 8618002
    Abstract: The present invention provides a pattern formation method capable of preventing formation of surface defects. In the method, a resist surface after subjected to exposure is coated with an acidic film and then subjected to heating treatment. This method is suitably adopted in a process employing liquid immersion lithography and/or light of short wavelength, such as ArF excimer laser beams, for producing a very fine pattern.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: December 31, 2013
    Assignee: AZ Electronic Materials USA Corp.
    Inventors: Wenbing Kang, Xiaowei Wang, Yuriko Matsuura
  • Patent number: 8618003
    Abstract: Electronic devices can be prepared by forming a patterned thin film on a suitable receiver substrate. A cyanoacrylate polymer is used as a deposition inhibitor material and applied first as a deposition inhibitor material. The deposition inhibitor material can be patterned to provide selected areas on the receiver substrate where the deposition inhibitor is absent. An inorganic thin film is then deposited on the receiver substrate using a chemical vapor deposition technique only in those areas where the deposition inhibitor material is absent. The cyanoacrylate polymer deposition inhibitor material can be applied by thermal transfer from a donor element to a receiver substrate before a patterned thin film is formed.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 31, 2013
    Assignee: Eastman Kodak Company
    Inventors: Mitchell S. Burberry, David H. Levy
  • Patent number: 8617989
    Abstract: Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 ?m. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: December 31, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kedar Sapre, Manuel Hernandez, Lei Luo
  • Publication number: 20130337656
    Abstract: A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.
    Type: Application
    Filed: August 15, 2013
    Publication date: December 19, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Publication number: 20130328137
    Abstract: A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO2, using atomic layer deposition. Forming the refractory metal silicon nitride film may include forming a film of tantalum silicon nitride using a physical vapor deposition process. Annealing the gate dielectric stack may include annealing the gate dielectric stack in an oxygen-bearing ambient at approximately 750 C for 10 minutes or less. In one embodiment, annealing the dielectric stack includes annealing the dielectric stack for approximately 60 seconds at a temperature of approximately 500 C.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Rama I. Hegde
  • Patent number: 8603924
    Abstract: A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Chia-Cheng Chen, Clement Hsingjen Wann
  • Patent number: 8603877
    Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: December 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Noel Rocklein, Chris Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
  • Patent number: 8603919
    Abstract: A semiconductor device fabricating method includes forming an etch target layer and a first hard mask layer over a substrate, forming a second hard mask pattern having lines over the first hard mask layer, forming a third hard mask layer over the second hard mask pattern, forming a sacrificial pattern over the third hard mask layer, forming a cell spacer on sidewalls of the sacrificial pattern, removing the sacrificial pattern, etching the third hard mask layer using the cell spacer as an etch barrier, etching the first hard mask layer using the third hard mask pattern and the second hard mask pattern as etch barriers, forming an elliptical opening having an axis pointing in a second direction by etching the etch target layer, and forming a silicon layer that fills the elliptical opening.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: December 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jung-Dae Han
  • Publication number: 20130320508
    Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.
    Type: Application
    Filed: March 8, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tamotsu Owada, Hikaru Ohira, Hirosato Ochimizu
  • Publication number: 20130320509
    Abstract: A moisture barrier coating for protecting a substrate from moisture, comprises an inorganic layer disposed over the substrate, the inorganic layer comprising an oxide or nitride of an element selected from the group consisting of silicon, aluminum, titanium, zirconium, hafnium and combinations thereof; and an organic silicon-containing layer disposed over the inorganic layer.
    Type: Application
    Filed: August 5, 2013
    Publication date: December 5, 2013
    Applicant: Applied Microstructures, Inc.
    Inventors: Boris Kobrin, Nikunj Hirji Dangaria, Romuald Nowak, Michael T. Grimes
  • Publication number: 20130320510
    Abstract: An article having a surface treated to provide a protective coating structure in accordance with the following method: vapor depositing a first layer on a substrate, wherein said first layer is a metal oxide adhesion layer selected from the group consisting of an oxide of a Group IIIA metal element, a Group IVB metal element, a Group VB metal element, and combinations thereof; vapor depositing a second layer upon said first layer, wherein said second layer includes a silicon-containing layer selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride; and vapor depositing a third layer upon said second layer, wherein said third layer is a functional organic-comprising layer, wherein said functional organic-comprising layer is a SAM.
    Type: Application
    Filed: August 5, 2013
    Publication date: December 5, 2013
    Applicant: Applied Microstructures, Inc.
    Inventors: Boris Kobrin, Nikunj Dangaria, Romuald Nowak, Michael T. Grimes
  • Patent number: 8598044
    Abstract: An intermediate film 222 in a three-layered resist film 225 is formed by the chemical vapor deposition process at a temperature not higher than 300° C., using Si(OR1)(OR2)(OR3)(OR4), where each of R1, R2, R3 and R4 independently represents a carbon-containing group or a hydrogen atom, excluding the case where all of R1 to R4 are hydrogen atoms.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: December 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Sadayuki Ohnishi, Masayuki Hiroi, Akira Matsumoto
  • Publication number: 20130313656
    Abstract: Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Applicant: Intermolecular, Inc.
    Inventor: Jinhong Tong
  • Patent number: 8592324
    Abstract: A method for forming a laminated structure including an amorphous carbon film on an underlying layer includes forming an initial layer containing Si—C bonds on a surface of the underlying layer, by supplying an organic silicon gas onto the underlying layer; and forming the amorphous carbon film by thermal film formation on the underlying layer with the initial layer formed on the surface thereof, by supplying a film formation gas containing a hydrocarbon compound gas onto the underlying layer.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: November 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Okada, Yukio Tojo
  • Publication number: 20130307126
    Abstract: A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is lower than the energy bandgap of the first metal oxide layer and that of the third metal oxide layer. The semiconductor structure includes a metal oxide layer on a substrate, wherein the energy bandgap of the metal oxide layer changes along a direction perpendicular to the surface of the substrate. The present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Inventors: Chen-Kuo Chiang, Chun-Hsien Lin
  • Patent number: 8580584
    Abstract: A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 12, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Yun Wang, Tony P. Chiang, Chi-I Lang
  • Publication number: 20130292807
    Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: ASM IP HOLDINGS B.V.
    Inventors: Petri Raisanen, Michael Givens, Mohith Verghese
  • Patent number: 8575021
    Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, Tony P. Chiang, Anh Duong, Zachary Fresco, Nitin Kumar, Chi-I Lang, Sandra G. Malhotra, Jinhong Tong
  • Patent number: 8575039
    Abstract: A surface treating method for treating a surface of a substrate inside a process chamber includes the steps of generating an atmosphere containing no moisture in the process chamber, heating the substrate inside the atmosphere containing no moisture in the process chamber; and causing a reaction between the substrate and an adhesion accelerating agent by feeding the adhesion accelerating agent gas into the process chamber.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Yamaguchi, Hiroyuki Hashimoto
  • Patent number: 8569753
    Abstract: The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Yoshinori Ieda, Keitaro Imai, Kiyoshi Kato, Yuto Yakubo, Yuki Hata
  • Publication number: 20130280918
    Abstract: Described are apparatus and methods for forming silicon interfacial layers on germanium or III-V materials. Such silicon layers may be deposited by atomic layer deposition at specific temperatures to avoid interdiffusion of silicon and the germanium or III-V material.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 24, 2013
    Inventor: Khaled Z. AHMED
  • Publication number: 20130280836
    Abstract: A method of selectively applying a material to a surface of a substrate from a stamp with a raised surface using an energy activated release layer is provided. The release layer is applied to at least a first portion of a surface of the stamp. A layer of the material is applied to the raised surface of the stamp. The raised surface of the stamp is placed in contact with the surface of the substrate such that the material layer is situated therebetween. Thereafter, the release layer is activated with energy, causing the material layer to release from the raised surface of the stamp, and to adhere to the surface of the substrate. Alternatively, the entire stamp surface may be coated with the release layer and the release layer may be selectively activated in the areas in which the material on the stamp surface is in contact with the substrate.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: EMAGIN CORPORATION
    Inventors: Amalkumar P. Ghosh, Ronald W. Wake
  • Patent number: 8564025
    Abstract: An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Conal E. Murray, Jeffrey W. Sleight
  • Patent number: 8558385
    Abstract: An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2? in the intermediate region, where d2<d2?.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeman Yoon, Yungi Kim, Kangyoon Lee, Youngwoong Son
  • Publication number: 20130264659
    Abstract: Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active species on the halogen-sensitive metal-including layer, the metal-including active species being derived from a non-halogenated metal oxide precursor. The example method also includes reacting an oxygen-containing reactant with the metal-including active species to form the metal oxide protective layer.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: ASM IP HOLDINGS B.V.
    Inventor: Sung-Hoon Jung
  • Patent number: 8551891
    Abstract: Methods of treating the interior of a plasma region are described. The methods include a preventative maintenance procedure or the start-up of a new substrate processing chamber having a remote plasma system. A new interior surface is exposed within the remote plasma system. The (new) interior surfaces are then treated by sequential steps of (1) forming a remote plasma from hydrogen-containing precursor within the remote plasma system and then (2) exposing the interior surfaces to water vapor. Steps (1)-(2) are repeated at least ten times to complete the burn-in process. Following the treatment of the interior surfaces, a substrate may be transferred into a substrate processing chamber. A dielectric film may then be formed on the substrate by flowing one precursor through the remote plasma source and combining the plasma effluents with a second precursor flowing directly to the substrate processing region.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Lili Ji, Nitin K. Ingle
  • Publication number: 20130260573
    Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang Lee, Yun-Yue Lin, Hung-Chang Hsieh, Chia-Jen Chen, Yih-Chen Su, Ta-Cheng Lien, Anthony Yen
  • Patent number: 8535998
    Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fung Ka Hing, Haiting Wang, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
  • Patent number: 8536017
    Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masaru Kadoshima, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
  • Publication number: 20130230989
    Abstract: A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.
    Type: Application
    Filed: March 5, 2012
    Publication date: September 5, 2013
    Applicant: United Microelectronics Corporation
    Inventors: An-Chi LIU, Chih-Wen Teng, Tzu-Yu Tseng, Chi-Heng Lin
  • Patent number: 8519470
    Abstract: A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sun-won Kang, Hwan-sik Lim
  • Patent number: 8507389
    Abstract: Methods for forming a dielectric layer on a substrate are provided herein. In some embodiments a method for forming a dielectric layer on a substrate may include exposing the substrate to a first source gas comprising a silicon precursor and an oxidizer for a first period of time to form a first layer comprising silicon and oxygen; and exposing the substrate to a second source gas comprising a metal precursor and the silicon precursor for a second period of time to form a second layer comprising silicon and a metal, where in the first layer and the second layer form the dielectric layer.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 13, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Lucien Date, Paul William Turnbull
  • Patent number: 8507388
    Abstract: In some embodiments, a reducing gas ambient containing a reducing agent is established in a batch process chamber before substrates are subjected to a deposition. The reducing atmosphere is established before and/or during loading of the substrates into the process chamber, and can include flowing reducing gas into the process chamber while the chamber is open. The reducing gas can be a mixture of a reducing agent and an inert gas, with the reducing agent being a minority component of the reducing gas. Using the reducing gas ambient, oxidation of substrate surfaces is reduced.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: August 13, 2013
    Assignee: ASM International N.V.
    Inventors: Steven R. A. Van Aerde, Rene de Blank
  • Publication number: 20130203266
    Abstract: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Bernd Hintze, Frank Koschinsky
  • Patent number: 8501634
    Abstract: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Gin-Chen Huang, Tsuo-Wen Lu, Chien-Liang Lin, Yu-Ren Wang
  • Patent number: 8501609
    Abstract: A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 6, 2013
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Avi Strum
  • Publication number: 20130196514
    Abstract: Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 1, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Maurice E. EWERT, Anantha SUBRAMANI, Umesh M. KELKAR, Chandrasekhar BALASUBRAMANYAM, Joseph M. RANISH
  • Publication number: 20130196515
    Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Robert D. Clark
  • Patent number: 8497218
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: July 30, 2013
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
  • Patent number: 8481430
    Abstract: The present invention provides a method of manufacturing a semiconductor device. The method includes stacking a SiO2 film, a N-containing stopper film, and a resist pattern in this order on a semiconductor substrate, performing etching on the stopper film and the SiO2 film with a F-containing etching gas, with the resist pattern serving as a mask to form an opening, and performing ashing on the resist pattern to remove the resist pattern, using a gas containing an oxygen gas and an inert gas under the condition that the ratio of the oxygen radical to the inert-gas radical becomes equal to or lower than 5.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: July 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Ryou Sato
  • Publication number: 20130171834
    Abstract: Disclosed herein are methods of forming a film stack which may include the plasma accelerated deposition of a silicon nitride film formed from the reaction of nitrogen containing precursor with silicon containing precursor, the plasma accelerated substantial elimination of silicon containing precursor from the processing chamber, the plasma accelerated deposition of a silicon oxide film atop the silicon nitride film formed from the reaction of silicon containing precursor with oxidant, and the plasma accelerated substantial elimination of oxidant from the processing chamber. Also disclosed herein are process station apparatuses for forming a film stack of silicon nitride and silicon oxide films which may include a processing chamber, one or more gas delivery lines, one or more RF generators, and a system controller having machine-readable media with instructions for operating the one or more gas delivery lines, and the one or more RF generators.
    Type: Application
    Filed: November 7, 2012
    Publication date: July 4, 2013
    Inventors: Jason Haverkamp, Pramod Subramonium, Joe Womack, Dong Niu, Keith Fox, John Alexy, Patrick Breiling, Jennifer O'Loughlin, Mandyam Spiram, George Andrew Antonelli, Bart van Schravendijk
  • Publication number: 20130171835
    Abstract: The purpose of the present invention to provide: a composition which can be used for water-repellent treating of the entire surface of a semiconductor substrate having a pattern formed by laminating a Si-containing insulating layer and a metal layer, at one time; and a method for water-repellent treatment of the semiconductor substrate surface using the composition. The present invention relates to: (1) a composition for water-repellent treatment of a semiconductor substrate surface comprising a) at least one kind of a compound selected from the group consisting of a long-chain alkyl tertiary amine and a long-chain alkyl ammonium salt, b) a base or an acid generating agent, having a condensed ring structure or forming a condensed ring structure by generating a base or an acid and c) a polar organic solvent, and (2) a method for water-repellent treatment of the semiconductor substrate surface having the pattern formed by laminating the Si-containing insulating layer and the metal layer, using the composition.
    Type: Application
    Filed: September 7, 2011
    Publication date: July 4, 2013
    Applicant: WAKO PURE CHEMICAL INDUSTRIES, LTD.
    Inventors: Hironori Mizuta, Yoji Urano, Masahiko Kakizawa
  • Publication number: 20130164945
    Abstract: A film deposition method includes an adsorption step of adsorbing a first reaction gas onto a substrate by supplying the first reaction gas from a first gas supplying portion for a predetermined period without supplying a reaction gas from a second gas supplying portion while separating a first process area and a second process area by supplying a separation gas from a separation gas supplying portion and rotating a turntable; and a reaction step of having the first reaction gas adsorbed onto the substrate react with a second reaction gas by supplying the second reaction gas from the second gas supplying portion for a predetermined period without supplying a reaction gas from the first gas supplying portion while separating the first process area and the second process area by supplying the separation gas from the separation gas supplying portion and rotating the turntable.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 27, 2013
    Applicant: Tokyo Electron Limited
    Inventor: Tokyo Electron Limited
  • Patent number: 8471267
    Abstract: A semiconductor device of the present invention has a semiconductor element region 17 that is provided in part of a silicon carbide layer 3 and a guard-ring region 18 that is provided in another part of the silicon carbide layer 3 surrounding the semiconductor element region 17 when seen in a direction perpendicular to a principal surface of the silicon carbide layer 3.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Masashi Hayashi, Koichi Hashimoto, Kazuhiro Adachi
  • Patent number: 8470719
    Abstract: Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer, and a phase-change layer formed between the first and second reactant layers due to a solid-state reaction between a material forming the first reactant layer and a material forming the second reactant layer. The phase-change memory device consumes low power and operates at high speed.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: June 25, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Yun Lee, Young Sam Park, Sung Min Yoon, Soon Won Jung, Byoung Gon Yu
  • Patent number: 8470718
    Abstract: A vapor deposition reactor includes a chamber filled with a first material, and at least one reaction module in the chamber. The reaction module may be configured to make a substrate pass the reaction module through a relative motion between the substrate and the reaction module. The reaction module may include an injection unit for injecting a second material to the substrate. A method for forming thin film includes positioning a substrate in a chamber, filling a first material in the chamber, moving the substrate relative to a reaction module in the chamber, and injecting a second material to the substrate while the substrate passes the reaction module.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: June 25, 2013
    Assignee: Synos Technology, Inc.
    Inventor: Sang In Lee
  • Publication number: 20130149873
    Abstract: A thin film including characteristics of low permittivity, high etching resistance and high leak resistance is to be formed. A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; and forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer.
    Type: Application
    Filed: December 8, 2012
    Publication date: June 13, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: HITACHI KOKUSAI ELECTRIC INC.
  • Publication number: 20130149874
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a thin film containing a predetermined element on a substrate by repeating a cycle, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer; and modifying a surface of the second layer by supplying a hydrogen-containing gas to the substrate.
    Type: Application
    Filed: December 8, 2012
    Publication date: June 13, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: HITACHI KOKUSAI ELECTRIC INC.