Nitridation Patents (Class 438/775)
  • Patent number: 7888154
    Abstract: To provide an elemental technique for improving the emission intensity of deep ultraviolet light from a light emitting layer made of an AlGaInN-based material, in particular, an AlGaN-based material. First, an AlN layer is grown on a sapphire surface. The AlN layer is grown under a NH3-rich condition. The TMAl pulsed supply sequence includes growing an AlGaN layer for 10 seconds, interrupting the growth for 5 seconds to remove NH3, and then introducing TMAl at a flow rate of 1 sccm for 5 seconds. After that, the growth is interrupted again for 5 seconds. Defining this sequence as one growth cycle, five growth cycles are carried out. By such growth, an AlGaN layer having a polarity of richness in Al can be obtained. The above sequence is described only for illustrative purposes, and various variations are possible. In general, the Al polarity can be achieved by a process of repeating both growth interruption and supply of an Al source.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: February 15, 2011
    Assignee: Riken
    Inventors: Hideki Hirayama, Tomoaki Ohashi, Norihiko Kamata
  • Patent number: 7884003
    Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 ?-?m2 or even less than or equal to 1 ?-?m2 for the electrical device.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: February 8, 2011
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 7879737
    Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: February 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-Hee Sohn, Gil-Heyun Choi, Byung-Hee Kim, Byung-Hak Lee, Tae-Ho Cha, Hee-Sook Park, Jae-Hwa Park, Geum-Jung Seong
  • Patent number: 7875534
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: January 25, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou
  • Patent number: 7871939
    Abstract: A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Gyu Dong Cho, Ho Jin Cho, Hyun Jung Kim
  • Patent number: 7867917
    Abstract: By providing a barrier layer stack including a thin SiCN layer for enhanced adhesion, a silicon nitride layer for confining a copper-based metal region (thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region), and a SiCN layer, the total relative permittivity may still be maintained at a low level, since the thickness of the first SiCN layer and of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: January 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joerg Hohage, Matthias Lehr, Volker Kahlert
  • Patent number: 7863179
    Abstract: Various embodiments provide improved processes and systems that produce a barrier layer with decreasing nitrogen concentration with the increase of film thickness. A barrier layer with decreasing nitrogen concentration with film thickness allows the end of barrier layer with high nitrogen concentration to have good adhesion with a dielectric layer and the end of barrier layer with low nitrogen concentration (or metal-rich) to have good adhesion with copper. An exemplary method of depositing a barrier layer on an interconnect structure is provided. The method includes (a) providing an atomic layer deposition environment, (b) depositing a barrier layer on the interconnect structure with a first nitrogen concentration during a first phase of deposition in the atomic layer deposition environment.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: January 4, 2011
    Assignee: Lam Research Corporation
    Inventors: Hyungsuk Alexander Yoon, Fritz Redeker
  • Patent number: 7863202
    Abstract: An integrated circuit can be formed with a high-k dielectric layer. A first titanium oxide layer is deposited over a substrate using a first ALD process. A first metal oxide layer is also deposited over the substrate using a second ALD process. A second titanium oxide layer is deposited over the substrate using a third ALD process and a second metal oxide layer is deposited over the substrate using a fourth ALD process. The first and second metal oxides are preferably strontium oxide and/or aluminum oxide.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 4, 2011
    Assignee: Qimonda AG
    Inventor: Shrinivas Govindarajan
  • Patent number: 7858509
    Abstract: A disclosed substrate processing method in a single wafer substrate processing device including a first process position for introducing nitrogen atoms to a high-dielectric film and a second process position for performing heat treatment on the high-dielectric film includes: successively conveying plural substrates to be processed to the first process position and the second process position one by one; and successively performing the introduction of nitrogen atoms and the heat treatment on the high-dielectric film on the substrates to be processed, wherein the treatment on the substrate to be processed is started within 30 seconds at the second process position after the process at the first position.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: December 28, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Miki Aruga, Kazuyoshi Yamazaki, Shintaro Aoyama, Kouji Shimomura
  • Publication number: 20100323529
    Abstract: A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface; a step of performing first nitriding to the silicon exposed on the surface of the substrate, and forming a silicon nitride film having a thickness of 0.2 nm but not more than 1 nm on the surface of the substrate; and a step of performing first heat treatment to the silicon nitride film in N2O atmosphere and forming a silicon nitride film. This method may further include a step of performing second nitriding to the silicon oxynitride film, and furthermore, may include a step of performing second heat treatment to the silicon oxynitride film after the second nitriding.
    Type: Application
    Filed: December 20, 2007
    Publication date: December 23, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
  • Patent number: 7851383
    Abstract: Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: December 14, 2010
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xiaopeng Yu, Sean F. Zhang
  • Patent number: 7842621
    Abstract: The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2?T2N)/(T2?T1N)}×100 (1).
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: November 30, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Jiro Katsuki, Tetsuro Takahashi, Shuuichi Ishizuka
  • Patent number: 7825014
    Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Hong-Seon Yang, Tae-Kwon Lee, Won Kim, Kwan-Yong Lim, Seung-Ryong Lee
  • Patent number: 7821056
    Abstract: A nonvolatile semiconductor memory device includes an array of nonvolatile memory cell transistors, each of which is configured such that a tunnel insulation film, a floating gate electrode, a floating gate insulation film and a control gate electrode are stacked on a surface of a semiconductor substrate. A mean roughness of an interface between a polysilicon, of which the floating gate electrode is formed, and the floating gate insulation film is 1.5 nm or less.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: October 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Wakako Takeuchi
  • Patent number: 7820557
    Abstract: In a substrate nitriding method for nitriding a target substrate by allowing a nitrogen-containing plasma to act on silicon on a surface of the substrate in a processing chamber of a plasma processing apparatus, the nitridation by the nitrogen-containing plasma is performed by controlling a sheath voltage Vdc around the substrate to be less than or equal to about 3.5 eV. The sheath voltage Vdc is a potential difference Vp?Vf between a plasma potential Vp in a plasma generating region and a floating potential Vf of the substrate.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: October 26, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Minoru Honda, Toshio Nakanishi
  • Patent number: 7816281
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon substrate, and forming a silicon nitride film on the silicon oxide film. The step of forming the silicon nitride film includes the steps of growing a first silicon layer having a thickness larger than a thickness of a monoatomic silicon layer, nitriding the first silicon layer to form a first silicon nitride layer, growing a second silicon layer on the first silicon layer on the first silicon nitride layer, and nitriding the second silicon oxide layer to form a second silicon nitride layer.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: October 19, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Motoyuki Kono
  • Patent number: 7811896
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: October 12, 2010
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Bishnu Prasanna Gogoi
  • Patent number: 7803678
    Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: September 28, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Kevin L. Beaman, John T. Moore
  • Patent number: 7799649
    Abstract: The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: September 21, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Reima Tapani Laaksonen
  • Patent number: 7790627
    Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 7, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Publication number: 20100210118
    Abstract: A thin film can be formed on a substrate at a low temperature with a practicable film-forming rate. There is provided a semiconductor device manufacturing method for forming an oxide or nitride film on a substrate. The method comprises: exposing the substrate to a source gas; exposing the substrate to a modification gas comprising an oxidizing gas or a nitriding gas, wherein an atom has electronegativity different from that of another atom in molecules of the oxidizing gas or the nitriding gas; and exposing the substrate to a catalyst. The catalyst has acid dissociation constant pKa in a range from 5 to 7, but a pyridine is not used as the catalyst.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 19, 2010
    Applicant: HITACHI-KOKUSAI ELECTRIC, INC.
    Inventor: Norikazu Mizuno
  • Patent number: 7776761
    Abstract: A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and removing the mask layer pattern. The method further includes growing a silicon oxide layer on the semiconductor substrate to form gate insulating layers having different thicknesses from one another on the first and second regions.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Sik Park
  • Patent number: 7772129
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
  • Patent number: 7759260
    Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jay S Burnham, John J Ellis-Monaghan, James S Nakos, James J Quinlivan
  • Patent number: 7749919
    Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
  • Patent number: 7737050
    Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Edward Dennis Adams, Jay Sanford Burnham, Evgeni Gousev, James Spiros Nakos, Heather Elizabeth Preuss, Joseph Francis Shepard, Jr.
  • Patent number: 7727828
    Abstract: A method for fabricating a gate dielectric of a field effect transistor is provided. In one embodiment, the method includes removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer, and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma. In another embodiment, the oxide layer on the gate dielectric layer is formed by forming a thermal oxide layer, i.e., depositing the oxide layer on the gate dielectric layer.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: June 1, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Thai Cheng Chua, Cory Czarnik, Andreas G. Hegedus, Christopher Sean Olsen, Khaled Z. Ahmed, Philip Allan Kraus
  • Patent number: 7723205
    Abstract: There is provided a semiconductor device, in which characteristics of the semiconductor device are improved by thinning a gate insulating film and a leak current can be reduced, and a manufacturing method thereof. An aluminum film which is a metal film is formed over a polycrystalline semiconductor film, and plasma oxidizing treatment is performed to the aluminum film, whereby an aluminum oxide film is formed by oxidizing the aluminum film, and a silicon oxide film is formed between the polycrystalline semiconductor film and the aluminum oxide film.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: May 25, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventor: Tetsuya Kakehata
  • Patent number: 7723241
    Abstract: According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently, it is possible to improve quality of the oxynitride film, resulting in a reduced leakage current, an improved operating speed, and improved NBTI resistance.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: May 25, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Seiji Matsuyama, Toshio Nakanishi, Shigenori Ozaki, Hikaru Adachi, Koichi Takatsuki, Yoshihiro Sato
  • Patent number: 7718548
    Abstract: A process to form a copper-silicon-nitride layer on a copper surface on a semiconductor wafer is described. The process may include the step of exposing the wafer to a first plasma made from helium. The process may also include exposing the wafer to a second plasma made from a reducing gas, where the second plasma removes copper oxide from the copper surface, and exposing the wafer to silane, where the silane reacts with the copper surface to selectively form copper silicide. The process may further include exposing the wafer to a third plasma made from ammonia and molecular nitrogen to form the copper silicon nitride layer.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: May 18, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Sang M. Lee, Vladimir Zubkov, Zhenijiang Cui, Meiyee Shek, Li-Qun Xia, Hichem M'Saad
  • Patent number: 7704806
    Abstract: A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: April 27, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Gee-Sung Chae, Mi-Kyung Park
  • Patent number: 7696107
    Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 13, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Toshiharu Yamauchi, Tunenori Yamauchi, Kumiko Toyota
  • Patent number: 7695981
    Abstract: A seed layer is formed on a substrate using a first biological agent. The seed layer may comprise densified nanoparticles which are bound to the biological agent. The seed layer is then used for a deposition of a metal layer, such as a barrier layer, an interconnect layer, a cap layer and/or a bus line for a solid state device.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: April 13, 2010
    Assignee: Siluria Technologies, Inc.
    Inventors: Haixia Dai, Khashayar Pakbaz, Michael Spaid, Theo Nikiforov
  • Patent number: 7682973
    Abstract: A method of forming a Carbon NanoTube (CNT) structure and a method of manufacturing a Field Emission Device (FED) using the method of forming a CNT structure includes: forming an electrode on a substrate, forming a buffer layer on the electrode, forming a catalyst layer in a particle shape on the buffer layer, etching the buffer layer exposed through the catalyst layer, and growing CNTs from the catalyst layer formed on the etched buffer layer.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ha-Jin Kim, In-Taek Han, Young-Chul Choi, Kwang-Seok Jeong
  • Patent number: 7682988
    Abstract: A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Husam N. Alshareef, Rajesh Khamankar, Ajith Varghese, Cathy A. Chancellor, Anand Krishnan, Malcolm J. Bevan
  • Patent number: 7678672
    Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: March 16, 2010
    Assignee: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Vincent Gambin, Roger Su-Tsung Tsai
  • Patent number: 7674722
    Abstract: In the present invention, when a gate insulation film in a DRAM is formed, an oxide film constituting a base of the gate insulation film is plasma-nitrided. The plasma nitridation is performed with microwave plasma generated by using a plane antenna having a large number of through holes. Nitrogen concentration in the gate insulation film formed by the plasma nitridation is 5 to 20% in atomic percentage. Even without subsequent annealing, it is possible to effectively prevent a boron penetration phenomenon in the DRAM and to reduce traps in the film causing deterioration in driving capability of the device.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: March 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuo Nishita, Shuuichi Ishizuka, Yutaka Fujino, Toshio Nakanishi, Yoshihiro Sato
  • Patent number: 7670965
    Abstract: A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 2, 2010
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Yoshinobu Nakada, Hiroyuki Shiraki
  • Patent number: 7658973
    Abstract: A method of forming a dielectric film that includes nitrogen. The method includes incorporating nitrogen into a dielectric film using a nitridation gas and a rapid thermal annealing process, wherein an ultra-low pressure of equal to or less than about 10 Torr is used for the rapid thermal annealing process.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: February 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Pravin K. Narwankar, Gary E. Miner, Arnaud Lepert
  • Patent number: 7659214
    Abstract: A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a first wet process gas comprising water vapor into the process chamber, and reacting the substrate with the first wet process gas to grow an oxide film on the substrate. The method further includes flowing a second wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber, and reacting the oxide film and the substrate with the second wet process gas to grow an oxynitride film. In another embodiment, the method further comprises annealing the substrate containing the oxynitride film in an annealing gas. According to one embodiment of the method where the substrate is silicon, a silicon oxynitride film can be formed that exhibits a nitrogen peak concentration of approximately 3 atomic % or greater.
    Type: Grant
    Filed: September 30, 2007
    Date of Patent: February 9, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Kimberly G. Reid, Anthony Dip
  • Patent number: 7651953
    Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: January 26, 2010
    Assignee: ASM America, Inc.
    Inventors: Michael A. Todd, Keith D. Weeks, Christiaan J. Werkhoven, Christophe F. Pomarede
  • Patent number: 7648923
    Abstract: A method of fabricating a flash memory device is disclosed. The method comprises forming a first insulating layer on a semiconductor substrate; accumulating nitrogen at an interface between the semiconductor substrate and the first insulating layer to form a second insulating layer at the interface; and implanting oxygen into the second insulating layer to convert the second insulating layer to a third insulating layer.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: January 19, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Shil Park, Kwon Hong, Jae Hong Kim, Jae Hyoung Koo
  • Patent number: 7645647
    Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: January 12, 2010
    Assignee: LG. Display Co., Ltd.
    Inventors: Gee-Sung Chae, Mi-Kyung Park
  • Patent number: 7635655
    Abstract: A method for performing an oxidation process on a plurality of substrates in a batch processing system. According to one embodiment, the method includes selecting a N2O-based oxidation process for the substrates including a first process gas containing N2O that thermally decomposes in a process chamber of the batch processing system to N2, O2, and NO byproducts, and generating a replacement NO-based oxidation process for the substrates including a second process gas containing N2, O2, and NO with molar concentrations that mimic that of the N2, O2, and NO byproducts in the N2O-based oxidation process. According to another embodiment of the invention, the NO-based oxidation process contains NO, O2, and an inert gas.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: December 22, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Anthony Dip
  • Patent number: 7629270
    Abstract: A nitrogen precursor that has been activated by exposure to a remotely excited species is used as a reactant to form nitrogen-containing layers. The remotely excited species can be, e.g., N2, Ar, and/or He, which has been excited in a microwave radical generator. Downstream of the microwave radical generator and upstream of the substrate, the flow of excited species is mixed with a flow of NH3. The excited species activates the NH3. The substrate is exposed to both the activated NH3 and the excited species. The substrate can also be exposed to a precursor of another species to form a compound layer in a chemical vapor deposition. In addition, already-deposited layers can be nitrided by exposure to the activated NH3 and to the excited species, which results in higher levels of nitrogen incorporation than plasma nitridation using excited N2 alone, or thermal nitridation using NH3 alone, with the same process temperatures and nitridation durations.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: December 8, 2009
    Assignee: ASM America, Inc.
    Inventors: Johan Swerts, Hilde De Witte, Jan Willem Maes, Christophe F. Pomarede, Ruben Haverkort, Yuet Mei Wan, Marinus J. De Blank, Cornelius A. Van Der Jeugd, Jacobus Johannes Beulens
  • Patent number: 7622396
    Abstract: A semiconductor device is produced by providing a reaction chamber with a substrate and sequentially repeating steps of: supplying a first kind of gas into the reaction chamber, exhausting the first kind of gas from the reaction chamber, supplying a second kind of gas into the reaction chamber, and exhausting the second kind of gas from the reaction chamber to process the substrate disposed in the reaction chamber. The first kind of gas is pre-reserved in an intermediate portion of a supply path through which the first kind of gas flows, and is supplied into the reaction chamber with exhaust of the reaction chamber being substantially stopped.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: November 24, 2009
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuyuki Okuda, Yasushi Yagi, Toru Kagaya, Masanori Sakai
  • Patent number: 7622402
    Abstract: The surface of an insulating film disposed on an electronic device substrate is irradiated with plasma based on a process gas comprising at least an oxygen atom-containing gas, to thereby form an underlying film at the interface between the insulating film and the electronic device substrate. A good underlying film is provided at the interface between the insulating film and the electronic device substrate, so that the thus formed underlying film can improve the property of the insulating film.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 24, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki, Seiji Matsuyama, Kazuhide Hasebe, Shigeru Nakajima, Tomonori Fujiwara
  • Patent number: 7615500
    Abstract: A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: November 10, 2009
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Kensuke Takano, Ichiro Yamamoto, Koji Watanabe
  • Patent number: 7601404
    Abstract: A method for switching decoupled plasma nitridation (DPN) processes of different doses, which is able to decrease the switching time, is provided. According to the method, a dummy wafer is inserted into a chamber, a process gas introduced is ignited into plasma, and then a DPN doping process of the next dose is performed on the dummy wafer. The nitrogen concentration of the chamber is thus adjusted rapidly to switch to the DPN process of the next dose. In addition, after several cycles of the above steps are repeated, a dummy wafer is inserted into the chamber, and a complete DPN process of the next dose is performed on the dummy wafer. This process is performed several times before switching to the next DPN process.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: October 13, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Ying-Wei Yen, Yun-Ren Wang, Shu-Yen Chan, Chen-Kuo Chiang, Chung-Yih Chen
  • Patent number: 7569502
    Abstract: A SiOxNy gate dielectric and a method for forming a SiOxNy gate dielectric by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 and then exposing the structure to a plasma comprising a nitrogen source are provided. In one aspect, the structure is annealed after it is exposed to a plasma comprising a nitrogen source. In another aspect, a SiOxNy gate dielectric is formed in an integrated processing system by heating a structure comprising a silicon oxide film on a silicon substrate in an atmosphere comprising NH3 in one chamber of the integrated processing system and then exposing the structure to a plasma comprising a nitrogen source in another chamber of the integrated processing system.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: August 4, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Olsen, Faran Nouri, Thai Cheng Chua