Using Electromagnetic Or Wave Energy Patents (Class 438/776)
  • Patent number: 9412773
    Abstract: A photoelectric conversion section contains a semiconductor element having a laminated structure which contains an electroconductor, a semiconductor, and an insulator provided between the electroconductor and the semiconductor, in which the insulator is a silicon oxide film containing nitrogen in a main portion located between the electroconductor and the semiconductor.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: August 9, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Katsunori Hirota
  • Patent number: 9349877
    Abstract: A nonvolatile trapped-charge memory device and method of fabricating the same are described. Generally, the memory device includes a tunneling layer on a substrate, a charge trapping layer on the tunneling layer, and a blocking layer on the charge trapping layer. The tunneling layer includes a nitrided oxide film formed by annealling an oxide grown on the substrate using a nitrogen source. The tunneling layer comprises a first region proximate to the substrate, and a second region proximate to the charge trapping layer, and wherein the nitrogen concentration decreases from a first interface between the second region and the charge trapping layer to a second interface between the first region and the substrate to reduce nitrogen trap density at the second interface. Other embodiments are also described.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 24, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Frederick B. Jenne
  • Patent number: 9275865
    Abstract: Methods for plasma treatment of films to remove impurities are disclosed herein. Methods for removing impurities can include positioning a substrate with a barrier layer in a processing chamber, the barrier layer comprising a barrier metal and one or more impurities, maintaining the substrate at a bias, creating a plasma comprising a treatment gas, the treatment gas comprising an inert gas, delivering the treatment gas to the substrate to reduce the ratio of one or more impurities in the barrier layer, and reacting a deposition gas comprising a metal halide and hydrogen-containing gas to deposit a bulk metal layer on the barrier layer. The methods can further include the use of diborane to create selective nucleation in features over surface regions of the substrate.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: March 1, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Benjamin C. Wang, Joshua Collins, Michael Jackson, Avgerinos V. Gelatos, Amit Khandelwal
  • Patent number: 9130238
    Abstract: Methods of and hybrid factories for thin-film battery manufacturing are described. A method includes operations for fabricating a thin-film battery. A hybrid factory includes one or more tool sets for fabricating a thin-film battery.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 8, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Byung-Sung Kwak, Stefan Bangert, Dieter Haas, Omkaram Nalamasu
  • Patent number: 9076651
    Abstract: SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 7, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Khaled Ahmed, Frank Greer, Raj Jammy
  • Patent number: 9054048
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes exposing a first layer of a substrate to a plasma formed from a process gas comprising predominantly a mixture of ammonia (NH3) and a noble gas, wherein ammonia is about 0.5 to about 15 percent of the process gas; and maintaining the process chamber at a pressure of about 10 mTorr to about 80 mTorr while exposing the first layer to the plasma to transform at least an upper portion of the first layer into a nitrogen-containing layer.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: June 9, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Malcolm J. Bevan, Christopher S. Olsen, Johanes Swenberg
  • Patent number: 9018109
    Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
  • Patent number: 9006064
    Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Barry P. Linder, Shahab Siddiqui
  • Patent number: 8932964
    Abstract: A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Jin Lee, Ji-Soon Park, Jong-Myeong Lee, Hyun-Bae Lee
  • Publication number: 20150004803
    Abstract: When forming a TiN film to be formed as a metallic hard mask for etching a film formed on a substrate to be processed, a first step and a second step are repeated a plurality of times to form a TiN film having reduced film stress. In the first step (step 1), the substrate to be processed is conveyed into a processing chamber, TiCl4 gas and a nitriding gas are fed into the processing chamber, the interior of which being kept in a depressurized state during this time, and a plasma from the gases is generated to form a TiN unit film. In the second step (step 2), a nitriding gas is fed into the processing container, a plasma of the gas is generated, and the TiN unit film is subjected to plasma nitriding.
    Type: Application
    Filed: December 12, 2012
    Publication date: January 1, 2015
    Inventors: Hideaki Yamasaki, Takeshi Yamamoto
  • Patent number: 8916483
    Abstract: Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 23, 2014
    Assignee: SOITEC
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8916484
    Abstract: Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: December 23, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Yoshitaka Yokota
  • Patent number: 8906790
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 9, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Publication number: 20140295676
    Abstract: A method of operating vertical heat treatment apparatus includes: cleaning interior of vertical reaction chamber by supplying cleaning gas; pre-coating the interior of the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas; eliminating charges by loading substrate holding unit holding a dummy semiconductor substrate or a conductive substrate into the reaction chamber and supplying the second gas while generating plasma from the second gas without supplying the first gas; loading the substrate holding unit holding a plurality of product semiconductor substrates into the reaction chamber; and forming thin film in the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 2, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Keisuke SUZUKI, Yutaka MOTOYAMA
  • Publication number: 20140273518
    Abstract: Methods of forming a layer on a substrate may include providing a substrate to a process chamber, the process chamber having a gas port, an exhaust, and a plasma port disposed between the gas port and the exhaust; providing a process gas from the gas port in a first direction such that the process gas flows across the substrate; providing a plasma such that a flow of the plasma interacts with a flow of the process gas at an angle that is non-perpendicular; and rotating the substrate while providing the process gas and the plasma, wherein a thickness profile of the layer is controlled by adjusting at least one of a flow velocity of the process gas, a flow velocity of the plasma, the angle the flow of the plasma interacts with the flow of the process gas, or a direction of rotation of the substrate.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: MATTHEW S. ROGERS, KEVIN BAUTISTA
  • Publication number: 20140273517
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a first temperature; and exposing the first layer to an RF plasma formed from a process gas comprising ammonia (NH3) to transform the first layer into a nitrogen-containing layer, wherein the plasma has an ion energy of less than about 8 eV.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: THERESA KRAMER GUARINI, WEI LIU
  • Patent number: 8802578
    Abstract: A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 12, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zuozhen Fu, Huaxiang Yin, Jiang Yan
  • Patent number: 8748259
    Abstract: Methods and apparatus for selective one-step nitridation of semiconductor substrates is provided. Nitrogen is selectively incorporated in silicon regions of a semiconductor substrate having silicon regions and silicon oxide regions by use of a selective nitridation process. Nitrogen containing radicals may be directed toward the substrate by forming a nitrogen containing plasma and filtering or removing ions from the plasma, or a thermal nitridation process using selective precursors may be performed. A remote plasma generator may be coupled to a processing chamber, optionally including one or more ion filters, showerheads, and radical distributors, or an in situ plasma may be generated and one or more ion filters or shields disposed in the chamber between the plasma generation zone and the substrate support.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Theresa Kramer Guarini, Matthew Scott Rogers, Yoshitaka Yokota, Johanes S. Swenberg, Malcolm J. Bevan
  • Patent number: 8741785
    Abstract: Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: June 3, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Yoshitaka Yokota
  • Patent number: 8741784
    Abstract: A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 3, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Te-Lin Sun, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8741714
    Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: June 3, 2014
    Assignee: Sandisk 3D LLC
    Inventor: Donovan Lee
  • Patent number: 8716156
    Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
  • Patent number: 8685757
    Abstract: A method for fabricating a magnetic tunnel junction element includes forming a magneto resistance layer including a first magnetic layer, an insulation layer and a second magnetic layer on a substrate, forming a magnetic loss area by doping a magnetic loss impurity into a region of the magneto resistance layer to cause a magnetic loss, and etching the magnetic loss area to form a magnetic tunnel junction element.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Dong Ha Jung, Gyu An Jin, Su Ryun Min
  • Publication number: 20140051262
    Abstract: Described are methods of making silicon nitride (SiN) materials and other silicon-containing films, including carbon-containing and/or oxygen-containing films such as SiCN (also referred to as SiNC), SiON and SiONC films, on substrates. According to various embodiments, the methods involve electromagnetic radiation-assisted activation of one or more reactants. In certain embodiments, for example, the methods involve ultraviolet (UV) activation of vapor phase amine coreactants. The methods can be used to deposit silicon-containing films, including SiN and SiCN films, at temperatures below about 400° C.
    Type: Application
    Filed: May 15, 2012
    Publication date: February 20, 2014
    Inventors: Adrien Lavoie, Bhadri Varadarajan, Jon Henri, Dennis Hausmann
  • Patent number: 8647993
    Abstract: Described are methods of making silicon nitride (SiN) materials and other silicon-containing films, including carbon-containing and/or oxygen-containing films such as SiCN (also referred to as SiNC), SiON and SiONC films, on substrates. According to various embodiments, the methods involve electromagnetic radiation-assisted activation of one or more reactants. In certain embodiments, for example, the methods involve ultraviolet (UV) activation of vapor phase amine coreactants. The methods can be used to deposit silicon-containing films, including SiN and SiCN films, at temperatures below about 400° C.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: February 11, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Bhadri Varadarajan, Jon Henri, Dennis Hausmann
  • Patent number: 8609519
    Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 17, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Albert Lee, Tony P. Chiang, Jason Wright
  • Patent number: 8568606
    Abstract: A substrate processing method uses a substrate processing apparatus including a chamber for accommodating a substrate, a lower electrode to mount the substrate, a first RF power applying unit for applying an RF power for plasma generation into the chamber, and a second RF power applying unit for applying an RF power for bias to the lower electrode. The RF power for plasma generation is controlled to be intermittently changed by changing an output of the first RF power applying unit at a predetermined timing. If no plasma state or an afterglow state exists in the chamber by a control of the first RF power applying unit, an output of the second RF power applying unit is controlled to be in an OFF state or decreased below an output of the second RF power applying unit when the output of the first RF power applying unit is a set output.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 29, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Ohse, Shinji Himori, Jun Abe, Norikazu Yamada
  • Patent number: 8546273
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method of forming a nitrogen-containing layer may include placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas consisting essentially of ammonia (NH3) and an inert gas while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 1, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Malcolm J. Bevan, Johanes Swenberg, Son T. Nguyen, Wei Liu, Jose Antonio Marin, Jian Li
  • Patent number: 8547085
    Abstract: An arrangement for measuring process parameters within a processing chamber is provided. The arrangement includes a probe arrangement disposed in an opening of an upper electrode. Probe arrangement includes a probe head, which includes a head portion and a flange portion. The arrangement also includes an o-ring disposed between the upper electrode and the flange portion. The arrangement further includes a spacer made of an electrically insulative material positioned between the head portion and the opening of the upper electrode to prevent the probe arrangement from touching the upper electrode. The spacer includes a disk portion configured for supporting an underside of the flange portion. The spacer also includes a hollow cylindrical portion configured to encircle the head portion. The spacer forms a right-angled path between the o-ring and an opening to the processing chamber to prevent direct line-of-sight path between the o-ring and the opening to the processing chamber.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: October 1, 2013
    Assignee: Lam Research Corporation
    Inventors: Jean-Paul Booth, Douglas Keil
  • Patent number: 8507971
    Abstract: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: August 13, 2013
    Assignee: Spansion LLC
    Inventor: Satoshi Torii
  • Patent number: 8502286
    Abstract: A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Dong-Suk Shin, Pan-Kwi Park
  • Publication number: 20130196516
    Abstract: Described are methods of making silicon nitride (SiN) materials and other silicon-containing films, including carbon-containing and/or oxygen-containing films such as SiCN (also referred to as SiNC), SiON and SiONC films, on substrates. According to various embodiments, the methods involve electromagnetic radiation-assisted activation of one or more reactants. In certain embodiments, for example, the methods involve ultraviolet (UV) activation of vapor phase amine coreactants. The methods can be used to deposit silicon-containing films, including SiN and SiCN films, at temperatures below about 400° C.
    Type: Application
    Filed: May 15, 2012
    Publication date: August 1, 2013
    Inventors: Adrien Lavoie, Bhadri Varadarajan, Jon Henri, Dennis Hausmann
  • Patent number: 8492291
    Abstract: The present invention provides a method for manufacturing a gate dielectric (710) that includes providing a nitrided dielectric layer (220) over a substrate (120). The nitrided dielectric layer (220) has a nonuniform concentration of nitrogen in a bulk thereof. The nitrided dielectric layer (220) is exposed to oxygen radicals (410), resulting in a reduction of the non-uniformity.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 23, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Reima T. Laaksonen
  • Patent number: 8481433
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas comprising nitrogen while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer. In some embodiments, the process gas includes ammonia (NH3).
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 9, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Malcolm J. Bevan, Johanes Swenberg, Son T. Nguyen, Wei Liu, Jose Antonio Marin, Jian Li
  • Publication number: 20130171837
    Abstract: A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner.
    Type: Application
    Filed: January 2, 2012
    Publication date: July 4, 2013
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8426868
    Abstract: An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Publication number: 20130072028
    Abstract: A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicant: United Microelectronics Corp.
    Inventors: CHIEN-LIANG LIN, Te-Lin Sun, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8318586
    Abstract: Two plates, each comprising a thin layer of silicon or silicon oxide at a surface thereof, are bonded by subjecting the thin layer of at least one of the plates to a surface treatment step forming a silicon oxynitride superficial thin film with a thickness of less than 5nm. The thin film is performed with a nitrogen-based plasma generated by an inductively coupled plasma source. Furthermore, a potential difference applied between the plasma and a substrate holder supporting said plate during the surface treatment step is less than 50 V, advantageously less than 15 V and preferably zero. This enables a defect-free bonding interface to be obtained irrespective of a temperature of any heat treatment carried out after a contacting step between the respective thin layers of the two plates.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: November 27, 2012
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Laure Libralesso, Hubert Moriceau, Christophe Morales, François Rieutord, Caroline Ventosa, Thierry Chevolleau
  • Publication number: 20120252188
    Abstract: A plasma processing method for use in device isolation by shallow trench isolation in which an insulating film is embedded in a trench formed in silicon and the insulating film is planarized to form a device isolation film, the method includes a plasma nitriding the silicon of an inner wall surface of the trench by using a plasma before embedding the insulating film in the trench. The plasma nitriding is performed by using a plasma of a processing gas containing a nitrogen-containing gas under conditions in which a processing pressure ranges from 1.3 Pa to 187 Pa and a ratio of a volumetric flow rate of the nitrogen-containing gas to a volumetric flow rate of the entire processing gas ranges from 1% to 80% such that a silicon nitride film is formed on the inner wall surface of the trench to have a thickness of 1 to 10 nm.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 4, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Ryota YONEZAWA, Kazuyoshi Yamazaki, Masaki Sano
  • Publication number: 20120184111
    Abstract: A selective plasma nitriding method includes mounting an object to be processed on a mounting table in a processing chamber of a plasma processing apparatus, the object having a silicon surface and a silicon compound layer exposed; setting a pressure in the processing chamber within the range of about 66.7 Pa to 667 Pa; and generating a nitrogen-containing plasma while applying a bias voltage to the object by supplying to the mounting table a high frequency power with an output of about 0.1 W/cm2 to 1.2 W/cm2 per unit area of the object. The plasma nitriding method further includes selectively nitriding the silicon surface by the nitrogen-containing plasma to form a silicon nitride film.
    Type: Application
    Filed: September 29, 2010
    Publication date: July 19, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Taichi Monden, Hideo Nakamura, Junichi Kitagawa
  • Patent number: 8216889
    Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 10, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Gee-Sung Chae, Mi-Kyung Park
  • Patent number: 8183165
    Abstract: According to the present invention,when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to from an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently,it is possible to improve quality of the oxynitride film, resulting in a reduced leadage current, an improved operating speed, and improved NBTI resistance.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: May 22, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Seiji Matsuyama, Toshio Nakanishi, Shigenori Ozaki, Hikaru Adachi, Koichi Takatsuki, Yoshihiro Sato
  • Patent number: 8173531
    Abstract: A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sunfei Fang, Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang
  • Publication number: 20120108077
    Abstract: Disclosed is a substrate processing apparatus that includes: a substrate supporting member that supports a substrate; a processing chamber capable of housing the substrate supporting member; a rotating mechanism that rotates the substrate supporting member; a carrying mechanism that carries out the substrate supporting member from the processing chamber; a material gas supply system that supplies material gas into the processing chamber; a nitrogen-containing-gas supply system that supplies nitrogen containing gas into the processing chamber; and a controller that controls the material gas supply system, the nitrogen-containing-gas supply system, the carrying mechanism, and the rotating mechanism, after forming a nitride film on the substrate by using the material gas and the nitrogen containing gas, to carry out the substrate supporting member that supports the substrate while being rotated from the processing chamber.
    Type: Application
    Filed: September 14, 2011
    Publication date: May 3, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yukinao KAGA, Tatsuyuki SAITO, Masanori SAKAI, Takashi YOKOGAWA
  • Patent number: 8153538
    Abstract: A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: April 10, 2012
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Larry Wayne Shive, Brian Lawrence Gilmore
  • Publication number: 20120052693
    Abstract: When alternately performing a film deposition step where a silicon-containing gas and O3 gas are alternately supplied to a substrate on a susceptor by rotating the susceptor thereby to forma thin film of the reaction product, and an alteration step where the reaction product is altered by irradiating plasma to the substrate, plasma intensity of the plasma is changed during film deposition. Specifically, the plasma intensity is lower when a thickness of the thin film is small (or at an initial stage of the film deposition—alteration step), and is increased as the thin film becomes thicker (or as the number of the film deposition steps is increased). Alternatively, the plasma intensity is higher when the thin film is relatively thin and then reduced.
    Type: Application
    Filed: August 24, 2011
    Publication date: March 1, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Shigenori OZAKI, Hitoshi Kato, Takeshi Kumagai
  • Patent number: 8101490
    Abstract: A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: January 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanobu Ando, Toru Gotoda, Toru Kita
  • Publication number: 20110318940
    Abstract: A method of manufacturing a semiconductor device includes forming a layer containing a predetermined element on a substrate by supplying a source gas containing the predetermined element into a process vessel and exhausting the source gas from the process vessel to cause a chemical vapor deposition (CVD) reaction. A nitrogen-containing gas is supplied into the process vessel and then exhausted, changing the layer containing the predetermined element into a nitride layer. This process is repeated to form a nitride film on the substrate. The process vessel is purged by supplying an inert gas into the process vessel and exhausting the inert gas from the process vessel between forming the layer containing the predetermined element and changing the layer containing the predetermined element into the nitride layer.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 29, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yosuke OTA, Yoshiro HIROSE, Naonori AKAE, Yushin TAKASAWA
  • Patent number: 8067293
    Abstract: A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage device region by etching part of the first gate oxide layer and also etching part of the field insulating layer to form a stepped field insulating layer, forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region, and forming a gate over the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: November 29, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Cho Eung Park
  • Publication number: 20110256734
    Abstract: Described are methods of making SiN materials on substrates, particularly SiN thin films on semiconductor substrates. Improved SiN films made by the methods are also included.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 20, 2011
    Inventors: Dennis M. Hausmann, Jon Henri, Mandyam Sriram, Bart J. van Schravendijk