Abstract: A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, a resist cover film processing block, a resist cover film removal block, a cleaning/drying processing block, and an interface block. An exposure device is arranged adjacent to the interface block in the substrate processing apparatus. The exposure device subjects a substrate to exposure processing by means of an immersion method. In the edge cleaning unit in the cleaning/drying processing block, a brush abuts against an end of the rotating substrate, so that the edge of the substrate before the exposure processing is cleaned. At this time, the position where the substrate is cleaned is corrected.

Abstract: A method and apparatus for forming an organic semiconductor circuit. A circuit printer is positioned relative to a location on a surface of a composite structure. A number of organic materials is deposited in a pattern on the surface of the composite structure at the location to form the organic semiconductor circuit on the surface of the composite structure at the location.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: An object of the invention is to provide an organic electroluminescence (EL) element formed using a relatively stable new electron injection material in an atmosphere of approximately ordinary pressure. An organic EL element of a preferable embodiment is an organic EL element including a supporting substrate, an anode, a light-emitting layer, an electron injection layer, and a cathode in this order, in which the electron injection layer is formed by applying an ink including an ionic polymer so as to form a film, and the cathode is formed by applying an ink including a material which forms the cathode so as to form a film or transferring a conductive thin film which forms the cathode.

Abstract: A photoresist coating process including a first step and a second step is provided. In the first step, a wafer is accelerated by a first average acceleration. In the second step, the wafer is accelerated by a second average acceleration. The first acceleration and the second acceleration are both larger than zero, and photoresist material is provided to the wafer only in the second step.

Abstract: A thin film deposition apparatus that includes a thin film deposition assembly incorporating: a deposition source that discharges a deposition material; a deposition source nozzle unit that is disposed at a side of the deposition source and includes a plurality of deposition source nozzles arranged in a first direction; a patterning slit sheet that is disposed opposite to the deposition source nozzle unit and includes a plurality of patterning slits arranged in the first direction; and a barrier plate assembly including a plurality of barrier plates that are disposed between the deposition source nozzle unit and the patterning slit sheet in the first direction, and partition a space between the deposition source nozzle unit and the patterning slit sheet into a plurality of sub-deposition spaces, wherein each of the barrier plates is separate from the patterning slit sheet.

Abstract: To provide a photo-curable composition for imprints which can ensure high ratio of mold filling and low defect density during mold releasing, and can provide a resist material with high etching durability. A photo-curable composition for imprints comprising a monofunctional monomer, a polyfunctional monomer and a photo-polymerization initiator, having a viscosity at 25° C. of 15 mPa·s or smaller, an Ohnishi parameter of 3.0 or smaller, and a crosslink density calculated by (Formula 1) of 0.6 mmol/cm3 or larger; Crosslink density={?(Ratio of mixing of polyfunctional monomer (parts by mass)*Number of functional groups of polyfunctional monomer/Molecular weight of polyfunctional monomer)}/Specific gravity.

Abstract: New photoresists are provided that comprise preferably as distinct components: a resin, a photoactive component and a phenolic component Preferred photoresists of the invention are can be useful for ion implant lithography protocols.

Abstract: On a surface of a substrate (3) on which surface a vapor-deposited film is to be formed, a photoresist (13) is formed so as to have an opening in a sealing region including a display region (R1) which sealing region is formed by a sealing resin (11) of a frame shape. Then, luminescent layers (8R, 8G, and 8B) having a striped pattern are formed. Subsequently, the photoresist (13) is removed with the use of an exfoliative solution so as to form the luminescent layers (8R, 8G, and 8B) patterned with high definition.

Abstract: An improved technique achieves a uniform photoresist film on a wafer by controlling the volatility of the solvent in a photoresist solution during the bake process step. Because film formation takes place in the bake rather than the spin steps of the process, the improved technique involves using less viscous and therefore less costly and easier to use resists to cast relatively thick photoresist films. Such control is achieved in an enclosed chamber into which a carrier gas is introduced; the carrier gas mixes with gaseous solvent to create a saturating atmosphere in which the rate of evaporation of solvent decreases. This enables the heating of the wafer without the reduction of solvent in the film so that the photoresist can self-level. When the film has self-leveled, the solvent is then baked off as usual.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: A process for forming a carbon nanotube field effect transistor (CNTFET) device includes site-specific nanoparticle deposition on a CNTFET that has one or more carbon nanotubes, a source electrode, a drain electrode, and a sacrificial electrode on a substrate with an interposed dielectric layer. The process includes control of PMMA removal and electrodeposition in order to select nanoparticle size and deposition location down to singular nanoparticle deposition. The CNTFET device resulting in ultra-sensitivity for various bio-sensing applications, including detection of glucose at hypoglycemic levels.

Abstract: Laser pyrolysis reactor designs and corresponding reactant inlet nozzles are described to provide desirable particle quenching that is particularly suitable for the synthesis of elemental silicon particles. In particular, the nozzles can have a design to encourage nucleation and quenching with inert gas based on a significant flow of inert gas surrounding the reactant precursor flow and with a large inert entrainment flow effectively surrounding the reactant precursor and quench gas flows. Improved silicon nanoparticle inks are described that has silicon nanoparticles without any surface modification with organic compounds. The silicon ink properties can be engineered for particular printing applications, such as inkjet printing, gravure printing or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon nanoparticles.

Abstract: According to one embodiment, an ultraviolet curing curable resin material for pattern transfer is provided. The resin contains isobornyl acrylate, an acrylate having a fluorene skeleton, a polyfunctional acrylate, and a polymerization initiator.

Abstract: A method of preparing a DIABS-based silsesquioxane resin for use in an antireflective hard-mask coating for photolithography is provided. Methods of preparing an antireflective coating from the DIABS-based silsesquioxane resin and using said antireflective coating in photolithography is alternatively presented. The DIABS-based silsequioxane resin has structural units formed from the hydrolysis and condensation of silane monomers including di-t-butoxydiacetoxysilane (DIABS) and at least one selected from the group of R1 SiX3, R2SiX3, R3SiX3, and SiX4 with water; wherein R1 is H or an alkyl group, X is a halide or an alkoxy group, R2 is a chromophore moiety, and R3 is a reactive site or crosslinking site. The DIABS-based silsesqioxane resin is characterized by the presence of at least one tetra-functional SiO4/2 unit formed via the hydrolysis of di-t-butoxydiacetoxysilane (DIABS).

Abstract: Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties.

Abstract: A deposition device includes a deposition source for discharging a deposition material to be deposited on a substrate, an angle control member at least partly in a discharging path of the deposition material for controlling a discharging angle of the deposition material, and an angle control member driver coupled to the angle control member, the angle control member driver for moving the angle control member in a discharging direction of the deposition material to control the discharging angle.

Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.

Abstract: A method for processing a dielectric film on a substrate comprises: depositing a porous dielectric film on a substrate; removing the porogen; stuffing the film with a protective polymeric material; performing at least one intermediate processing step on the stuffed dielectric film; placing the film in a microwave applicator cavity and heating to a first temperature to partially burn out the polymeric material; introducing a controlled amount of a polar solvent into the porosity created by the partial burn out; applying microwave energy to heat the film to a second selected temperature below the boiling point of the solvent to clean away remaining polymeric material; and applying microwave energy to heat the film to a third temperature above the boiling point of the solvent to completely burnout the residues of polymeric material. The interaction of the polar solvent with the microwaves enhances the efficiency of the cleaning process.

Abstract: A method of manufacturing an organic light emitting display device and an organic light emitting display device manufactured using the method, which are suitable for manufacturing large-sized display devices on a mass scale and can be used for high-definition patterning. The method includes consecutively forming organic layers on a substrate on which a plurality of panels are arranged parallel to each other; forming a second electrode on the organic layers, for each of the panels; forming a passivation layer on the second electrode on each of the panels to cover the second electrode; and removing a part of the organic layers that exists between the passivation layer on the second electrode of one of the panels and the passivation layer on the second electrode of an adjacent one of the panels.

Abstract: Provided is a method of forming a pattern, including (a) forming a chemically amplified resist composition into a film, (b) exposing the film to light, (c) developing the exposed film with a developer containing an organic solvent, and (d) rinsing the developed film with a rinse liquid containing an organic solvent, which rinse liquid has a specific gravity larger than that of the developer.

Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.

Abstract: A coating treatment apparatus includes: a rotating and holding part; a nozzle supplying a coating solution; a moving mechanism moving the nozzle; and a control unit that controls the rotating and holding part, the nozzle, and the moving mechanism to supply the coating solution onto a central portion of the substrate and rotate the substrate at a first rotation speed, then move a supply position of the coating solution from a central position toward an eccentric position of the substrate with the substrate being rotated at a second rotation speed lower than the first rotation speed while continuing supply of the coating solution, then stop the supply of the coating solution with the rotation speed of the substrate decreased to a third rotation speed lower than the second rotation speed, and then increase the rotation speed of the substrate to be higher than the third rotation speed.

Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.

Abstract: The present invention describes a deposition method suitable for depositing a coating on a device. The method is particularly suited for depositing a self assembled monolayer (SAM) coating on a micro electro-mechanical structures (MEMS). The method employs carrier gases in order to form a deposition vapour in a process chamber within which the device is located wherein the deposition vapour comprises controlled amounts of a vapour precursor material and a vapour reactant material. Employing the described technique avoids the problematic effects of particulate contamination of the device even when the volumetric ratio of the reactant material to the precursor material is significantly higher than those ratios previously employed in the art. The vapour precursor material can be of a type that provides the MEMS with an anti-stiction coating with the associated vapour reactant material comprising water.

Abstract: In various embodiments, the present invention relates to production of encapsulated nanoparticles by dispersing said nanoparticles and an encapsulating medium in a common solvent to form a first solution system and applying a stimulus to said first solution system to induce simultaneous aggregation of the nanoparticles and the encapsulating medium.

Abstract: A substrate processing apparatus includes: a reaction chamber configured to process a substrate; a vaporizer including a vaporization container into which a processing liquid including hydrogen peroxide or hydrogen peroxide and water is supplied, a processing liquid supply unit configured to supply the processing liquid to the vaporization container, and a heating unit configured to heat the vaporization container; a gas supply unit configured to supply a processing gas generated by the vaporizer into the reaction chamber; an exhaust unit configured to exhaust an atmosphere in the reaction chamber; and a control unit configured to control the heating unit and the processing liquid supply unit such that the processing liquid supply unit supplies the processing liquid to the vaporization container while the heating unit heats the vaporization container.

Abstract: Compositions for directed self-assembly (DSA) patterning techniques are provided. Methods for directed self-assembly are also provided in which a DSA composition comprising a block copolymer is applied to a substrate and then self-assembled to form the desired pattern. The block copolymer includes at least two blocks of differing etch rates, so that one block (e.g., polymethylmethacrylate) is selectively removed during etching. Because the slower etching block (e.g., polystyrene) is modified with an additive to further slow the etch rate of that block, more of the slow etching block remains behind to fully transfer the pattern to underlying layers.

Abstract: A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. The metal layer and the surface passivation layer are dipped into a modifier, and the modifier is selectively absorbed and attached to the surface passivation layer, so as to form a covering layer. The covering layer has a plurality of nanoparticles and covers the surface passivation layer.

Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.

Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.

Abstract: A method for performing silicidation of a gate electrode is provided that includes forming both a first transistor with a first gate electrode covered by a cap layer and a semiconductor device on the same semiconductor substrate, forming an organic planarization layer (OPL) on the first transistor and the semiconductor device, back etching the OPL such that an upper surface of the OPL is positioned at a level that is below a level of an upper surface of the cap layer, forming a mask layer covering the semiconductor device without covering the first transistor, removing the cap layer while the back-etched OPL and the mask layer are present, and performing silicidation of the first gate electrode.

Abstract: A liquid processing method forms a coating film by supplying and pouring a coating solution from a coating solution nozzle onto a surface of a substrate held substantially horizontally by a substrate holder. In the liquid processing method, a process for photographing a leading end portion of a coating solution nozzle is provided. When performing a process for anti-drying of the coating solution for a long period of time in advance, a position of the coating solution and a position of an anti-drying liquid are set by using a soft scale displayed on a screen where the photographed image is displayed. Therefore, a dispense control is performed based on a set value without depending on the naked eyes and a control for suppressing the drying of the coating solution in the leading end portion of the coating solution nozzle is performed.

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract: A thin film deposition apparatus that is suitable for manufacturing large-sized display devices on a mass scale and that can be used for high-definition patterning, a method of manufacturing an organic light-emitting display device by using the thin film deposition apparatus, and an organic light-emitting display device manufactured by using the method.

Abstract: A method includes forming a polymer layer over a passivation layer, wherein the passivation layer further comprises a portion over a metal pad. The polymer layer is patterned to form an opening in the polymer layer, wherein exposed surfaces of the polymer layer have a first roughness. A surface treatment is performed to increase a roughness of the polymer layer to a second roughness greater than the first roughness. A metallic feature is formed over the exposed surface of the polymer layer.

Abstract: Embodiments described herein generally relate to an apparatus and methods for reducing the deposition of polymers in a semiconductor processing chamber. A heater jacket and heat sources are provided and may be configured to maintain a uniform temperature profile of the processing chamber. A method of maintaining a uniform temperature profile of a dielectric ceiling of the processing chamber is also provided.

Abstract: An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.

Abstract: According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on the quartz plate, and impurities are contained in a portion between the concave sections in the quartz plate.

Abstract: Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.

Abstract: A manufacturing device of an organic light emitting diode display, includes a stage including a temperature controller which heats or cools a region of a substrate on the stage; a discharging unit including a nozzle which provides light-emitting material to the region of the substrate; a beam irradiation unit which irradiates beams to the substrate; and a driving unit which is configured to move the stage or the discharging unit.

Abstract: A method of manufacturing a tungsten plug is described for producing semiconductor integrated circuits. The method protects the dielectric layer from getting damaged and avoids impact from CMP technology on the electrical RC properties of the semiconductor devices by using a high hardness amorphous carbon layer as an advance pattern film (APF) or barrier layer allowing grinding without altering the dielectric layer, to thereby improve the yield of products.

Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.

Abstract: A method of fabricating a memory device includes providing multiple coatings of nanodots on a tunnel dielectric layer to form a floating gate layer having a high nanodot density. The memory device may have a nanodot-containing floating gate layer with a density greater than 4×1012 dots/cm2. Further methods include forming an oxidation barrier layer, such as a silicon nitride shell, over a surface of the nanodots, and depositing a dielectric material over the nanodots to form a floating gate layer.

Abstract: A silicon polymer material, which has a silicon polymer backbone with chromophore groups attached directly to at least a part of the silicon atoms, the polymer further exhibiting carbosilane bonds. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two different chromophores the refractive index and the absorption co-efficient can be efficiently tuned. By varying the proportion of carbosilane bonds, and a desired Si-content of the anti-reflective coating composition can be obtained.

Abstract: The invention provides a material for forming a passivation film for a semiconductor substrate. The material includes a polymer compound having an anionic group or a cationic group.

Abstract: New photoresists are provided that comprise preferably as distinct components: a resin, a photoactive component and a phenolic component Preferred photoresists of the invention are can be useful for ion implant lithography protocols.

Abstract: A pressure sensor having a structure, which includes a supporting body, a circuit arrangement and at least one circuit support. The circuit arrangement includes circuit components, amongst which detection means for generating electrical signals representing a quantity to be detected. The at least one circuit support is connected to the supporting body and has a surface, formed on which is a plurality of said circuit components, amongst which electrically conductive paths, where the circuit support is laminated on the first face of the supporting body.

Abstract: A resist underlayer film forming composition for EUV lithography, comprising: as a silane, a hydrolyzable silane, a hydrolyzate of the hydrolyzable silane, a hydrolysis condensate of the hydrolyzable silane, or a mixture of any of the hydrolyzable silane, the hydrolyzate, and the hydrolysis condensate, wherein the hydrolyzable silane includes a combination of tetramethoxysilane, an alkyltrimethoxysilane, and an aryltrialkoxysilane, and the aryltrialkoxysilane is represented by formula (1): (R2)n2—R1—(CH2)n1—Si(X)3??Formula (1) In formula (1), R1 is an aromatic ring consisting of a benzene ring or a naphthalene ring or a ring including an isocyanuric acid structure, R2 is a substituent replacing a hydrogen atom on the aromatic ring and is a halogen atom or a C1-10 alkoxy group, and X is a C1-10 alkoxy group, a C2-10 acyloxy group, or a halogen group.

Abstract: An arrangement (1) for holding a substrate (10) in a material deposition apparatus, which substrate (10) has a deposition side (10a) upon which material (M) is to be deposited, and which arrangement (1) comprises: a shadow mask (20) comprising a number of deposition openings (Di); a support structure (30) comprising a number of surround openings (Si); and a support structure holding means (6) for holding the support mask (30) and/or a substrate holding means (5) for holding the substrate (10), such that the support structure (30) is on the same side as the deposition side (10a) of the substrate (10), and the shadow mask (20) is positioned between the substrate (10) and the support structure (30) such that at least one deposition opening (Di) of the shadow mask (10) lies within a corresponding surround opening (Si) of the support structure (30).