Insulative Material Having Impurity (e.g., For Altering Physical Characteristics, Etc.) Patents (Class 438/783)
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Patent number: 7510982Abstract: Porous dielectric layers are produced by embedding and removing nanoparticles in composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: June 6, 2005Date of Patent: March 31, 2009Assignee: Novellus Systems, Inc.Inventors: Nerissa S. Draeger, Gary William Gray
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Patent number: 7507653Abstract: A method of fabricating a dielectric piece which includes metal compound dots is provided. A stacked layer formed over the substrate includes a metal compound layer and an energy barrier layer. A process such as an oxidization annealing process is then performed so that the metal compound layer is transformed into a great number of crystalline metal compound dots distributed in the energy barrier layer.Type: GrantFiled: August 24, 2006Date of Patent: March 24, 2009Assignee: Industrial Technology Research InstituteInventors: Cha-Hsin Lin, Pei-Jer Tzeng, Maikap Siddheswar
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Patent number: 7501354Abstract: Nano-porous low dielectric constant films are deposited utilizing materials having reactive by-products readily removed from a processing chamber by plasma cleaning. In accordance with one embodiment, an oxidizable silicon containing compound is reacted with an oxidizable non-silicon component having thermally labile groups, in a reactive oxygen ambient and in the presence of a plasma. The deposited silicon oxide film is annealed to form dispersed microscopic voids or pores that remain in the nano-porous silicon. Oxidizable non-silicon components with thermally labile groups that leave by-products readily removed from the chamber, include but are not limited to, limonene, carene, cymene, fenchone, vinyl acetate, methyl methacrylate, ethyl vinyl ether, tetrahydrofuran, furan, 2,5 Norbornadiene, cyclopentene, cyclopentene oxide, methyl cyclopentene, 2-cyclopentene-1-one, and 1-butene.Type: GrantFiled: September 9, 2005Date of Patent: March 10, 2009Assignee: Applied Materials, Inc.Inventors: Dustin W. Ho, Derek R. Witty, Helen R. Armer, Hichem M'Saad
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Patent number: 7494939Abstract: Atomic layer deposited lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices. In an embodiment, a lanthanum aluminum oxide dielectric layer is formed by depositing aluminum and lanthanum by atomic layer deposition onto a substrate surface in which precursors to deposit the lanthanum include a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor.Type: GrantFiled: August 31, 2004Date of Patent: February 24, 2009Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 7491655Abstract: A semiconductor device using a TFT structure with high reliability is realized. As an insulating film used for the TFT, for example, a gate insulating film, a protecting film, an under film, an interlayer insulating film, or the like, a silicon nitride oxide film (SiNXBYOZ) containing boron is formed by a sputtering method. As a result, the internal stress of this film becomes ?5×1010 dyn/cm2 to 5×1010 dyn/cm2, preferably ?1010 dyn/cm2 to 1010 dyn/cm2, and the film has high thermal conductivity, so that it typically becomes possible to prevent deterioration due to heat generated at the time of an on operation of the TFT.Type: GrantFiled: August 31, 2004Date of Patent: February 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Publication number: 20090017640Abstract: Methods of forming boron-containing films are provided. The methods include introducing a boron-containing precursor into a chamber and depositing a network comprising boron-boron bonds on a substrate by thermal decomposition or a plasma process. The network may be post-treated to remove hydrogen from the network and increase the stress of the resulting boron-containing film. The boron-containing films have a stress between about ?10 GPa and 10 GPa and may be used as boron source layers or as strain-inducing layers.Type: ApplicationFiled: July 11, 2008Publication date: January 15, 2009Inventors: Jeong-Uk Huh, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty, Hichem M'Saad
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Patent number: 7476609Abstract: A method for forming, by dry etch, an opening of a given shape in a silica glass layer, the layer having a doping profile similar to the shape and the etch plasma being a non-carbonated fluorinated plasma causing a non-directional etching.Type: GrantFiled: October 27, 2006Date of Patent: January 13, 2009Assignee: STMicroelectronics S.A.Inventor: Fabienne Judong
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Patent number: 7470606Abstract: The invention includes masking methods. In one implementation, a masking material which includes boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material includes at least about 0.5 atomic percent boron. The masking material is substantially anisotropically etched effective to form an anisotropically etched sidewall spacer which includes the boron doped amorphous carbon on a sidewall of the feature. The substrate is then processed proximate the spacer while using the boron doped amorphous carbon-including spacer as a mask. After processing the substrate proximate the spacer, the boron doped amorphous carbon-including spacer is etched from the substrate. Other implementations and aspects are contemplated.Type: GrantFiled: July 31, 2006Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventors: Zhiping Yin, Gurtej S. Sandhu
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Publication number: 20080290473Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.Type: ApplicationFiled: July 31, 2008Publication date: November 27, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Hiroomi Tsutae
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Patent number: 7439194Abstract: A dielectric film containing lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric film is formed by evaporation of Ti, a lanthanide, and oxidation of the evaporated Ti/lanthanide film using an oxygen plasma.Type: GrantFiled: January 7, 2005Date of Patent: October 21, 2008Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20080254644Abstract: A disclosed substrate processing method in a single wafer substrate processing device including a first process position for introducing nitrogen atoms to a high-dielectric film and a second process position for performing heat treatment on the high-dielectric film includes: successively conveying plural substrates to be processed to the first process position and the second process position one by one; and successively performing the introduction of nitrogen atoms and the heat treatment on the high-dielectric film on the substrates to be processed, wherein the treatment on the substrate to be processed is started within 30 seconds at the second process position after the process at the first position.Type: ApplicationFiled: April 25, 2007Publication date: October 16, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Miki Aruga, Kazuyoshi Yamazaki, Shintaro Aoyama, Kouji Shimomura
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Patent number: 7432126Abstract: A substrate comprises at least one semiconductor layer applied to a substrate material, whereby the semiconductor layer comprises an inert matrix material, in which an inorganic semiconductor material is embedded in particle form.Type: GrantFiled: November 30, 2001Date of Patent: October 7, 2008Assignee: Infineon Technologies AGInventor: Günter Schmid
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Patent number: 7429541Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.Type: GrantFiled: August 31, 2005Date of Patent: September 30, 2008Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Chris W. Hill
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Patent number: 7419903Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.Type: GrantFiled: April 13, 2005Date of Patent: September 2, 2008Assignee: ASM International N.V.Inventors: Suvi P. Haukka, Ivo Raaijmakers, Wei Min Li, Juhana Kostamo, Hessel Sprey
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Patent number: 7419919Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.Type: GrantFiled: September 9, 2005Date of Patent: September 2, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Hiroomi Tsutae
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Patent number: 7419920Abstract: A metal oxide thin film may be obtained by providing a source gas and an oxidizer gas. The source gas may include a hydrolyzable metallic compound. The oxidizer gas may include a hydrate of a metal salt. The metal oxide thin film may be obtained by alternately feeding the source gas and the oxidizer gas into a reaction chamber in which a substrate is placed.Type: GrantFiled: December 12, 2005Date of Patent: September 2, 2008Assignees: HORIBA, Ltd., Rohm Co., Ltd., Renesas Technology Corp.Inventors: Koji Tominaga, Kunihiko Iwamoto, Toshihide Nabatame
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Publication number: 20080203487Abstract: By providing a highly stressed interlayer dielectric material, the performance of at least one type of transistor may be increased due to an enhanced strain-inducing mechanism. For instance, by providing a highly compressive silicon dioxide of approximately 400 Mega Pascal and more as an interlayer dielectric material, the drive current of the P-channel transistors may be increased by 2% and more while not unduly affecting the performance of the N-channel transistors.Type: ApplicationFiled: October 17, 2007Publication date: August 28, 2008Inventors: Joerg Hohage, Michael Finken, Christof Streck, Ralf Richter
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Patent number: 7410913Abstract: Provided are methods for manufacturing silicon rich oxide (SRO) layers useful in the fabrication of semiconductor devices, for example, non-volatile memory devices, and methods for fabricating semiconductor devices incorporating such SRO layers. The methods include absorbing a first silicon source gas onto the substrate, oxidizing the first absorbed layer to form a silicon oxide layer, absorbing a second silicon source gas onto the substrate and reducing the second absorbed layer to form a silicon layer. The combination of the silicon oxide layer(s) and the silicon layer(s) comprise, in turn, a composite SRO layer. These manufacturing methods facilitate control of the oxygen concentration in the SRO, the relative thicknesses of the silicon oxide and silicon layers, and provides improved step coverage, thus allowing the manufacturing of high quality semiconductor devices.Type: GrantFiled: September 12, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyun Lee, Sang-Bong Bang
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Publication number: 20080188091Abstract: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.Type: ApplicationFiled: March 6, 2008Publication date: August 7, 2008Inventors: SHAO-TA HSU, Teng-Chun Tsai, Neng-Kuo Chen, Hsiu-Lien Liao, Cheng-Han Wu, Wen-Han Hung
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Patent number: 7402533Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions, such as a memory transistor array, and widely spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely spaced regions and a second thickness over the widely spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely spaced regions.Type: GrantFiled: August 31, 2006Date of Patent: July 22, 2008Assignee: Micron Technology, Inc.Inventor: Christopher W Hill
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Patent number: 7402532Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: GrantFiled: August 4, 2006Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stefanie R. Chiras, Timothy Dalton, James J. Demarest, Derren N. Dunn, Chester T. Dziobkowski, Philip L. Flaitz, Michael W. Lane, James R. Lloyd, Darryl D. Restaino, Thomas M. Shaw, Yun-Yu Wang, Chih-Chao Yang
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Patent number: 7371698Abstract: A method of forming a film pattern includes the steps of forming a bank for partitioning a pattern forming area including a first pattern forming area and a second pattern forming area having an intersection with the first pattern forming area and divided in the intersection into sub-areas, disposing a functional liquid to the first pattern forming area to form a first film pattern, and disposing a functional liquid to the sub-areas to form second film patterns, executing a lyophobic process on the entire surface of a substrate including the first film pattern, the second film patterns, and the bank, weakening the lyophobicity on the substrate while selectively maintaining the lyophobicity on predetermined positions of the respective second film patterns formed in a divided condition after executing the lyophobic process, stacking a cap layer on the first film pattern and the second film patterns after weakening the lyophobicity, removing the lyophobicity in the predetermined positions of the respective seconType: GrantFiled: May 23, 2006Date of Patent: May 13, 2008Assignee: Seiko Epson CorporationInventors: Katsuyuki Moriya, Toshimitsu Hirai
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Patent number: 7368401Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.Type: GrantFiled: May 13, 2004Date of Patent: May 6, 2008Assignee: Texas Instruments IncorporatedInventor: Robert H. Havemann
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Patent number: 7365027Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.Type: GrantFiled: March 29, 2005Date of Patent: April 29, 2008Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20080093639Abstract: A method for forming a gate insulating layer of a Metal Oxide Semiconductor (MOS) transistor includes forming an oxide layer on a semiconductor substrate, implanting plasma nitrogen ions into the oxide layer, and performing heat treatment on the nitrogen ion-implanted oxide layer to eliminate damage to a surface of the oxide layer. The nitrogen ions are implanted according to a Decoupled Plasma Nitridation (DPN) method. The nitrogen ions are implanted under conditions including RF power of approximately 200-800 W, a duty cycle of approximately 20-100%, a pressure of approximately 10-30 mtorr, and a process time of approximately 30-100 seconds.Type: ApplicationFiled: October 10, 2007Publication date: April 24, 2008Inventor: Dae-Young Kim
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Patent number: 7361611Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.Type: GrantFiled: February 8, 2006Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Judson Holt, Kevin K. Chan, Sadanand V. Deshpande, Rangarajan Jagannathan
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Patent number: 7342290Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.Type: GrantFiled: November 4, 2004Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James R. Elliott, Kenneth R. Gault, Mousa H. Ishaq, Steven M. Shank, Mary A. St. Lawrence
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Patent number: 7335610Abstract: Semiconductor structures and methods of fabricating semiconductor structures are disclosed. The method comprises the steps of: providing an initial semiconductor structure; forming a non-silicon layer overlying the initial semiconductor structure, the non-silicon layer having an extinction coefficient greater than zero at wavelengths below about 300 nanometers; and performing a plasma-based process to form a layer overlying the non-silicon layer, the non-silicon layer preventing the ultraviolet radiation generated during the plasma-based process from damaging the initial semiconductor structure.Type: GrantFiled: April 28, 2005Date of Patent: February 26, 2008Assignee: Macronix International Co., Ltd.Inventors: Tuung Luoh, Ling Wuu Yang, Kuang Chao Chen
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Patent number: 7335598Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent.Type: GrantFiled: April 19, 2005Date of Patent: February 26, 2008Assignee: United Microelectronics Corp.Inventors: Kun-Lin Wu, Meng-Jin Tsai
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Patent number: 7335609Abstract: A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate. The method includes flowing a silicon-containing precursor into a process chamber housing the substrate, flowing an oxidizing gas into the chamber, and providing a hydroxyl-containing precursor in the process chamber. The method also includes reacting the silicon-containing precursor, oxidizing gas and hydroxyl-containing precursor to form the dielectric material in the trench. The ratio of the silicon-containing precursor to the oxidizing gas flowed into the chamber is increased over time to alter a rate of deposition of the dielectric material.Type: GrantFiled: August 26, 2005Date of Patent: February 26, 2008Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Shan Wong, Xinyun Xia, Vikash Banthia, Won B. Bang, Yen-Kun V. Wang
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Patent number: 7332446Abstract: According to the invention, the thin film having the thickness controlled desirably can be easily formed using common semiconductor processes. Provided is a coating liquid for forming the porous film having an excellent dielectric property and mechanical property. Specifically, the coating liquid for forming a porous film comprises the condensation product obtained by condensation of one or more silicate compounds represented by the formula (X2O) i(SiO2)j(H2O)k and one more organosilate compounds represented by the formula (X2O)a(RSiO1.5)b(H2O)c. Thus, the porous insulating film having sufficient mechanical strength and dielectric properties for use in the semiconductor manufacturing process can be manufactured.Type: GrantFiled: March 25, 2004Date of Patent: February 19, 2008Assignees: Shin-Etsu Chemical Co., Ltd., Matsushita Electric Industrial Co., Ltd.Inventors: Tsutomu Ogihara, Fujio Yagihashi, Yoshitaka Hamada, Takeshi Asano, Motoaki Iwabuchi, Hideo Nakagawa, Masaru Sasago
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Patent number: 7320944Abstract: A method of forming a phosphosilicate glass, includes flowing a pre-deposition gas comprising an inert gas into a deposition chamber containing a substrate, where the temperature of the substrate is at a pre-deposition temperature of at least 400° C; continuously increasing the temperature of gas in the chamber to a deposition temperature and simultaneously continuously increasing a flow rate of phosphine and silane until a phosphine:silane deposition ratio is achieved; and depositing the phosphosilicate glass on the substrate at the deposition temperature and at the phosphine:silane deposition ratio.Type: GrantFiled: June 27, 2005Date of Patent: January 22, 2008Assignee: Cypress Semiconductor CorporationInventors: Michal Efrati Fastow, Ryan Holler
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Patent number: 7312165Abstract: Methods of film deposition using metals and metal oxides. A thin film of germanium oxide and an oxide of a non-germanium metal is deposited by ALD by alternating deposition of first and second precursor compounds, wherein the first precursor compound includes a metal other than germanium, and the second precursor compound includes germanium.Type: GrantFiled: May 5, 2005Date of Patent: December 25, 2007Inventors: Gregory M. Jursich, Ronald S. Inman
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Patent number: 7309650Abstract: A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.Type: GrantFiled: February 24, 2005Date of Patent: December 18, 2007Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Connie Pin-Chin Wang, Lu You, Zoran Krivokapic, Paul Raymond Besser, Suzette Keefe Pangrle
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Patent number: 7294556Abstract: This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.Type: GrantFiled: January 7, 2005Date of Patent: November 13, 2007Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Publication number: 20070259534Abstract: A method is provided for in-situ formation of a thin oxidized AlN film on a substrate. The method includes providing the substrate in a process chamber, depositing an AlN film on the substrate, and post-treating the AlN film with exposure to a nitrogen and oxygen-containing gas. The post-treating increases the dielectric constant of the AlN film with substantially no increase in the AlN film thickness. The method can also include pre-treating the substrate prior to AlN deposition, post-annealing the AlN film before or after the post-treatment, or both.Type: ApplicationFiled: May 7, 2007Publication date: November 8, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Kimberly G. Reid, Anthony Dip
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Patent number: 7288491Abstract: One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning film precursor gas into the chamber and generating a plasma within the chamber, performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma, and then removing the workpiece from the chamber and removing the seasoning film from the chamber interior surfaces.Type: GrantFiled: January 28, 2005Date of Patent: October 30, 2007Assignee: Applied Materials, Inc.Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
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Patent number: 7282458Abstract: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.Type: GrantFiled: November 7, 2005Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Stephen M. Gates, Christos D. Dimitrakopoulos, Alfred Grill, Son Van Nguyen
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Patent number: 7259111Abstract: A method of depositing a organosilicate dielectric layer exhibiting high adhesion strength to an underlying substrate disposed within a single processing chamber without plasma arcing. The method includes positioning a substrate within a processing chamber having a powered electrode, flowing an interface gas mixture into the processing chamber, the interface gas mixture comprising one or more organosilicon compounds and one or more oxidizing gases, depositing a silicon oxide layer on the substrate by varying process conditions, wherein DC bias of the powered electrode varies less than 60 volts.Type: GrantFiled: June 1, 2005Date of Patent: August 21, 2007Assignee: Applied Materials, Inc.Inventors: Deenesh Padhi, Ganesh Balasubramanian, Annamalai Lakshmanan, Zhenjiang Cui, Juan Carlos Rocha-Alvarez, Bok Hoen Kim, Hichem M'Saad, Steven Reiter, Francimar Schmitt
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Publication number: 20070161258Abstract: In an embodiment, a method of fabricating a semiconductor device having a hydrogen source layer includes forming an interlayer insulating layer on a semiconductor substrate. A hydrogen source layer is formed on the substrate having the interlayer insulating layer. A thermal annealing process is performed on the substrate having the hydrogen source layer such that hydrogen inside the hydrogen source layer is diffused to a surface of the semiconductor substrate. A conductive pattern is formed on the substrate having the thermally-treated hydrogen source layer. The conductive pattern may be a metal interconnection.Type: ApplicationFiled: October 25, 2006Publication date: July 12, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Heum NAM, Chear-Yeon MUN, Bo-Sung KIM
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Patent number: 7241705Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.Type: GrantFiled: September 1, 2004Date of Patent: July 10, 2007Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Gurtej S. Sandhu, H. Montgomery Manning
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Patent number: 7241706Abstract: Embodiments of the invention provide a relatively hydrophilic layer in a low k dielectric layer. The hydrophilic layer may be formed by exposing the dielectric layer to light having enough energy to break Si—C and C—C bonds but not enough to break Si—O bonds.Type: GrantFiled: September 16, 2004Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Steven W. Johnston, Nate Baxter
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Patent number: 7235501Abstract: Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is formed as a structure of one or more monolayers, and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.Type: GrantFiled: December 13, 2004Date of Patent: June 26, 2007Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 7220684Abstract: There is included an inorganic insulating film having a porous structure including a cylindrical vacancy oriented in parallel with the surface of a substrate subjected to a hydrophilic treatment or a hydrophobic treatment.Type: GrantFiled: June 28, 2002Date of Patent: May 22, 2007Assignee: ROHM Co., Ltd.Inventors: Norikazu Nishiyama, Korekazu Ueyama, Yoshiaki Oku
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Patent number: 7183183Abstract: A method for forming a mechanically strengthened feature in a low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. A sidewall of the feature in the low-k dielectric film is then treated in order to increase the film's mechanical strength. Treatment of the sidewall of the feature in the low-k dielectric film comprises forming a hardened layer by subjecting the low-k dielectric film to low energy, high flux ion implantation. Process parameters of the ion implantation are selected such that the implantation process does not cause a substantial change in the dielectric constant of the low-k dielectric film.Type: GrantFiled: July 23, 2004Date of Patent: February 27, 2007Assignee: Tokyo Electron LimitedInventors: Kenneth Duerksen, David C. Wang, Robert J. Soave
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Patent number: 7176144Abstract: Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to moisture or ambient conditions.Type: GrantFiled: February 23, 2004Date of Patent: February 13, 2007Assignee: Novellus Systems, Inc.Inventors: Feng Wang, Michelle T. Schulberg, Jianing Sun, Raashina Humayun, Patrick A. Van Cleemput
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Patent number: 7172980Abstract: A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.Type: GrantFiled: February 18, 2004Date of Patent: February 6, 2007Assignees: STMicroelectronics SA, Koninklijke Philips Electronics N.V.Inventors: Joaquin Torres, Vincent Arnal, Laurent Gosset
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Patent number: 7166505Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.Type: GrantFiled: September 16, 2004Date of Patent: January 23, 2007Assignee: Intel CorporationInventors: Robert Chau, Reza Arghavani, Mark Doczy
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Patent number: 7157387Abstract: One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.Type: GrantFiled: August 31, 2004Date of Patent: January 2, 2007Assignee: Micron Technologies, Inc.Inventors: Arup Bhattacharyya, Paul A. Farrar
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Patent number: RE40507Abstract: A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization techniques to a thickness that allows for adequate mobile-ion gettering.Type: GrantFiled: June 25, 2003Date of Patent: September 16, 2008Assignee: Atmel CorporationInventors: Amit S. Kelkar, Michael D. Whiteman