Silicon Nitride Formation Patents (Class 438/791)
  • Patent number: 10388511
    Abstract: There is provided a method of forming a silicon nitride film including: arranging substrates in a process vessel; and forming a silicon nitride film on the substrates in a batch by repeating a cycle including: a first purge step of purging the process vessel while heating the process vessel and making an interior of the process vessel be in a predetermined depressurized state; a film-forming raw material gas adsorbing step of adsorbing a chlorine-containing silicon compound to the substrates by supplying a film-forming raw material gas composed of the chlorine-containing silicon compound into the process vessel; a second purge step of purging the process vessel; and a nitriding step of nitriding the substrates by supplying a nitriding gas into the process vessel, and wherein in each of the cycle, a hydrogen radical purge step is performed between the film-forming raw material gas adsorbing step and the nitriding step.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 20, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yamato Tonegawa
  • Patent number: 10269989
    Abstract: A hydrogen sensor can include a substrate, an Ohmic metal disposed on the substrate, a nitride layer disposed on the substrate and having a first window exposing the substrate, a Schottky metal placed in the first window and disposed on the substrate, a final metal disposed on the nitride layer and the Schottky metal and having a second window exposing the Schottky metal, and a polymethyl-methacrylate (PMMA) layer encapsulating the second window. The PMMA layer can fill the second window and be in contact with the Schottky metal.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 23, 2019
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Fan Ren, Stephen J. Pearton, Soohwan Jang, Sunwoo Jung
  • Patent number: 10262858
    Abstract: Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiNx monolayer at temperatures below about 300° C.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 16, 2019
    Assignees: Applied Materials, Inc., The Regents of the University of California
    Inventors: Naomi Yoshida, Lin Dong, Andrew Kummel, Jessica Kachian, Mary Edmonds, Steve Wolf
  • Patent number: 10211047
    Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, Deepika Priyadarshini
  • Patent number: 9934963
    Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, Deepika Priyadarshini
  • Patent number: 9805949
    Abstract: A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jean Fompeyrine, Edward W. Kiewra, Steven J. Koester, Devendra K. Sadana, David J. Webb
  • Patent number: 9735359
    Abstract: A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: August 15, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Patent number: 9431235
    Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, Deepika Priyadarshini
  • Patent number: 9373498
    Abstract: A method of operating vertical heat treatment apparatus includes: cleaning interior of vertical reaction chamber by supplying cleaning gas; pre-coating the interior of the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas; eliminating charges by loading substrate holding unit holding a dummy semiconductor substrate or a conductive substrate into the reaction chamber and supplying the second gas while generating plasma from the second gas without supplying the first gas; loading the substrate holding unit holding a plurality of product semiconductor substrates into the reaction chamber; and forming thin film in the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: June 21, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keisuke Suzuki, Yutaka Motoyama
  • Patent number: 9349876
    Abstract: A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Yuichiro Mitani, Masayasu Miyata, Yasushi Nakasaki, Koichi Kato, Daisuke Matsushita, Akira Takashima, Misako Morota
  • Patent number: 9337022
    Abstract: A method of creating a virtual relaxed substrate includes providing a bulk semiconductor substrate, and creating a layer of strained semiconductor material on the substrate, a non-zero lattice mismatch of less than about 2% being present between the substrate and the layer of strained semiconductor material, and the layer of strained semiconductor material having a thickness of from about 50 nm to about 150 nm. The method further includes etching through the layer of strained semiconductor material and into the substrate to create shaped pillars separated by slits and sized to achieve edge effect relaxation throughout each shaped pillar, merging a top portion of the pillars with single crystal growth of epitaxial material to create a continuous surface while substantially maintaining the slits, and creating a virtual relaxed substrate by creating a layer of epitaxial composite semiconductor material over the continuous surface.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 10, 2016
    Assignees: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Bruce Doris
  • Patent number: 9331168
    Abstract: Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high k dielectric layer disposed over the substrate, and a gate layer over the high k dielectric layer. The high k dielectric layer is partially crystallized and comprising an average thickness of from about 10 ? to about 30 ?. Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (i) forming a high k dielectric layer with a thickness of from about 10 ? to about 30 ? over a substrate, (ii) forming a gate layer over the dielectric layer, and (iii) transforming at least a portion of the dielectric layer from a first phase to a second phase by microwave irradiation.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 3, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Su-Horng Lin, Lin-Jung Wu
  • Patent number: 9269568
    Abstract: Provided are a deposition apparatus and a method of manufacturing a semiconductor device. In the method, a reaction chamber provided with a gaseous source supply unit and a liquid source supply unit is prepared, and an etch stop layer is formed on a substrate by using a gaseous source. Then, an interlayer insulation layer is formed on the etch stop layer by using a vaporized liquid source and a vaporized dopant source. In this way, the etch stop layer and the interlayer insulation layer are formed in-situ in the same reaction chamber.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 23, 2016
    Assignee: WONIK IPS CO., LTD
    Inventors: Young Soo Kwon, Kyoung Pil Na, Seok Jong Hyun
  • Patent number: 9177783
    Abstract: Provided are silacyclopropane-based compounds and methods of making the same. Also provided are methods of using said compounds in film deposition processes to deposit films comprising silicon. Certain methods comprise exposing a substrate surface to a silacyclopropane-based precursor and a co-reagent in various combinations.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: November 3, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Mark Saly, David Thompson
  • Patent number: 9163325
    Abstract: A crystal growth apparatus comprises a reaction vessel holding a melt mixture containing an alkali metal and a group III metal, a gas supplying apparatus supplying a nitrogen source gas to a vessel space exposed to the melt mixture inside the reaction vessel, a heating unit heating the melt mixture to a crystal growth temperature, and a support unit supporting a seed crystal of a group III nitride crystal inside the melt mixture.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 20, 2015
    Assignee: RICOH COMPANY, LTD.
    Inventors: Seiji Sarayama, Hirokazu Iwata, Akihiro Fuse
  • Patent number: 9123707
    Abstract: Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF4, SiCl4, Si2Cl6, and forming a hydrogen free silicon containing layer on the substrate in the presence of the gas mixture.
    Type: Grant
    Filed: August 20, 2011
    Date of Patent: September 1, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Soo Young Choi
  • Patent number: 9029171
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9023737
    Abstract: A method for forming a conformal, homogeneous dielectric film includes: forming a conformal dielectric film in trenches and/or holes of a substrate by cyclic deposition using a gas containing a silicon and a carbon, nitrogen, halogen, hydrogen, and/or oxygen, in the absence of a porogen gas; and heat-treating the conformal dielectric film and continuing the heat-treatment beyond a point where substantially all unwanted carbons are removed from the film and further continuing the heat-treatment to render substantially homogeneous film properties of a portion of the film deposited on side walls of the trenches and/or holes and a portion of the film deposited on top and bottom surfaces of the trenches and/or holes.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: May 5, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Julien Beynet, Ivo Raaijmakers, Atsuki Fukazawa
  • Patent number: 9018093
    Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 28, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Naoto Tsuji, Fumitaka Shoji
  • Patent number: 9018104
    Abstract: There is provided a method for manufacturing a semiconductor device, including forming an insulating film having a prescribed composition and a prescribed film thickness on a substrate by alternately performing the following steps prescribed number of times: supplying one of the sources of a chlorosilane-based source and an aminosilane-based source to a substrate in a processing chamber, and thereafter supplying the other source, to form a first layer containing silicon, nitrogen, and carbon on the substrate; and supplying a reactive gas different from each of the sources, to the substrate in the processing chamber, to modify the first layer and form a second layer.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: April 28, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Kenji Kanayama, Norikazu Mizuno, Yushin Takasawa, Yosuke Ota
  • Patent number: 9018109
    Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
  • Patent number: 9018106
    Abstract: A method of forming a material layer on a substrate is provided. The method is based on a combination of an overheating before deposition and a cooling of the reaction chamber during a second deposition stage. The second deposition stage follows a first deposition stage preferably carried out at a predetermined temperature. This combination makes it possible to compensate for the reactant gas depletion across wafer throughout the whole deposition process. The method can be conveniently used when growing a nitride layer to be used as a hard mask during shallow trench isolation (STI) region formation.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Fabian Koehler, Itasham Hussain, Bianca Antonioli-Trepte
  • Patent number: 9012335
    Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Publication number: 20150104955
    Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 16, 2015
    Inventor: Viljami Pore
  • Publication number: 20150099374
    Abstract: Provided is a method of forming a silicon nitride film on a surface to be processed of a target object, which includes: repeating a first process a first predetermined number of times, the process including supplying a silicon source gas containing silicon toward the surface to be processed and supplying a decomposition accelerating gas containing a material for accelerating decomposition of the silicon source gas toward the surface to be processed; performing a second process of supplying a nitriding gas containing nitrogen toward the surface to be processed a second predetermine number of times; and performing one cycle a third predetermined number of times, the one cycle being a sequence including the repetition of the first process and the performance of the second process to form the silicon nitride film on the surface to be processed.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 9, 2015
    Inventors: Akinobu KAKIMOTO, Kazuhide HASEBE
  • Patent number: 8999847
    Abstract: Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Gaku Furuta, Soo Young Choi, Beom Soo Park, Young-jin Choi, Omori Kenji
  • Patent number: 8999863
    Abstract: A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 7, 2015
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jae Gon Lee, Jingze Tian, Shyue Seng Tan, Luona Goh, Wei Lu, Elgin Quek
  • Patent number: 8981466
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Publication number: 20150050818
    Abstract: Disclosed is a substrate processing apparatus, including: a processing chamber for processing a substrate; a substrate rotating mechanism for rotating the substrate; a gas supply unit for supplying gas to the substrate, at least two kinds of gases A and B being alternately supplied a plurality of times to form a desired film on the substrate; and a controller for controlling a rotation period of the substrate or a gas supply period defined as a time period between an instant when the gas A is made to flow and an instant when the gas A is made to flow next time such that the rotation period and the gas supply period are not brought into synchronization with each other at least while the alternate gas supply is carried out predetermined times.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 19, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masanori SAKAI, Tomohiro YOSHIMURA
  • Publication number: 20150050817
    Abstract: A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 19, 2015
    Inventor: Xu CHENG
  • Patent number: 8956984
    Abstract: Provided is a method of manufacturing a semiconductor device capable of forming a nitride layer having high resistance to hydrogen fluoride at low temperatures. The method includes forming a nitride film on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate, supplying a plasma-excited hydrogen-containing gas to the substrate, supplying a plasma-excited or thermally excited nitriding gas to the substrate, and supplying at least one of a plasma-excited nitrogen gas and a plasma-excited rare gas to the substrate.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Kazuyuki Okuda
  • Patent number: 8940615
    Abstract: The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang
  • Patent number: 8940586
    Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chris Kuo, Lee-Chuan Tseng
  • Patent number: 8937369
    Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • Patent number: 8906455
    Abstract: This invention discloses the method of forming silicon nitride, silicon oxynitride, silicon oxide, carbon-doped silicon nitride, carbon-doped silicon oxide and carbon-doped oxynitride films at low deposition temperatures. The silicon containing precursors used for the deposition are monochlorosilane (MCS) and monochloroalkylsilanes. The method is preferably carried out by using plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, and plasma enhanced cyclic chemical vapor deposition.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 9, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Liu Yang, Xinjian Lei, Bing Han, Manchao Xiao, Eugene Joseph Karwacki, Jr., Hansong Cheng
  • Patent number: 8895457
    Abstract: To provide a method of manufacturing a semiconductor device, including: forming a thin film different from a silicon oxide film on a substrate by supplying a processing gas into a processing vessel in which the substrate is housed; removing a deposit including the thin film adhered to an inside of the processing vessel by supplying a fluorine-containing gas into the processing vessel after executing forming the thin film prescribed number of times; and forming a silicon oxide film having a prescribed film thickness on the inside of the processing vessel by alternately supplying a silicon-containing gas, and an oxygen-containing gas and a hydrogen-containing gas into the heated processing vessel in which a pressure is set to be less than an atmospheric pressure after removing the deposit.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Kotaro Murakami, Yoshiro Hirose, Kenji Kameda
  • Patent number: 8895455
    Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: November 25, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose
  • Publication number: 20140339497
    Abstract: Fluorescent semiconductor nanocrystals and quantum dots having an inorganic coating on the outermost surface of the nanocrystal are described herein as well as methods for preparing and using such nanocrystals and quantum dots. Devices in which such nanocrystals and quantum dots are used are also described.
    Type: Application
    Filed: June 20, 2012
    Publication date: November 20, 2014
    Applicant: CRYSTALPLEX CORPORATION
    Inventors: Lianhua Qu, Matthew W. Bootman
  • Patent number: 8889568
    Abstract: Disclosed are: a method for producing a silicon nitride film, wherein generation of blisters at the periphery of a substrate is suppressed when a silicon nitride film is formed through application of a bias power; and an apparatus for producing a silicon nitride film. Specifically disclosed are a method and apparatus for producing a silicon nitride film, wherein a silicon nitride film used for a semiconductor element is formed on a substrate by plasma processing. In the method and apparatus for producing a silicon nitride film, a bias is applied to the substrate at time (b1), and a starting material gas SiH4 for the silicon nitride film is started to be supplied at time (b3) after the application of the bias.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: November 18, 2014
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Seiji Nishikawa, Hidetaka Kafuku, Tadashi Shimazu
  • Patent number: 8883624
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 11, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 8871656
    Abstract: Methods of depositing initially flowable dielectric films on substrates are described. The methods include introducing silicon-containing precursor to a deposition chamber that contains the substrate. The methods further include generating at least one excited precursor, such as radical nitrogen or oxygen precursor, with a remote plasma system located outside the deposition chamber. The excited precursor is also introduced to the deposition chamber, where it reacts with the silicon-containing precursor in a reaction zone deposits the initially flowable film on the substrate. The flowable film may be treated in, for example, a steam environment to form a silicon oxide film.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin K. Ingle
  • Publication number: 20140315393
    Abstract: A method of manufacturing a semiconductor device includes: pre-treating a surface of a substrate by supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in a process chamber under a pressure less than atmospheric pressure; and forming a film on the pre-treated substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas to the substrate in the process chamber; and supplying a reaction gas to the substrate in the process chamber.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 23, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takashi OZAKI, Hideki HORITA
  • Patent number: 8846536
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Patent number: 8835240
    Abstract: A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corporation
    Inventors: An-Chi Liu, Chih-Wen Teng, Tzu-Yu Tseng, Chi-Heng Lin
  • Publication number: 20140252427
    Abstract: Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Thomas N. Adam
  • Patent number: 8809207
    Abstract: A pattern-forming method for forming a predetermined pattern serving as a mask when etching film on a substrate includes the steps of: an organic film pattern-forming step for forming an organic film pattern on a film to be processed; forming a silicon nitride film on the organic film pattern; etching the silicon nitride film so that the silicon nitride film remains only on the lateral wall sections of the organic film pattern; and removing the organic film, thereby forming the predetermined silicon nitride film pattern on the film to be processed on a substrate. With the temperature of the substrate maintained at no more than 100° C., the film-forming step excites a processings gas and generates a plasma, performs plasma processing with the plasma, and forms a silicon nitride film having stress of no more than 100 MPa.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiraku Ishikawa, Teruyuki Hayashi, Takaaki Matsuoka, Yuji Ono
  • Patent number: 8809202
    Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Weng, Wei-Sheng Yun, Shao-Ming Yu, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8791034
    Abstract: A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6×10^-11 to about 8×10^-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: July 29, 2014
    Assignee: Cornell University
    Inventors: James R. Shealy, Richard Brown
  • Patent number: 8785312
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8765617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Takeyoshi Masuda