Silicon Nitride Formation Patents (Class 438/791)
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Patent number: 8524591Abstract: In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.Type: GrantFiled: August 2, 2010Date of Patent: September 3, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Sven Beyer, Rick Carter, Andreas Hellmich, Berthold Reimer
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Publication number: 20130210241Abstract: A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido) silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant andType: ApplicationFiled: March 1, 2012Publication date: August 15, 2013Applicant: Novellus Systems Inc.Inventors: Adrien LaVoie, Mark J. Saly, Daniel Moser, Rajesh Odedra, Ravi Kanjolia
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Patent number: 8497191Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.Type: GrantFiled: October 14, 2008Date of Patent: July 30, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi
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Publication number: 20130189853Abstract: This invention discloses the method of forming silicon nitride, silicon oxynitride, silicon oxide, carbon-doped silicon nitride, carbon-doped silicon oxide and carbon-doped oxynitride films at low deposition temperatures. The silicon containing precursors used for the deposition are monochlorosilane (MCS) and monochloroalkylsilanes. The method is preferably carried out by using plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, and plasma enhanced cyclic chemical vapor deposition.Type: ApplicationFiled: September 21, 2012Publication date: July 25, 2013Applicants: TOKYO ELECTRON LIMITED, AIR PRODUCTS AND CHEMICALS, INC.Inventors: Liu Yang, Xinjian Lei, Bing Han, Manchao Xiao, Eugene Joseph Karwacki, JR., Kazuhide Hasebe, Masanobu Matsunaga, Masato Yonezawa, Hansong Cheng
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Method of fabricating a device using low temperature anneal processes, a device and design structure
Patent number: 8490029Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: GrantFiled: March 15, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang -
Patent number: 8470678Abstract: A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET.Type: GrantFiled: February 24, 2011Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Chun-chen Yeh, Pranita Kulkarni
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Patent number: 8450207Abstract: The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line.Type: GrantFiled: June 21, 2011Date of Patent: May 28, 2013Assignee: Nanya Technology Corp.Inventors: Shyam Surthi, Lars Heineck
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Patent number: 8450813Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.Type: GrantFiled: June 25, 2010Date of Patent: May 28, 2013Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
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Patent number: 8445381Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.Type: GrantFiled: December 20, 2007Date of Patent: May 21, 2013Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sundar Narayanan
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Patent number: 8445973Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.Type: GrantFiled: June 24, 2010Date of Patent: May 21, 2013Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Zhijiong Luo, Huilong Zhu, Haizhou Yin
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Patent number: 8440580Abstract: A method for fabricating a silicon nitride gap-filling layer is provided. A pre-multi-step formation process is performed to form a stacked layer constituting as a dense film on a substrate. Then, a post-single step deposition process is conducted to form a cap layer constituting as a sparse film on the stacked layer, wherein the cap layer has a thickness of at least 10% of the total film thickness.Type: GrantFiled: September 11, 2007Date of Patent: May 14, 2013Assignee: United Microelectronics Corp.Inventors: Neng-Kuo Chen, Chao-Ching Hsieh, Chien-Chung Huang
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Publication number: 20130102161Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate in a process chamber, and removing a deposit from at least a portion of an inside of the process chamber after forming the film, wherein removing the deposit includes performing a cycle a predetermined number of times, the cycle including a first process of supplying a first gas for etching the deposit into the process chamber and a second process of supplying a second gas into the process chamber so as to increase a pressure in the process chamber, the second gas being incapable of etching a member constituting the process chamber or having an etchability against the member lower than that of the first gas.Type: ApplicationFiled: October 12, 2012Publication date: April 25, 2013Applicant: Hitachi Kokusai Electric Inc.Inventor: Hitachi Kokusai Electric Inc.
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Patent number: 8426288Abstract: A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.Type: GrantFiled: December 29, 2011Date of Patent: April 23, 2013Assignee: Shanghai Huali Microelectronics CorporationInventors: Qiang Xu, Wenguang Zhang, Chunsheng Zheng, Yuwen Chen
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Patent number: 8426302Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes: forming a stack structure by alternately stacking control gate electrodes and interlayer insulating films; forming a through-hole that penetrates through the stack structure in a stacking direction of the control gate electrodes and the interlayer insulating films; forming a first insulating film that covers an inner surface of the through-hole; forming a charge storage layer that covers an inner surface of the first insulating film; forming a second insulating film that covers an inner surface of the charge storage layer; forming a semiconductor layer that covers an inner surface of the second insulating film; and oxidizing an interface between the semiconductor layer and the second insulating film by performing a heat treatment in an atmosphere containing O2 gas at a temperature of 600° C. or lower.Type: GrantFiled: February 10, 2012Date of Patent: April 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Koichi Kato, Yuichiro Mitani
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Patent number: 8420477Abstract: A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400° C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.Type: GrantFiled: April 27, 2011Date of Patent: April 16, 2013Assignee: Nanya Technology CorporationInventors: Kuo Hui Su, Yi Nan Chen, Hsien Wen Liu
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Patent number: 8415258Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying at least two types of source gases into the process vessel, each of the at least two types of source gases containing the element, and (b) changing the layer containing the element by supplying reaction gas into the process vessel, the reaction gas being different from the at least two types of source gases; and unloading the processed substrate from the process vessel.Type: GrantFiled: November 1, 2011Date of Patent: April 9, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
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Publication number: 20130082362Abstract: A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process.Type: ApplicationFiled: November 25, 2011Publication date: April 4, 2013Inventors: Huaxiang Yin, Qiuxia Xu, Dapeng Chen
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Patent number: 8410003Abstract: A method of manufacturing a semiconductor device includes forming a layer containing a predetermined element on a substrate by supplying a source gas containing the predetermined element into a process vessel and exhausting the source gas from the process vessel to cause a chemical vapor deposition (CVD) reaction. A nitrogen-containing gas is supplied into the process vessel and then exhausted, changing the layer containing the predetermined element into a nitride layer. This process is repeated to form a nitride film on the substrate. The process vessel is purged by supplying an inert gas into the process vessel and exhausting the inert gas from the process vessel between forming the layer containing the predetermined element and changing the layer containing the predetermined element into the nitride layer.Type: GrantFiled: June 24, 2011Date of Patent: April 2, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Yosuke Ota, Yoshiro Hirose, Naonari Akae, Yushin Takasawa
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Patent number: 8367562Abstract: Ultrathin layers are deposited by chemical vapor deposition (CVD) with reduced discontinuities, such as pinholes. Embodiments include depositing a material on a wafer by CVD while rotating the CVD showerhead and/or the wafer mounting surface, e.g., at least 45°. Embodiments include rotating the showerhead and/or mounting surface continuously through the deposition of the material. Embodiments also include forming subfilms of the material and rotating the showerhead and/or mounting surface after the deposition of each subfilm. The rotation of the showerhead and/or mounting surface averages out the non-uniformities introduced by the CVD showerhead, thereby eliminating discontinuities and improving within wafer and wafer-to-wafer uniformity.Type: GrantFiled: March 16, 2009Date of Patent: February 5, 2013Assignee: Globalfoundries Inc.Inventor: Errol T. Ryan
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Patent number: 8367563Abstract: A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.Type: GrantFiled: October 7, 2009Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Hui Ouyang, Da-Yuan Lee, Kuang Yuan Hsu, Hun-Jan Tao, Xiong-Fei Yu
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Patent number: 8357574Abstract: A method for fabricating an integrated device is disclosed. The disclosed method provides improved formation selectivity of epitaxial films over a pre-determined region designed for forming an epi film and a protective layer preferred not to form an epi, polycrystalline, or amorphous film thereon during an epi film formation process. In an embodiment, the improved formation selectivity is achieved by providing a nitrogen-rich protective layer to decrease the amount of growth epi, polycrystalline, or amorphous film thereon.Type: GrantFiled: October 14, 2010Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Hui Ouyang, Chi-Ming Yang
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Patent number: 8350334Abstract: A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.Type: GrantFiled: June 13, 2011Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Min Wang, An-Chi Liu, Hsin-Hsing Chen, Chih-Chun Wang
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Patent number: 8343867Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.Type: GrantFiled: September 16, 2011Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Yu-Ying Hsu, Chi-Ju Lee, Sin-Hua Wu, Bao-Ru Young, Harry-Hak-Lay Chuang
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Patent number: 8329596Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.Type: GrantFiled: March 19, 2012Date of Patent: December 11, 2012Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
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Patent number: 8324119Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.Type: GrantFiled: May 7, 2010Date of Patent: December 4, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Carsten Reichel, Thorsten Kammler, Annekathrin Zeun, Stephan Kronholz
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Publication number: 20120286377Abstract: Improved nano-electromechanical system devices and structures and systems and techniques for their fabrication. In one embodiment, a structure comprises an underlying substrate separated from first and second anchor points by first and second insulating support points, respectively. The first and second anchor points are joined by a beam. First and second deposition regions overlie the first and second anchor points, respectively, and the first and second deposition regions exert compression on the first and second anchor points, respectively. The compression on the first and second anchor points causes opposing forces on the beam, subjecting the beam to a tensile stress. The first and second deposition regions suitably exhibit an internal tensile stress having an achievable maximum varying with their thickness, so that the tensile stress exerted on the beam depends at least on part on the thickness of the first and second deposition regions.Type: ApplicationFiled: May 9, 2011Publication date: November 15, 2012Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Sebastian U. Engelmann, Michael A. Guillorn, Fei Liu, Conal E. Murray
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Patent number: 8304352Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.Type: GrantFiled: March 18, 2011Date of Patent: November 6, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Kazuhiro Matsuo, Yoshio Ozawa
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Patent number: 8283263Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: GrantFiled: July 5, 2006Date of Patent: October 9, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
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Patent number: 8283237Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.Type: GrantFiled: December 23, 2010Date of Patent: October 9, 2012Assignee: Applied Materials, Inc.Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
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Patent number: 8273669Abstract: A method for forming a passivated densified nanoparticle thin film on a substrate in a chamber is disclosed. The method includes depositing a nanoparticle ink on a first region on the substrate, the nanoparticle ink including a set of Group IV semiconductor particles and a solvent. The method also includes heating the nanoparticle ink to a first temperature between about 30° C. and about 400° C., and for a first time period between about 1 minute and about 60 minutes, wherein the solvent is substantially removed, and a porous compact is formed. The method further includes flowing an oxidizer gas into the chamber; and heating the porous compact to a second temperature between about 600° C. and about 1000° C., and for a second time period of between about 5 seconds and about 1 hour; wherein the passivated densified nanoparticle thin film is formed.Type: GrantFiled: November 4, 2010Date of Patent: September 25, 2012Assignee: Innovalight, Inc.Inventors: Dmitry Poplavskyy, Maxim Kelman, Mason Terry
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Patent number: 8263489Abstract: A method for the deposition of an anti-reflection film on a substrate is disclosed. A substrate including a plurality of solar cell structures is provided and placed in a vacuum chamber with a target including silicon. A flow of a nitrogen-containing reactive gas into the vacuum chamber is set to a first value while a voltage between the target and ground is switched off and then increased to a second value. A voltage is applied between the target and ground, whereby a film of silicon and nitrogen is deposited on the substrate in a flow of the nitrogen-containing reactive gas which is higher than the first value.Type: GrantFiled: January 21, 2011Date of Patent: September 11, 2012Assignee: OC Oerlikon Balzers AGInventors: Oliver Rattunde, Stephan Voser
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Publication number: 20120220138Abstract: Assembly and method for depositing a thin film including: providing an expanding thermal plasma plume, including at least one chemical component to be deposited; designating a first and a second deposition zone within the plasma plume, such that the first and second deposition zones have a mutually different relative content of the chemical component; providing a substrate, and transporting said substrate through the plasma plume along a substrate transport path having a substrate transport path direction; and providing a mask that is at least partly disposed in the plasma plume and that shields a portion of the substrate transport path from being deposited on, wherein said shielded portion of the substrate transport path extends in the direction of the substrate transport path and bridges at least the first deposition zone, while it starts or terminates in the second deposition zone.Type: ApplicationFiled: September 17, 2010Publication date: August 30, 2012Applicant: OTB SILAR B.V.Inventors: Björn Van Gerwen, Roland Cornelis Maria Bosch, Franciscus Cornelius Dings
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Patent number: 8252653Abstract: A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.Type: GrantFiled: October 21, 2008Date of Patent: August 28, 2012Assignee: Applied Materials, Inc.Inventors: Mihaela Balseanu, Vladimir Zubkov, Li-Qun Xia, Atif Noori, Reza Arghavani, Derek R. Witty, Amir Al-Bayati
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Patent number: 8247331Abstract: A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface; a step of performing first nitriding to the silicon exposed on the surface of the substrate, and forming a silicon nitride film having a thickness of 0.2 nm but not more than 1 nm on the surface of the substrate; and a step of performing first heat treatment to the silicon nitride film in N2O atmosphere and forming a silicon nitride film. This method may further include a step of performing second nitriding to the silicon oxynitride film, and furthermore, may include a step of performing second heat treatment to the silicon oxynitride film after the second nitriding.Type: GrantFiled: December 20, 2007Date of Patent: August 21, 2012Assignee: Tokyo Electron LimitedInventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
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Publication number: 20120208376Abstract: A method of forming a silicon nitride film by using a plasma CVD method, where the silicon nitride film has abundant traps and is useful as a charge accumulation layer of a nonvolatile semiconductor memory device. A silicon nitride film having a lot of traps is formed by performing plasma CVD by using processing gases including a nitrogen gas and a gas of a compound formed of silicon atoms and chlorine atoms, and by setting a pressure in a processing container within a range between more than or equal to 0.1 Pa and less than or equal to 8 Pa, in a plasma CVD apparatus that performs film-formation by introducing microwaves in the processing container by using a planar antenna having a plurality of holes to generate plasma.Type: ApplicationFiled: September 28, 2010Publication date: August 16, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru Honda, Masayuki Kohno, Toshio Nakanishi
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Method of fabricating a device using low temperature anneal processes, a device and design structure
Patent number: 8236709Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.Type: GrantFiled: July 29, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Terence L. Kane, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Yun-Yu Wang -
Publication number: 20120196452Abstract: High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si—N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400° C., and exposing the deposited silicon nitride film to ultraviolet radiation.Type: ApplicationFiled: February 2, 2012Publication date: August 2, 2012Applicant: Applied Materials, Inc.Inventors: Mihaela Balseanu, Michael S. Cox, Li-Qun Xia, Mei-Yee Shek, Jia Lee, Vladimir Zubkov, Tzu-Fang Huang, Rongping Wang, Isabelita Roflox, Hichem M'Saad
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Patent number: 8227305Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.Type: GrantFiled: March 17, 2011Date of Patent: July 24, 2012Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 8227357Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.Type: GrantFiled: March 24, 2010Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: In-Sun Yi, Ki-Hyun Hwang, Jin-Tae Noh, Jae-Young Ahn, Si-Young Choi
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Publication number: 20120178267Abstract: Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as low dielectric constant (k) thin films, high k gate silicates, low temperature silicon epitaxial films, and films containing silicon nitride (Si3N4), siliconoxynitride (SiOxNy) and/or silicon dioxide (SiO2). The precursors of the invention are amenable to use in low temperature (e.g., <500° C.) chemical vapor deposition processes, for fabrication of ULSI devices and device structures.Type: ApplicationFiled: March 19, 2012Publication date: July 12, 2012Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.Inventors: Ziyun Wang, Chongying Xu, Ravi K. Laxman, Thomas H. Baum, Bryan Hendrix, Jeffrey Roeder
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Patent number: 8216950Abstract: A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate.Type: GrantFiled: December 4, 2009Date of Patent: July 10, 2012Assignee: Eudyna Devices Inc.Inventor: Norikazu Iwagami
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Patent number: 8216905Abstract: The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.Type: GrantFiled: April 27, 2010Date of Patent: July 10, 2012Inventors: Ru-Shang Hsiao, Nai-Wen Cheng, Chung-Te Lin, Chien-Hsien Tseng, Shou-Gwo Wuu
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Patent number: 8211783Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include multiply stacking an insulating layer and a conductive layer alternately above a base member. The insulating layer includes silicon oxide. The conductive layer includes silicon. In addition, the method can form a SiOC film on a stacked body of the insulating layers and the conductive layers, pattern the SiOC film, and make a hole in the stacked body by etching the insulating layers and the conductive layers using the patterned SiOC film as a mask.Type: GrantFiled: December 13, 2010Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Noriko Sakurai, Katsunori Yahashi, Tokuhisa Ohiwa
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Publication number: 20120164848Abstract: A plasma-assisted ALD method using a vertical furnace and being performed by repeating a cycle until a desired film thickness is obtained is disclosed. The cycle comprises introducing a source gas containing a source to be nitrided, adsorbing, purging, introducing a nitriding gas and nitriding the source, and then, purging. A flow rate of a second carrier gas during introduction of the nitriding gas is reduced relative to that of a first carrier gas during introduction of the source gas. Particularly, a flow ratio of NH3 gas as the nitriding gas to N2 gas as the second carrier gas is 50:3 or less.Type: ApplicationFiled: December 28, 2011Publication date: June 28, 2012Applicants: Tokyo Electron Limited, Elpida Memory, Inc.Inventors: Motoki FUJII, Masanobu MATSUNAGA, Kazuya YAMAMOTO, Kota UMEZAWA
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Publication number: 20120156894Abstract: This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <550° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least a silane or disilane derivative that is substituted with at least one alkylhydrazine functional groups and is free of halogen substitutes.Type: ApplicationFiled: February 9, 2012Publication date: June 21, 2012Applicant: Advanced Technology Materials, Inc.Inventors: Ziyun Wang, Chongying Xu, Thomas H. Baum
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Patent number: 8202806Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.Type: GrantFiled: October 3, 2005Date of Patent: June 19, 2012Assignee: Micron Technology, Inc.Inventors: Randhir P.S. Thakur, Ravi Iyer, Howard Rhodes
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Patent number: 8178448Abstract: Disclosed is a method for using a film formation apparatus to form a silicon nitride film by CVD on target substrates while suppressing particle generation. The apparatus includes a process container and an exciting mechanism attached on the process container. The method includes conducting a pre-coating process by performing pre-cycles and conducting a film formation process by performing main cycles. Each of the pre-cycles and main cycles alternately includes a step of supplying a silicon source gas and a step of supplying a nitriding gas with steps of exhausting gas from inside the process container interposed therebetween. The pre-coating process includes no period of exciting the nitriding gas by the exciting mechanism. The film formation process repeats a first cycle set that excites the nitriding gas by the exciting mechanism and a second cycle that does not excite the nitriding gas by the exciting mechanism.Type: GrantFiled: August 6, 2010Date of Patent: May 15, 2012Assignee: Tokyo Electron LimitedInventors: Nobutake Nodera, Masanobu Matsunaga, Kazuhide Hasebe, Koto Umezawa, Pao-Hwa Chou
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Patent number: 8178436Abstract: Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive capping layer. Further, a first opening is formed in the ILD layer using a first chemistry. A second opening is formed in the tensile capping layer and the compressive capping layer using a second chemistry. Next, a second conductive layer is formed in the first opening and the second opening.Type: GrantFiled: December 21, 2006Date of Patent: May 15, 2012Assignee: Intel CorporationInventors: Sean King, Jason Klaus
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Patent number: 8168549Abstract: There are provided a method of manufacturing a semiconductor device and a substrate processing apparatus by which the quality of a silicon nitride film can be improved. The method comprises: (a) supplying a silicon-containing gas into a process chamber accommodating a substrate in a heated state; (b) switching between an exhaust stop state and an exhaust operation state at least two times while a nitrogen-containing gas is supplied into the process chamber so as to vary an inside pressure of the process chamber such that a maximum inside pressure of the process chamber is at least twenty times higher than a minimum inside pressure of the process chamber. The steps (a) and (b) are alternately repeated to form a silicon nitride film on the substrate.Type: GrantFiled: September 13, 2010Date of Patent: May 1, 2012Assignee: Hitachi Kokusai Electric, Inc.Inventor: Masayuki Asai
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Patent number: 8163623Abstract: A method of manufacturing a semiconductor device which previously form sidewalls between lower electrodes to prevent bunkers and leaning phenomena during a sacrificial layer dip out process, thereby improving characteristic of the device, is provided. The method includes forming a mesh pattern defining a storage node region over a semiconductor substrate, forming a lower electrode over the semiconductor substrate and sidewalls of the mesh pattern, forming a dielectric layer over the semiconductor substrate including the lower electrode, and forming an upper electrode over the dielectric layer.Type: GrantFiled: December 29, 2010Date of Patent: April 24, 2012Assignee: Hynix Semiconductor Inc.Inventor: Jong Hun Choi