Having Selenium Or Tellurium Elemental Semiconductor Component Patents (Class 438/84)
  • Patent number: 8703524
    Abstract: A solar cell includes an absorber layer formed of a CIGAS, copper, indium, gallium, aluminum, and selenium. A method for forming the absorber layer provides for using an indium-aluminum target and depositing an aluminum-indium film as a metal precursor layer using sputter deposition. Additional metal precursor layers such as a CuGa layer are also provided and a thermal processing operation causes the selenization of the metal precursor layers. The thermal processing operation/selenization operation converts the metal precursor layers to an absorber layer. In some embodiments, the absorber layer includes a double graded chalcopyrite-based bandgap.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 22, 2014
    Assignee: TSMC Solar Ltd.
    Inventors: Wen-Tsai Yen, Chung-Hsien Wu, Shih-Wei Chen, Wen-Chin Lee
  • Patent number: 8697480
    Abstract: Methods for treating a semiconductor material, and for making devices containing a semiconducting material, are presented. One embodiment is a method for treating a semiconductor material that includes a chalcogenide. The method comprises contacting at least a portion of the semiconductor material with a chemical agent. The chemical agent comprises a solvent, and an iodophor dissolved in the solvent.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 15, 2014
    Assignee: First Solar, Inc.
    Inventor: Donald Franklin Foust
  • Patent number: 8691612
    Abstract: Provided is a method of enhancing thermoelectric performance by surrounding crystalline semiconductors with nanoparticles by contacting a bismuth telluride material with a silver salt under a substantially inert atmosphere and a temperature approximately near the silver salt decomposition temperature; and recovering a metallic bismuth decorated material comprising silver telluride crystal grains.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 8, 2014
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Hyun-Jung Kim, Sang Hyouk Choi, Glen C. King, Yeonjoon Park, Kunik Lee
  • Patent number: 8664033
    Abstract: A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Haifan Liang
  • Patent number: 8664524
    Abstract: Solar cell structures formed using molecular beam epitaxy (MBE) that can achieve improved power efficiencies in relation to prior art thin film solar cell structures are provided. A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device using MBE are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: March 4, 2014
    Assignee: Uriel Solar, Inc.
    Inventor: James David Garnett
  • Patent number: 8617918
    Abstract: A thermoelectric converter is made of a first thermoelectric conversion material in which at least one type of second thermoelectric conversion material particles having an average size of 1 to 100 nm is dispersed. At least a part of the second thermoelectric conversion material particles is dispersed at a distance not more than the mean free path of the phonons of the first thermoelectric conversion material.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: December 31, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Junya Murai, Takuji Kita
  • Patent number: 8618410
    Abstract: A method of manufacturing improved thin-film solar cells entirely by sputtering includes a high efficiency back contact/reflecting multi-layer containing at least one barrier layer consisting of a transition metal nitride. A copper indium gallium diselenide (Cu(InXGa1-X)Se2) absorber layer (X ranging from 1 to approximately 0.7) is co-sputtered from specially prepared electrically conductive targets using dual cylindrical rotary magnetron technology. The band gap of the absorber layer can be graded by varying the gallium content, and by replacing the gallium partially or totally with aluminum. Alternately the absorber layer is reactively sputtered from metal alloy targets in the presence of hydrogen selenide gas. RF sputtering is used to deposit a non-cadmium containing window layer of ZnS. The top transparent electrode is reactively sputtered aluminum doped ZnO. A unique modular vacuum roll-to-roll sputtering machine is described.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 31, 2013
    Assignee: MiaSole
    Inventor: Dennis R. Hollars
  • Publication number: 20130327393
    Abstract: A method of fabricating a solar cell includes forming a front contact layer over a substrate, and the front contact layer is optically transparent at specified wavelengths and electrically conductive. A first scribed area is scribed through the front contact layer to expose a portion of the substrate. A buffer layer doped with an n-type dopant is formed over the front contact layer and the first scribed area. An absorber layer doped with a p-type dopant is formed over the buffer layer. A back contact layer that is electrically conductive is formed over the absorber layer.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 12, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chin LEE, Wen-Tsai YEN, Liang-Sheng YU, Yung-Sheng CHIU
  • Patent number: 8586401
    Abstract: A solar cell manufacturing method includes forming a first electrode on a substrate, forming a mixed metal layer on the first electrode, forming a light absorbing layer by injecting hydrogen selenide on the entire surface of the mixed metal layer using a gas injection device, and forming a second electrode on the light absorbing layer. Further, the gas injection device includes a gas pipeline, an inner gas pipe positioned in the gas pipeline and having an opening, and a plurality of injection nozzles disposed below the gas pipeline.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: November 19, 2013
    Assignees: Samsung SDI Co., Ltd., Samsung Display Co., Ltd.
    Inventors: Seoung-Jin Seo, Jung-Gyu Nam, Sang-Cheol Park, Woo-Su Lee, Seong-Ryong Hwang, In-Ki Kim
  • Patent number: 8580602
    Abstract: A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: November 12, 2013
    Assignee: Uriel Solar, Inc.
    Inventor: James David Garnett
  • Patent number: 8574538
    Abstract: The invention relates to a solid material with the following formula (A): (Cu+1a-u; Ag+1u; Zn+2b-v-(y/2); Cd+2v; Sn+4c-w-(y/2); 1X+4w; 2X+3y; S?2x)(A), in which the solid material: is in divided state in the form of particles having a mean equivalent diameter of 15 nm to 400 nm; has, according to X-ray diffraction analysis of the solid material, a unique crystalline structure; is suitable for forming a stable dispersion of at least one solid material with formula (A) in a liquid, referred to as dispersion liquid, made up of at least one compound with a value of ?p higher than 8 and a value of ?H higher than 5.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: November 5, 2013
    Assignees: Universite Paul Sabatier Toulouse III, Centre National de la Recherche Scientifique (C.N.R.S.), Institut National des Sciences Appliquees de Toulouse, Ecole Superieure des Beaux-Arts de la Reunion
    Inventors: Jean-Yves Chane-Ching, Arnaud Gillorin, Xavier Marie, Pascal Dufour, Oana Zaberca
  • Patent number: 8563351
    Abstract: A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 8562939
    Abstract: A method for producing a high yield of high quality, low size distribution, and size tunable semiconductor nanocrystals. The method produces III-V, II-VI, II-V, IV-VI, IV, ternary, quarternary, and quinary semiconductor nanocrystals (quantum dots) using a catalyst assisted two-phase reaction.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: October 22, 2013
    Assignee: Evident Technologies
    Inventor: Adam Peng
  • Patent number: 8563353
    Abstract: Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: October 22, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Liu Yang, Xinjian Lei, Iain Buchanan
  • Patent number: 8541048
    Abstract: An absorber layer of a photovoltaic device may be formed on an aluminum or metallized polymer foil substrate. A nascent absorber layer containing one or more elements of group IB and one or more elements of group IIIA is formed on the substrate. The nascent absorber layer and/or substrate is then rapidly heated from an ambient temperature to an average plateau temperature range of between about 200° C. and about 600° C. and maintained in the average plateau temperature range 1 to 30 minutes after which the temperature is reduced.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: September 24, 2013
    Assignee: Nanosolar, Inc.
    Inventors: Craig Leidholm, Brent Bollman
  • Patent number: 8541256
    Abstract: In the preferred embodiment of the present invention, narrow bandgap II-VI compound semiconductor HgxCd1-xTe (0.1?x?0.5) (HgCdTe) wafers are annealed under Cd supersaturated conditions by exposing the HgCdTe planar or mesa surfaces to a Cd molecular beam in a vacuum deposition system before, during, and/or after anneals performed during individual photodiode fabrication process steps or HgCdTe epitaxial growth steps for eliminating or neutralizing the bulk or interfacial defects.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 24, 2013
    Inventor: Chang-Feng Wan
  • Patent number: 8536625
    Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Massachusetts Institute of Technology
    Inventor: Barry E. Burke
  • Patent number: 8524524
    Abstract: A method for forming a back contact for a photovoltaic cell that includes at least one semiconductor layer is provided. The method includes applying a continuous film of a chemically active material on a surface of the semiconductor layer and activating the chemically active material such that the activated material etches the surface of the semiconductor layer. The method further includes removing the continuous film of the activated material from the photovoltaic cell and depositing a metal contact layer on the etched surface of the semiconductor layer.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: September 3, 2013
    Assignee: General Electric Company
    Inventors: Bastiaan Arie Korevaar, Juan Carlos Rojo, Roman Shuba
  • Patent number: 8486750
    Abstract: A fabrication method for solid-state imaging devices includes having circuitry formed on a substrate, forming a lower electrode layer on the circuitry, patterning the lower electrode layer to separate pixel-wise into a set of segments, and forming a compound-semiconductor film of chalcopyrite structure over a whole area of element regions. A resist layer is applied on the compound-semiconductor thin film to pixel-wise pattern in accordance with the lower electrode layer as a base separated into the set of segments, and an ion doping is applied over a whole area of element regions, forming element separating regions in the compound-semiconductor thin film. The method includes removing the resist layer for exposure of surfaces of as set of compound-semiconductor thin films separated pixel-wise by the element separating regions. A transparent electrode layer is formed in a planarizing manner over a whole area of element regions.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 16, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Osamu Matsushima, Kenichi Miyazaki
  • Patent number: 8476105
    Abstract: In one aspect of the present invention, a method is provided. The method includes disposing a substantially amorphous cadmium tin oxide layer on a support; and thermally processing the substantially amorphous cadmium tin oxide layer in an atmosphere substantially free of cadmium from an external source to form a transparent layer, wherein the transparent layer has an electrical resistivity less than about 2×10?4 Ohm-cm. Method of making a photovoltaic device is also provided.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: July 2, 2013
    Assignee: General Electric Company
    Inventors: Holly Ann Blaydes, George Theodore Dalakos, David William Vernooy, Allan Robert Northrup, Juan Carlos Rojo, Peter Joel Meschter, Hongying Peng, Hongbo Cao, Yangang Andrew Xi, Robert Dwayne Gossman, Anping Zhang
  • Patent number: 8436445
    Abstract: A method for processing a thin-film absorber material with enhanced photovoltaic efficiency includes forming a barrier layer on a soda lime glass substrate followed by formation of a stack structure of precursor layers. The method further includes subjecting the soda-lime glass substrate with the stack structure to a thermal treatment process with at least H2Se gas species at a temperature above 400° C. to cause formation of an absorber material. By positioning the substrates close together, during the process sodium from an adjoining substrate in the furnace also is incorporated into the absorber layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 7, 2013
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Patent number: 8431430
    Abstract: A method is provided for fabricating a thin film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor target material. The compound semiconductor target material is deposited onto a substrate to form a thin film having a composition substantially the same as a composition of the compound semiconductor target material.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: April 30, 2013
    Assignee: Sunlight Photonics Inc.
    Inventors: Allan James Bruce, Sergey Frolov, Michael Cyrus
  • Patent number: 8409906
    Abstract: The present invention provides a non-vacuum method of depositing a photovoltaic absorber layer based on electrophoretic deposition of a mixture of nanoparticles with a controlled atomic ratio between the elements. The nanoparticles are first dispersed in a liquid medium to form a colloidal suspension and then electrophoretically deposited onto a substrate to form a thin film photovoltaic absorber layer. The absorber layer may be subjected to optional post-deposition treatments for photovoltaic absorption.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: April 2, 2013
    Assignee: IMRA America, Inc.
    Inventors: Wei Guo, Yu Jin, Bing Liu, Yong Che
  • Patent number: 8404512
    Abstract: The present invention provides methods for forming a doped Group IBIIIAVIA absorber layer for a solar cell. The method includes forming precursor layers that include a dopant rich layer and then annealing the precursor layers. The annealing process results in dopants diffusing through the layers to an exterior surface. The annealing process is periodically halted to remove dopants from the exposed surface.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 26, 2013
    Assignee: SoloPower, Inc.
    Inventors: Serdar Aksu, Mustafa Pinarbasi
  • Patent number: 8395043
    Abstract: A solar cell includes a photoactive, semiconductive absorber layer configured to generate excess charge carriers of opposed polarity by light incident on a front of the absorber layer during operation. The absorber layer is configured to separate and move, via at least one electric field formed in the absorber layer, the photogenerated excess charge carriers of opposed polarity over a minimal effective diffusion length Leff,min. The absorber layer has a thickness Lx of 0<Lx?Leff,min. First contact elements are configured to remove the excess charge carriers of a first polarity on a rear of the absorber layer. Second contact elements are configured remove the excess charge carriers of a second polarity on the rear of the absorber layer. At least one undoped, electrically insulating second passivation region is disposed in an alternating, neighboring arrangement with a first passivation region on the rear of the absorber layer.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: March 12, 2013
    Assignee: Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbH
    Inventors: Rolf Stangl, Bernd Rech
  • Patent number: 8389321
    Abstract: A solar cell includes a substrate, a protective layer located over a first surface of the substrate, a first electrode located over a second surface of the substrate, at least one p-type semiconductor absorber layer located over the first electrode, an n-type semiconductor layer located over the p-type semiconductor absorber layer, and a second electrode over the n-type semiconductor layer. The p-type semiconductor absorber layer includes a copper indium selenide (CIS) based alloy material, and the second electrode is transparent and electrically conductive. The protective layer has an emissivity greater than 0.25 at a wavelength of 2 ?m, has a reactivity with a selenium-containing gas lower than that of the substrate, and may differ from the first electrode in at least one of composition, thickness, density, emissivity, conductivity or stress state. The emissivity profile of the protective layer may be uniform or non-uniform.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: March 5, 2013
    Assignee: MiaSole
    Inventors: Chris Schmidt, John Corson
  • Publication number: 20130048488
    Abstract: A method of making a sputtering target includes forming a sputtering target containing a relatively porous sputtering material. The sputtering material may be initially formed to be substantially free of water or treated to remove substantially all of absorbed or adsorbed water from the sputtering material. The method also includes forming a water impermeable barrier layer over the substantially water free sputtering material to completely or substantially prevent re-absorption or re-adsorption of water in the sputtering material.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Inventor: Paul Shufflebotham
  • Patent number: 8377791
    Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: February 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Laurent Breuil, Franz Schuler, Georg Tempel
  • Patent number: 8372684
    Abstract: The method and system for selenization in fabricating CIS and/or CIGS based thin film solar cell overlaying cylindrical glass substrates. The method includes providing a substrate, forming an electrode layer over the substrate and depositing a precursor layer of copper, indium, and/or gallium over the electrode layer. The method also includes disposing the substrate vertically in a furnace. Then a gas including a hydrogen species, a selenium species and a carrier gas are introduced into the furnace and heated to between about 350° C. and about 450° C. to at least initiate formation of a copper indium diselenide film from the precursor layer.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: February 12, 2013
    Assignee: Stion Corporation
    Inventors: Robert D. Wieting, Steven Aragon, Chester A. Farris, III
  • Patent number: 8372688
    Abstract: A film-forming method includes a preprocessing step (step 1) wherein the inside of a processing chamber is exposed to a gas containing Cl and/or F in a state having no substrate in the processing chamber, and a step (step 2) wherein a substrate is loaded into the processing chamber after the step 1. Then, in a step 3, a gaseous Ge raw material, a gaseous Sb raw material, and a gaseous Te raw material are introduced into the processing chamber having the substrate loaded therein, and a Ge—Sb—Te film formed of Ge2Sb2Te5 is formed on the substrate by CVD.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: February 12, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Yumiko Kawano, Susumu Arima
  • Patent number: 8354586
    Abstract: Certain example embodiments relate to a transparent conductor film stack with cadmium stannate used as a front contact layer and/or a buffer layer in a photovoltaic device or the like. The cadmium stannate-based layers may be provided between the front glass substrate and the semiconductor absorber film in a photovoltaic device (e.g., a CdS and/or CdTe based photovoltaic device). In certain example embodiments, the buffer layer based on cadmium stannate may have a higher resistivity than the transparent conductive oxide layer based on cadmium stannate. In certain example embodiments, one or more index matching layer(s) may be provided between the glass substrate and the layer(s) comprising cadmium stannate, e.g., to help overcome the optical mismatch between the glass substrate and the CdSnOx.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: January 15, 2013
    Assignee: Guardian Industries Corp.
    Inventors: Scott V. Thomsen, Willem den Boer, Yiwei Lu
  • Patent number: 8350289
    Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masanori Tsukuda
  • Patent number: 8344349
    Abstract: Provided is an electronic component that includes a first bi-layer stack including a first silicon oxide layer and a first silicon nitride layer, a second bi-layer stack including a second silicon oxide layer and a second silicon nitride layer, and a convertible structure which is convertible between at least two states having different electrical properties, where the convertible structure is arranged between the first bi-layer stack and the second bi-layer stack.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Friso Jacobus Jedema, Michael Antoine Armand in't Zandt
  • Publication number: 20120325298
    Abstract: One aspect of the present invention includes method of making a photovoltaic device. The method includes disposing an absorber layer on a window layer, wherein the absorber layer includes a first region and a second region. The method includes disposing the first region adjacent to the window layer in a first environment including oxygen at a first partial pressure; and disposing the second region on the first region in a second environment including oxygen at a second partial pressure, wherein the first partial pressure is greater than the second partial pressure. One aspect of the present invention includes a photovoltaic device.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: James Neil Johnson, Bastiaan Arie Korevaar, Yu Zhao
  • Patent number: 8330137
    Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Roger W. Cheek
  • Patent number: 8318530
    Abstract: Described is a continuous electroless deposition method and a system to form a solar cell buffer layer with a varying composition through its thickness are provided. The composition of the buffer layer is varied by varying the composition of a chemical bath deposition solution applied onto an absorber surface on which the buffer layer with varying composition is formed. In one example, the buffer layer with varying composition includes a first section containing CdS, a second section containing CdZnS formed on top of the already deposited CdS, and a third section containing ZnS is formed on the second section All the process steps are applied in a roll-to-roll fashion. In another example, a transparent conductive layer including a first transparent conductive film such as aluminum doped zinc oxide and a second transparent conductive film such as indium tin oxide is deposited over the buffer layer with the varying composition.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 27, 2012
    Assignee: SoloPower, Inc.
    Inventors: Bulent M. Basol, Mustafa Pinarbasi, James Freitag
  • Patent number: 8313976
    Abstract: A solar cell includes a substrate, a first electrode located over the substrate, where the first electrode comprises a first transition metal layer, at least one p-type semiconductor absorber layer located over the first electrode, an n-type semiconductor layer located over the p-type semiconductor absorber layer, and a second electrode located over the n-type semiconductor layer. The first transition metal layer contains (i) an alkali element or an alkali compound and (ii) a lattice distortion element or a lattice distortion compound. The p-type semiconductor absorber layer includes a copper indium selenide (CIS) based alloy material.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: November 20, 2012
    Inventors: Neil M. Mackie, John Corson
  • Patent number: 8298856
    Abstract: A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: October 30, 2012
    Assignee: Uriel Solar, Inc.
    Inventor: James David Garnett
  • Publication number: 20120264254
    Abstract: In the preferred embodiment of the present invention, narrow bandgap II-VI compound semiconductor HgxCd1-xTe (0.1?x?0.5) (HgCdTe) wafers are annealed under Cd supersaturated conditions by exposing the HgCdTe planar or mesa surfaces to a Cd molecular beam in a vacuum deposition system before, during, and/or after anneals performed during individual photodiode fabrication process steps or HgCdTe epitaxial growth steps for eliminating or neutralizing the bulk or interfacial defects.
    Type: Application
    Filed: March 16, 2012
    Publication date: October 18, 2012
    Inventor: Chang-Feng Wan
  • Publication number: 20120264255
    Abstract: The invention relates to the production of a thin film having photovoltaic properties, containing a I-III-VI2-type alloy and deposited by electrolysis, including the following steps: (a) successive deposits of layers of metallic elements I and III; and (b) thermal post-treatment with the addition of element VI. In particular, step (a) comprises the following operations: (a1) depositing a multi-layer structure comprising at least two layers of element I and two layers of element III, deposited in an alternate manner, and (a2) annealing said structure before adding element VI in order to obtain a I-III alloy.
    Type: Application
    Filed: October 6, 2010
    Publication date: October 18, 2012
    Applicant: NEXCIS
    Inventors: Pierre-Philippe Grand, Salvador Jaime, Cedric Broussillou
  • Patent number: 8283198
    Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 8278134
    Abstract: The production method of a photoelectric conversion device comprises adding a chalcogenide powder of a group-IIIB element to an organic solvent including a single source precursor containing a group-IB element, a group-IIIB element, and a chalcogen element to prepare a solution for forming a semiconductor, and forming a semiconductor containing a group-I-III-VI compound by use of the solution for forming a semiconductor.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: October 2, 2012
    Assignee: Kyocera Corporation
    Inventors: Isamu Tanaka, Seiichiro Inai, Yoshihide Okawa, Daisuke Nishimura, Sentaro Yamamoto
  • Publication number: 20120241005
    Abstract: A CIS solar cell having flexibility and high conversion efficiency may be produced, using, as a substrate, a polyimide film which is prepared from an aromatic tetracarboxylic acid component comprising 3,3?,4,4?-biphenyltetracarboxylic dianhydride as the main component and an aromatic diamine component comprising p-phenylenediamine as the main component, and has a maximum dimensional change in the temperature-increasing step of from 25° C. to 500° C. within a range of from +0.6% to +0.9%, excluding +0.6%, based on the dimension at 25° C. before heat treatment.
    Type: Application
    Filed: November 19, 2010
    Publication date: September 27, 2012
    Applicant: Ube Industries, Ltd.
    Inventors: Hiroaki Yamaguchi, Takao Miyamoto, Nobu Iizumi, Ken Kawagishi
  • Patent number: 8268663
    Abstract: In a method of annealing a Cd1-xZnxTe sample/wafer, surface contamination is removed from the sample/wafer and the sample/wafer is then introduced into a chamber. The chamber is evacuated and Hydrogen or Deuterium gas is introduced into the evacuated chamber. The sample/wafer is heated to a suitable annealing temperature in the presence of the Hydrogen or Deuterium gas for a predetermined period of time.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: September 18, 2012
    Assignee: II-VI Incorporated
    Inventors: Csaba Szeles, Michael Prokesch, Utpal Chakrabarti
  • Patent number: 8268664
    Abstract: Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: September 18, 2012
    Assignees: Altis Semiconductor, Adesto Technology Corporation
    Inventor: Faiz Dahmani
  • Patent number: 8268665
    Abstract: Antimony, germanium and tellurium precursors useful for CVD/ALD of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (GST) films and microelectronic device products, such as phase change memory devices, including such films.
    Type: Grant
    Filed: June 26, 2011
    Date of Patent: September 18, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventors: William Hunks, Tianniu Chen, Chongying Xu, Jeffrey F. Roeder, Thomas H. Baum, Matthias Stender, Philip S. H. Chen, Gregory T. Stauf, Bryan C. Hendrix
  • Patent number: 8252619
    Abstract: Systems and processes for treatment of a cadmium telluride thin film photovoltaic device are generally provided. The systems can include a treatment system and a conveyor system. The treatment system includes a preheating section, a treatment chamber, and an anneal oven that are integrally interconnected within the treatment system. The conveyor system is operably disposed within the treatment system and configured for transporting substrates in a serial arrangement into and through the preheat section, into and through the treatment chamber, and into and through the anneal oven at a controlled speed. The treatment chamber is configured for applying a material to a thin film on a surface of the substrate and the anneal oven is configured to heat the substrate to an annealing temperature as the substrates are continuously conveyed by the conveyor system through the treatment chamber.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: August 28, 2012
    Assignee: PrimeStar Solar, Inc.
    Inventors: Cory Allen Schaeffer, Brian Robert Murphy
  • Patent number: 8252618
    Abstract: Methods for manufacturing a cadmium telluride based thin film photovoltaic device are generally disclosed. A resistive transparent layer can be sputtered on a transparent conductive oxide layer from a metal alloy target in a sputtering atmosphere of argon and oxygen that includes argon from about 5% to about 40%. A cadmium sulfide layer can then be formed on the resistive transparent layer. A cadmium telluride layer can be formed on the cadmium sulfide layer; and a back contact layer can be formed on the cadmium telluride layer. The sputtering can be accomplished within a sputtering chamber.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: August 28, 2012
    Assignee: Primestar Solar, Inc.
    Inventor: Patrick Lynch O'Keefe
  • Publication number: 20120208314
    Abstract: A method for forming multiple layers in a single process chamber includes placing a substrate in the process chamber having multiple processing sources and iteratively forming a copper indium gallium selenium (CIGS) including forming multiple relatively thin CIGS layers including forming a copper indium gallium (CIG) layer on the substrate, the CIG layer having a thickness of between less than about 50 angstroms and about 200 angstroms, forming a selenium layer on the CIG layer, the selenium layer having a thickness of between less than about 50 angstroms and about 200 angstroms and heating the substrate, the CIG layer and the selenium layer. A processing chamber system is also disclosed.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 16, 2012
    Inventor: Aiguo Feng
  • Patent number: 8241943
    Abstract: A method of sodium doping in fabricating CIGS/CIS based thin film solar cells includes providing a shaped substrate member. The method includes forming a barrier layer over the surface region followed by a first electrode layer, and then a sodium bearing layer. A precursor layer of copper, indium, and/or gallium materials having an atomic ratio of copper/group III species no greater than 1.0 is deposited over the sodium bearing layer. The method further includes transferring the shaped substrate member to a second chamber and subjecting it to a thermal treatment process within an environment comprising gas-phase selenium species, followed by an environment comprising gas-phase sulfur species with the selenium species being substantially removed to form an absorber layer.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: August 14, 2012
    Assignee: Stion Corporation
    Inventors: Robert D. Wieting, Steven Aragon, Chester A. Farris, III