Avalanche Diode Patents (Class 438/91)
  • Publication number: 20110272561
    Abstract: A Geiger-mode avalanche photodiode may include an anode, a cathode, an output pad electrically insulated from the anode and the cathode, a semiconductor layer having resistive anode and cathode regions, and a metal structure in the semiconductor layer and capacitively coupled to a region from the resistive anode and resistive cathode regions and connected to the output pad. The output pad is for detecting spikes correlated to avalanche events.
    Type: Application
    Filed: March 22, 2011
    Publication date: November 10, 2011
    Applicant: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato SANFILIPPO, Giovanni Condorelli
  • Publication number: 20110241149
    Abstract: An embodiment of a geiger-mode avalanche photodiode includes: a body of semiconductor material, having a first surface and a second surface; a cathode region of a first type of conductivity, which extends within the body; and an anode region of a second type of conductivity, which extends within the cathode region and faces the first surface, the anode and cathode regions defining a junction. The anode region includes at least two subregions, which extend at a distance apart within the cathode region starting from the first surface, and delimit at least one gap housing a portion of the cathode region, the maximum width of the gap and the levels of doping of the two subregions and of the cathode region being such that, by biasing the junction at a breakdown voltage, a first depleted region occupies completely the portion of the cathode region within the gap.
    Type: Application
    Filed: March 24, 2011
    Publication date: October 6, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Massimo Cataldo MAZZILLO, Delfo Nunziato SANFILIPPO
  • Publication number: 20110233386
    Abstract: Embodiments of the present invention include an electron counter with a charge-coupled device (CCD) register configured to transfer electrons to a Geiger-mode avalanche diode (GM-AD) array operably coupled to the output of the CCD register. At high charge levels, a nondestructive amplifier senses the charge at the CCD register output to provide an analog indication of the charge. At low charge levels, noiseless charge splitters or meters divide the charge into single-electron packets, each of which is detected by a GM-AD that provides a digital output indicating whether an electron is present. Example electron counters are particularly well suited for counting photoelectrons generated by large-format, high-speed imaging arrays because they operate with high dynamic range and high sensitivity. As a result, they can be used to image scenes over a wide range of light levels.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 29, 2011
    Applicant: Massachusetts Institute of Technology
    Inventors: David C. Shaver, Bernard B. Kosicki, Robert K. Reich, Dennis D. Rathman, Daniel R. Schuette, Brian F. Aull
  • Patent number: 8008688
    Abstract: The present invention provides a highly reliable photodiode, as well as a simple method of fabricating such a photodiode. During fabrication of the photodiode, a grading layer is epitaxially grown on a top surface of an absorption layer, and a blocking layer, for inhibiting current flow, is epitaxially grown on a top surface of the grading layer. The blocking layer is then etched to expose a window region of the top surface of the grading layer. Thus, the etched blocking layer defines an active region of the absorption layer. A window layer is epitaxially regrown on a top surface of the blocking layer and on the window region of the top surface of the grading layer, and is then etched to form a window mesa.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: August 30, 2011
    Assignee: JDS Uniphase Corporation
    Inventor: Syn-Yem Hu
  • Patent number: 8003478
    Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 23, 2011
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Mark Duskin, Suem Ping Loo, Ali Salih
  • Publication number: 20110198499
    Abstract: Silicon photodetectors using near-infrared dipole antennas. The photodetectors include a silicon region formed on a semiconductor substrate, dipole antenna forming two arms that are spaced apart with the silicon region therebetween and inducing an electromagnetic wave signal of incident light, and electrodes disposed in a vertical direction of the dipole antenna and spaced apart with the silicon region therebetween, where a critical bias voltage is applied to the electrodes to induce an avalanche gain operation in the silicon region.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 18, 2011
    Inventors: Yoon-dong Park, David Andrew Barclay Miller, Young-gu Jin, In-sung Joe
  • Patent number: 7995636
    Abstract: A semiconductor laser apparatus has a Zener diode containing a first semiconductor region of a first conduction type and a second semiconductor region of a second conduction type joined with the first semiconductor region, and a vertical-cavity surface-emitting semiconductor laser diode stacked above the Zener diode and containing at least a first mirror layer of a first conduction type, a second mirror layer of a second conduction type and an active region sandwiched between the first and second mirror layers. The first semiconductor region and the second mirror layer are electrically connected and the second semiconductor region and the first mirror layer are electrically connected.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: August 9, 2011
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Akemi Murakami, Hideo Nakayama, Yasuaki Kuwata, Teiichi Suzuki, Ryoji Ishii
  • Publication number: 20110147879
    Abstract: A wafer structure for an image sensor includes a substrate that has a given conductivity type, a given dopant concentration, and a given concentration of oxygen. An intermediate epitaxial layer is formed over the substrate. The intermediate epitaxial layer has the same conductivity type and the same, or substantially the same, dopant concentration as the substrate but a lower oxygen concentration than the substrate. A thickness of the intermediate epitaxial layer is greater than the diffusion length of a minority carrier in the intermediate layer. A device epitaxial layer is formed over the intermediate epitaxial layer. The device epitaxial layer has the same conductivity type but lower dopant and oxygen concentrations than the substrate.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventor: Cristian A. Tivarus
  • Patent number: 7964435
    Abstract: A method for controlling dopant diffusion is disclosed. Using certain control parameters that are not used in the prior art, the method provides an unprecedented measure of control over the dopant diffusion process. The control parameters include, among others, the size of the diffusion windows in the diffusion mask and the proximity of the diffusion windows to a dopant sink. In some embodiments, the diffusion process is conducted in an epi-reactor.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: June 21, 2011
    Assignee: Princeton Lightware, Inc.
    Inventors: Rafael Ben-Michael, Mark Allen Itzler, Xudong Jiang
  • Patent number: 7961477
    Abstract: A housing comprising a liquid-tight electric bushing is provided. The housing comprises an opening and a printed circuit board comprising at least first and second layers. The first layer is a top side of the printed circuit board and spans the opening. A first contact element is disposed on the top side and in a blind bore through the first layer that extends to the second layer. The second layer is a conductor track in the interior of the printed circuit board.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: June 14, 2011
    Assignee: Siemens Aktiengesellschaft
    Inventors: Josef Deuringer, Richard Eichhorn, Lars Lauer, Gerd Mörsberger, Paul Ponnath, Roland Rabe
  • Publication number: 20110121423
    Abstract: A mask for use in making a planar PN junction in a semiconductor device includes a central mask opening and a plurality of spaced apart concentric mask openings surrounding the central mask opening. The concentric mask openings each have a width less than a maximum dimension of the central mask opening. The central mask opening can be circular and the concentric mask openings can have a ring-shape. The mask can be used to form openings in a wafer layer for introducing an impurity to dope that wafer layer.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 26, 2011
    Applicant: Sensors Unlimited, Inc.
    Inventors: Keith Forsyth, Noah Clay
  • Patent number: 7943409
    Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: May 17, 2011
    Assignees: Lumiense Photonics, Inc., Hanvision Co., Ltd.
    Inventor: Robert Steven Hannebauer
  • Patent number: 7919790
    Abstract: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high.
    Type: Grant
    Filed: February 8, 2009
    Date of Patent: April 5, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Michio Nemoto
  • Publication number: 20110068428
    Abstract: In order to improve reliability by preventing an edge breakdown in a semiconductor photodetector having a mesa structure such as a mesa APD, the semiconductor photodetector comprises a mesa structure formed on a first semiconductor layer of the first conduction type formed on a semiconductor substrate, the mesa structure including a light absorbing layer for absorbing light, an electric field buffer layer for dropping an electric field intensity, an avalanche multiplication layer for causing avalanche multiplication to occur, and a second semiconductor layer of the second conduction type, wherein the thickness of the avalanche multiplication layer at the portion in the vicinity of the side face of the mesa structure is made thinner than the thickness at the central portion of the mesa structure.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 24, 2011
    Applicant: FUJITSU LIMITED,
    Inventors: Nami Yasuoka, Haruhiko Kuwatsuka, Toru Uchida, Yoshihiro Yoneda
  • Patent number: 7910394
    Abstract: A method for forming a photodiode cathode in an integrated circuit imager includes defining and implanting a photodiode cathode region with a photodiode cathode implant dose of a dopant species and defining and implanting an edge region of the photodiode cathode region with a photodiode cathode edge implant dose of a dopant species to form a region of higher impurity concentration than the photodiode cathode impurity concentration.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: March 22, 2011
    Assignee: Foveon, Inc.
    Inventor: Maxim Ershov
  • Patent number: 7898051
    Abstract: An imaging device is provided and includes: a photoelectric conversion layer that has a silicon crystal structure and generates signal charges upon incidence of light; a multiplication and accumulation layer that multiplies the signal charges by a phenomenon of avalanche electron multiplication; and a wiring substrate that reads the signal charges from the multiplication and accumulation layer and transmits the read signal charges.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 1, 2011
    Assignee: FUJIFILM Corporation
    Inventor: Shinji Uya
  • Patent number: 7888251
    Abstract: Apparatus and method are provided for hydrogenating semiconductor or other materials by ultraviolet (UV) radiation in the presence of hydrogen. Hydrogen uptake may be optimized by selection of temperature and wavelength of the UV radiation. Patterned areas may be selectively hydrogenated, such as mesas in Avalanche Photodiode Arrays.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: February 15, 2011
    Assignee: Amethyst Research, Inc.
    Inventors: Terry D. Golding, Ronald Paul Hellmer
  • Publication number: 20110024863
    Abstract: A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D1 of a portion covering the side wall of the mesa is equal to or greater than 850 nm.
    Type: Application
    Filed: June 8, 2010
    Publication date: February 3, 2011
    Applicant: NEC Electronics Corporation
    Inventors: Tomoaki Koi, Isao Watanabe, Takashi Matsumoto
  • Publication number: 20110018086
    Abstract: A system and method providing for the detection of an input signal, either optical or electrical, by using a single independent discrete amplifier or by distributing the input signal into independent signal components that are independently amplified. The input signal can either be the result of photoabsorption process in the wavelengths greater than 950 nm or a low-level electrical signal. The discrete amplifier is an avalanche amplifier operable in a non-gated mode while biased in or above the breakdown region, and includes a composite dielectric feedback layer monolithically integrated with input signal detection and amplification semiconductor layers.
    Type: Application
    Filed: June 28, 2010
    Publication date: January 27, 2011
    Inventor: Krishna Linga
  • Patent number: 7867808
    Abstract: Embodiments relate to an image sensor and a method of manufacturing an image sensor. According to embodiments, an image sensor may include a first substrate, a photodiode, and an ion implantation isolation layer. According to embodiments, circuitry including a metal interconnection may be disposed over the first substrate. A photodiode may be provided in a crystalline semiconductor layer bonded to the first substrate, and electrically connected to the metal interconnection. The ion implantation isolation layer may be provided in the photodiode.
    Type: Grant
    Filed: December 28, 2008
    Date of Patent: January 11, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hee-Sung Shim
  • Publication number: 20100327387
    Abstract: A photodiode may include a first region comprising substantially intrinsic semiconductor material, the region having a first side and a second side opposite to the first side. The photodiode may also include a second region comprising highly-doped p-type semiconductor material formed proximate to the first side of the first region. The photodiode may additionally include a third region comprising highly-doped n-type semiconductor material formed proximate to the second side of the first region. The photodiode may further include a fourth region comprising one of: (i) highly-doped p-type semiconductor formed between the first region and the third region, or (ii) highly-doped n-type semiconductor formed between the first region and the second region.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Ichiro Kasai, Justin G. A. Wehner
  • Patent number: 7851823
    Abstract: A transmitted light absorption/recombination layer, a barrier layer, a wavelength selection/absorption layer, and an InP window layer having a p-type region are supported by an n-type substrate and arranged in that order. Light with a wavelength of 1.3 ?m reaches the wavelength selection/absorption layer through the InP window layer. Then, the light is absorbed by the wavelength selection/absorption layer and drawn from the device as an electric current signal. Light with a wavelength of 1.55 ?m reaches the transmitted light absorption/recombination layer through the barrier layer. Then, the light is absorbed by the transmitted light absorption/recombination layer, generating electrons and holes. These electrons and holes recombine with each other and, hence, disappear.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: December 14, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Eitaro Ishimura
  • Patent number: 7851251
    Abstract: A portable optical detection chip comprises a substrate, a plurality of avalanche-type photosensitive device modules and a plurality of plane mirrors. The plurality of avalanche-type photosensitive device modules are formed on the substrate, and each of them comprises a plurality of avalanche-type photosensitive devices and a plurality of lenses. Each of the lenses is stacked on one of the avalanche-type photosensitive devices. The plurality of plane mirrors are disposed between the avalanche-type photosensitive device modules. That is, the avalanche-type photosensitive device modules are separated from each other by the plane mirrors.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: December 14, 2010
    Assignee: National Tsing Hua University
    Inventors: Fan Gang Tseng, Kuo Yung Hung
  • Publication number: 20100301440
    Abstract: A mesa photodiode which includes a mesa, the sidewall of the mesa is a surface that is inclined in the direction in which the bottom of the mesa becomes wider. At least the sidewall of the mesa is covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type. The semiconductor layer is grown on at least the sidewall of the mesa. The inclined angle of the inclined surface of the mesa at the upper end portion is smaller than the inclined angle of the inclined surface of the mesa at the lower end portion.
    Type: Application
    Filed: April 20, 2010
    Publication date: December 2, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Isao Watanabe, Tomoaki Koi
  • Patent number: 7838318
    Abstract: The present invention relates to a photodiode of an image sensor using a three-dimensional multi-layer substrate, and more particularly, to a method of implementing a buried type photodiode and a structure thereof, and a trench contact method for connecting a photodiode in a multi-layer substrate and a transistor for signal detection.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: November 23, 2010
    Assignee: Lumiense Photonics, Inc.
    Inventor: Robert Steven Hannebauer
  • Patent number: 7838410
    Abstract: A method of electrically connecting an element to wiring includes the steps of forming a conductive fixing member precursor layer at least on wiring provided on a base; and arranging an element having a connecting portion on the wiring such that the connecting portion contacts the conductive fixing member precursor layer, and then heating the conductive fixing member precursor layer to form a conductive fixing member latter, thereby fixing the connecting portion of the element to the wiring, with the conductive fixing member layer therebetween, wherein the conductive fixing member precursor layer is composed of a solution-tape conductive material.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: November 23, 2010
    Assignee: Sony Corporation
    Inventors: Naoki Hirao, Yasunobu Iwakoshi, Katsuhiro Tomoda, Huy Sam
  • Patent number: 7834379
    Abstract: The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 16, 2010
    Assignee: JDS Uniphase Corporation
    Inventors: Zhong Pan, David Venables, Craig Ciesla
  • Publication number: 20100279457
    Abstract: Disclosed is a method for manufacturing a semiconductor light-receiving device having high reproducibility and reliability. Specifically disclosed is a semiconductor light-receiving device 100 with a mesa structure wherein a light-absorbing layer 6, an avalanche multiplication layer 4 and an electric-field relaxation layer 5 are formed on a semiconductor substrate 2. The light-absorbing layer 6, avalanche multiplication layer 4 and electric-field relaxation layer 5 exposed in the side wall of the mesa structure are protected by an SiNx film or an SiOyNz film. The hydrogen concentration in the side wall surface of the electric-field relaxation layer 5 is set at not more than 15%, preferably not more than 10% of the carrier concentration of the electric-field relaxation layer 5.
    Type: Application
    Filed: July 20, 2010
    Publication date: November 4, 2010
    Applicant: NEC CORPORATION
    Inventors: Kazuhiro SHIBA, Kikuo Makita, Takeshi Nakata
  • Publication number: 20100271108
    Abstract: An embodiment of a Geiger-mode avalanche photodiode, having: a body made of semiconductor material of a first type of conductivity, provided with a first surface and a second surface and forming a cathode region; and an anode region of a second type of conductivity, extending inside the body on top of the cathode region and facing the first surface. The photodiode moreover has: a buried region of the second type of conductivity, extending inside the body and surrounding an internal region of the body, which extends underneath the anode region and includes the internal region and defines a vertical quenching resistor; a sinker region extending through the body starting from the first surface and in direct contact with the buried region; and a contact region made of conductive material, overlying the first surface and in direct contact with the sinker region.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 28, 2010
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Delfo Nunziato SANFILIPPO, Massimo Cataldo Mazzillo, Piero Giorgio Fallica
  • Patent number: 7772600
    Abstract: Disclosed are a light emitting device having a zener diode therein and a method of fabricating the light emitting device. The light emitting device comprises a P-type silicon substrate having a zener diode region and a light emitting diode region. A first N-type compound semiconductor layer is contacted to the zener diode region of the P-type silicon substrate to exhibit characteristics of a zener diode together with the P-type silicon substrate. Further, a second N-type compound semiconductor layer is positioned on the light emitting diode region of the P-type silicon substrate. The second N-type compound semiconductor layer is spaced apart from the first N-type compound semiconductor layer. Meanwhile, a P-type compound semiconductor layer is positioned on the second N-type compound semiconductor layer, and an active layer is interposed between the second N-type compound semiconductor layer and the P-type compound semiconductor layer.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: August 10, 2010
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Duck Hwan Oh, Sang Joon Lee, Kyung Hae Kim
  • Patent number: 7741172
    Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: June 22, 2010
    Assignee: Icemos Technology Ltd.
    Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
  • Publication number: 20100148040
    Abstract: An embodiment of a Geiger-mode avalanche photodiode includes a body of semiconductor material having a first conductivity type, a first surface and a second surface; a trench extending through the body from the first surface and surrounding an active region; a lateral-isolation region within the trench, formed by a conductive region and an insulating region of dielectric material, the insulating region surrounding the conductive region; an anode region having a second conductivity type, extending within the active region and facing the first surface. The active region forms a cathode region extending between the anode region and the second surface, and defines a quenching resistor. The photodiode has a contact region of conductive material, overlying the first surface and in contact with the conductive region for connection thereof to a circuit biasing the conductive region, thereby a depletion region is formed in the active region around the insulating region.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 17, 2010
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Delfo Nunziato SANFILIPPO, Massimo Cataldo MAZZILLO
  • Publication number: 20100133636
    Abstract: A semiconductor device includes a semiconductor substrate, a photon avalanche detector in the semiconductor substrate. The photon avalanche detector includes an anode of a first conductivity type and a cathode of a second conductivity type. A guard ring is in the semiconductor substrate and at least partially surrounds the photon avalanche detector. A passivation layer of the first conductivity type is in contact with the guard ring to reduce an electric field at an edge of the photon avalanche detector.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 3, 2010
    Applicants: STMicroelectronics (Research & Development) Limited, The University Court of The University of Edinburgh, Ecole Polytechnique Federale de Lausanne
    Inventors: Justin Richardson, Lindsay Grant, Marek Gersbach, Edoardo Charbon, Christiano Niclass, Robert Henderson
  • Patent number: 7695997
    Abstract: An electrostatic discharge protection element and a protection resistor, which are formed on an N? drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: April 13, 2010
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yoshio Shimoida, Masakatsu Hoshi, Tetsuya Hayashi, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7687323
    Abstract: The method is disclosed as applied to roughening the light-emitting surface of an LED wafer for reduction of the internal total reflection of the light generated. A masking film of silver is first deposited on the surface of a wafer to be diced into LED chips. Then the masking film is heated to cause its coagulation into discrete particles. Then, using the silver particles as a mask, the wafer surface is dry etched to create pits therein. The deposition of silver on the wafer surface and its thermal coagulation into particles may be either successive or concurrent.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: March 30, 2010
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Tetsuji Matsuo, Mikio Tazima, Takashi Kato
  • Publication number: 20090242934
    Abstract: The present invention provides a highly reliable photodiode, as well as a simple method of fabricating such a photodiode. During fabrication of the photodiode, a grading layer is epitaxially grown on a top surface of an absorption layer, and a blocking layer, for inhibiting current flow, is epitaxially grown on a top surface of the grading layer. The blocking layer is then etched to expose a window region of the top surface of the grading layer. Thus, the etched blocking layer defines an active region of the absorption layer. A window layer is epitaxially regrown on a top surface of the blocking layer and on the window region of the top surface of the grading layer, and is then etched to form a window mesa.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 1, 2009
    Applicant: JDS Uniphase Corporation
    Inventor: Syn-Yem Hu
  • Publication number: 20090242933
    Abstract: A method of manufacture of an avalanche photodiode involving a step of making a recess in a top window layer of an avalanche photodiode layer stack, such that a wall surrounding the recess runs smoothly and gradually from the level of the recess to the level of the window layer. Further, diffusing a dopant over the entire window layer area so as to form a p-n junction at the bottom of the recess, and providing a first electrical isolation region around the recess by buried ion implantation or wet oxidation in order to limit the flow of electrical current to the p-n junction. Forming an isolation trench around the photodiode and a second electrical isolation region by ion implantation into the trench such that the second electrical isolation region runs through the absorption layer of the photodiode.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: JDS Uniphase Corporation
    Inventors: Syn-Yem Hu, Zhong Pan
  • Patent number: 7582515
    Abstract: Embodiments of the present invention generally relate to solar cells and methods and apparatuses for forming the same. More particularly, embodiments of the present invention relate to thin film multi-junction solar cells and methods and apparatuses for forming the same.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: September 1, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Soo-Young Choi, Yong-Kee Chae, Shuran Sheng
  • Patent number: 7569432
    Abstract: A method of manufacturing an LED of high reflectivity includes forming a substrate; depositing an n-type GaN layer on the substrate; depositing an active layer on a first portion of the n-type GaN layer; attaching an n-type metal electrode to a second portion of the n-type GaN layer; depositing a p-type GaN layer on the active layer; forming a metal reflector on the p-type GaN layer; attaching a p-type metal electrode to the metal reflector; and attaching the p-type metal electrode and the n-type metal electrode to an epitaxial layer respectively. The metal reflector includes a transparent layer, an Ag layer, and an Au layer. The transparent layer and the Ag layer are formed by annealing in a furnace, and the Au layer is subsequently coated on the Ag layer.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: August 4, 2009
    Assignee: Chang Gung University
    Inventors: Liann-Be Chang, Shiue-Ching Chiuan, Kuo-Ling Chiang
  • Publication number: 20090184317
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 23, 2009
    Applicant: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato SANFILIPPO, Emilio Antonio SCIACCA, Piero Giorgio FALLICA, Salvatore Antonio LOMBARDO
  • Publication number: 20090184384
    Abstract: An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 23, 2009
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Delfo Nunziato Sanfilippo, Piero Giorgio Fallica
  • Patent number: 7553690
    Abstract: This disclosure is concerned with starved source diffusion methods for forming avalanche photodiodes are provided for controlling an edge effect. In one example, a method for manufacturing an avalanche photodiode includes forming an absorber layer and an avalanche layer over a substrate. Next, a patterned mask defining one or more openings is formed over a surface of the avalanche layer. Finally, a dopant is deposited over the patterned mask and the avalanche layer such that the dopant is blocked by the patterned mask but diffuses into the avalanche layer in areas where the patterned mask defines an opening. The patterned mask is configured such that the depth to which the dopant diffuses into the avalanche layer varies so as to form a sloped diffusion front in the avalanche layer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: June 30, 2009
    Assignee: Finisar Corporation
    Inventors: Daniel Francis, Rashit Nabiev, Richard P. Ratowsky, David Bruce Young, Sunil Thomas, Roman Dimitrov
  • Patent number: 7547587
    Abstract: A laminated structure having light-emitting units is formed on a single-crystal wafer. Electrode patterns are formed on the single-crystal wafer opposite the light-emitting units. Dummy patterns are formed on the single-crystal wafer at a location spaced apart from a location opposite the light-emitting units, and offset from a desired cleavage line intersecting the light-emitting units. A scratch is formed on the desired cleavage line. The wafer is cleaved, originating on the scratch, along the cleavage line orientation, in the direction from the dummy pattern, toward the light-emitting units.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 16, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hitoshi Nakamura, Hajime Abe, Noriaki Ishio
  • Publication number: 20090146238
    Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes ar
    Type: Application
    Filed: August 20, 2008
    Publication date: June 11, 2009
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Sun Yoon, Kun Sik Park, Jong Moon Park, Bo Woo Kim, Jin Yeong Kang
  • Patent number: 7528017
    Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: May 5, 2009
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith
  • Patent number: 7510903
    Abstract: A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: March 31, 2009
    Assignee: Protek Devices LP
    Inventors: Fred Matteson, Venkatesh P. Pai, Donald K. Cartmell
  • Publication number: 20090050933
    Abstract: Disclosed is a semiconductor light-receiving device having high reproducibility and reliability. Also disclosed is a method for manufacturing a semiconductor light-receiving device. Specifically disclosed is a semiconductor light-receiving device 100 with a mesa structure wherein a light-absorbing layer 6, an avalanche multiplication layer 4 and an electric-field relaxation layer 5 are formed on a semiconductor substrate 2. The light-absorbing layer 6, avalanche multiplication layer 4 and electric-field relaxation layer 5 exposed in the side wall of the mesa structure are protected by an SiNx film or an SiOyNz film. The hydrogen concentration in the side wall surface of the electric-field relaxation layer 5 is set at not more than 15%, preferably not more than 10% of the carrier concentration of the electric-field relaxation layer 5.
    Type: Application
    Filed: December 15, 2005
    Publication date: February 26, 2009
    Applicant: NEC Corporation
    Inventors: Kazuhiro Shiba, Kikuo Makita, Takeshi Nakata
  • Publication number: 20090026494
    Abstract: Avalanche photodiodes and methods for forming them are disclosed. The breakdown voltage of an avalanche photodiode is controlled through the inclusion of a diffusion sink that is formed at the same time as the device region of the photodiode. The device region and diffusion sink are formed by diffusing a dopant into a semiconductor to form a p-n junction in the device region. The dopant is diffused through a first diffusion window to form the device region and a second diffusion window to form the diffusion sink. The depth of the p-n junction is based on an attribute of the second diffusion window.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 29, 2009
    Applicant: PRINCETON LIGHTWAVE, INC.
    Inventor: Mark Allen Itzler
  • Patent number: 7474011
    Abstract: A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: January 6, 2009
    Assignee: Integrated Device Technologies, inc.
    Inventors: Chuen-Der Lien, Ta-Ke Tien, Pao-Lu Louis Huang
  • Patent number: RE41336
    Abstract: A fabrication process for a semiconductor device including a plurality of semiconductor layers, the plurality of semiconductor layers including at least a nitrogen-containing alloy semiconductor AlaGabIn1-a-bNxPyAszSb1-x-y-z (0?a?1, 0?b?1, 0<x<1, 0?y<1, 0?z<1), and a method of making the semiconductor device and apparatus. For at least two semiconductor layers out of the plurality of semiconductor layers, a value of lattice strain of said at least two semiconductor layers is set at less than a critical strain at which misfit dislocations are generated at an interface between said two adjacent semiconductor layers.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: May 18, 2010
    Assignee: Opnext Japan, Inc
    Inventors: Masahiko Kondow, Kazuhisa Uomi, Hitoshi Nakamura