Dummy Metallization Patents (Class 438/926)
  • Patent number: 8980718
    Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Yong Chen
  • Patent number: 8984466
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 8951869
    Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Keisuke Tsukamoto, Tatsuyoshi Mihara
  • Patent number: 8901673
    Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 2, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Takamitsu Onda
  • Patent number: 8883638
    Abstract: A method for manufacturing a damascene structure includes providing a substrate having a dielectric layer formed thereon, forming at least a trench in the dielectric layer, forming at least a via hole and a dummy via hole in the dielectric layer, forming a first conductive layer filling up the trench, the via hole and the dummy via hole on the substrate, and performing a chemical mechanical polishing process to form a damascene structure and simultaneously to remove the dummy via hole.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Chan-Yuan Hu, Ssu-I Fu
  • Patent number: 8791528
    Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang, Shau-Lin Shue
  • Patent number: 8772101
    Abstract: One method includes forming first sidewall spacers adjacent opposite sides of a sacrificial gate structure and a gate cap layer, removing the gate cap layer and a portion of the first sidewall spacers to define reduced-height first sidewall spacers, forming second sidewall spacers, removing the sacrificial gate structure to thereby define a gate cavity, whereby a portion of the gate cavity is laterally defined by the second sidewall spacers, and forming a replacement gate structure in the gate cavity, wherein at least a first portion of the replacement gate structure is positioned between the second sidewall spacers. A device includes a gate structure positioned above the substrate between first and second spaced-apart portions of a layer of insulating material and a plurality of first sidewall spacers, each of which are positioned between the gate structure and on one of the first and second portions of the layer of insulating material.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: July 8, 2014
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Ponoth Shom, Cho Jin, Charan Veera Venkata Satya Surisetty
  • Patent number: 8722491
    Abstract: Embodiments of the present invention relate to approaches for forming RMG FinFET semiconductor devices using a low-resistivity metal (e.g., W) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels). A work function layer (e.g., TiN) will be provided over the substrate (e.g., in and around the trenches). A low-resistivity metal gate layer (e.g., W) may then be deposited (e.g., via chemical vapor deposition) and polished (e.g., via chemical-mechanical polishing). Thereafter, the gate metal layer and the work function layer may be etched after the polishing to provide a trench having the etched gate metal layer over the etched work function layer along a bottom surface thereof.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chang Seo Park, Vimal K. Kamineni
  • Patent number: 8692351
    Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Cheng Kuo, Luke Lo, Minghsing Tsai, Ken-Yu Chang, Jye-Yen Cheng, Jeng-Shiun Ho, Hua-Tai Lin, Chih-Hsiang Yao
  • Patent number: 8691652
    Abstract: A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Hsuan-Hsu Chen
  • Patent number: 8685808
    Abstract: A method of fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. In at least one embodiment, a non-conductive material is used for forming the dummy gate feature to replace a sacrificial gate electrode.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Chieh Tsai, Yung-Che Albert Shih, Jhy-Kang Ting
  • Patent number: 8669661
    Abstract: A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are aligned to a straight line. A dummy metal line interconnects the two dummy metal patterns. A width of the dummy metal line is smaller than lengths and widths of the two dummy metal patterns, wherein the width is measure in a direction perpendicular to the straight line. Bottoms of the two dummy metal patterns and the dummy metal line are substantially level with a bottom surface of the metal line.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Yao, Ying-Wen Huang
  • Patent number: 8664057
    Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Pal, Sven Beyer, Andy Wei, Richard Carter
  • Patent number: 8552510
    Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Takamitsu Onda
  • Patent number: 8507919
    Abstract: A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: August 13, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kohji Ishikura
  • Patent number: 8486822
    Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric film on a semiconductor substrate including a pattern region and a dummy region, forming a photoresist pattern on the interlayer dielectric film such that the pattern region and the dummy region are partially exposed, etching the interlayer dielectric film exposed through the photoresist pattern as an etching mask to form a contact hole and a dummy contact hole, filling the contact hole and the dummy contact hole with a conductive material to form a contact plug and a dummy plug, depositing a semiconductor layer on the contact plug and the dummy plug, and subjecting the semiconductor layer to patterning to form a semiconductor layer pattern and a dummy pattern.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: July 16, 2013
    Assignee: SK hynix Inc.
    Inventor: Byung Ho Nam
  • Patent number: 8466052
    Abstract: A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-min Baek, Hee-sook Park, Seong-hwee Cheong, Gil-heyun Choi, Byung-hak Lee, Tae-ho Cha, Jae-hwa Park, Su-kyoung Kim
  • Patent number: 8455955
    Abstract: An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 4, 2013
    Assignee: X-Fab Semiconductor Foundries AG
    Inventors: Paul Ronald Stribley, John Nigel Ellis
  • Patent number: 8452455
    Abstract: In a control device of a plasma processing system, a communication unit is configured to receive processing information related to a carrier of a next processing lot. A determination unit is configured to determine whether the processing information received by the communication unit has pre-treatment information related to one of the plasma processing devices. When it is determined that the processing information has the pre-treatment information by the determination unit, a generation unit is configured to generate an object for declaring execution of the pre-treatment for the carrier of a next processing lot if a desired condition of transferring of the carrier is satisfied. In addition, if the object is generated by the generation unit, a process executing control unit is configured to start the pre-treatment for the target object in the carrier of a next processing lot without any notification that the carrier reaches a destination plasma processing device.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: May 28, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Hiroaki Mochizuki, Masahiro Numakura
  • Patent number: 8445345
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical oxide spacers are in direct contact with a gate dielectric layer of the first transistor device such that the first transistor device has a shifted threshold voltage with respect to the second transistor device.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8418114
    Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 9, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 8409941
    Abstract: The present invention proposes a method of forming a dual contact plug, comprising steps of: forming a source/drain region and a sacrificed gate structure on a semiconductor substrate, the sacrificed gate structure including a sacrificed gate; depositing a first inter-layer dielectric layer; planarizing the first inter-layer dielectric layer to expose the sacrificed gate in the sacrificed gate structure; removing the sacrificed gate and depositing to form a metal gate; etching to form a first source/drain contact opening in the first inter-layer dielectric layer; sequentially depositing a liner and filling conductive metal in the first source/drain contact opening to form a first source/drain contact plug; depositing a second inter-layer dielectric layer on the first inter-layer dielectric layer; etching to form a second source/drain contact opening and a gate contact opening in the second inter-layer dielectric layer; and sequentially depositing a liner and filling conductive metal in the second source/drain
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: April 2, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8399327
    Abstract: A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Won Lee, Jae-Seok Kim, Bo-Un Yoon
  • Patent number: 8384166
    Abstract: A semiconductor device manufacturing method includes the steps of: successively forming, on a semiconductor substrate, a gate insulating film and first and second dummy sections stacked in this order; forming a notch section by processing the gate insulating film and the first and second dummy gate sections into a previously set pattern and making the first dummy gate section move back in the gate length direction relative to the second dummy gate section; forming a side wall of an insulating material in a side part of each of the gate insulating film and the first and second dummy gate sections and embedding the notch section therewith; removing the first and second dummy gate sections to leave the gate insulating film and the notch section in the bottom of a removed portion; and forming a gate electrode made of a conductive material by embedding the removed portion with the conductive material.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: February 26, 2013
    Assignee: Sony Corporation
    Inventor: Kaori Takimoto
  • Patent number: 8349675
    Abstract: A method for forming a gate electrode includes: providing a substrate; forming a gate dielectric layer and forming a sacrificial layer, the sacrificial layer including doping ions, a density of the doping ions in the sacrificial layer decreasing with increasing distance from the substrate; forming a hard mask layer; patterning the sacrificial layer and the hard mask layer; removing part of the patterned sacrificial layer by wet etching with the patterned hard mask layer as a mask, to form a dummy gate electrode which has a top width bigger than a bottom width, and removing the patterned hard mask layer; removing the dummy gate electrode and filling a gate trench with gate material to form a gate electrode which has a top width bigger than a bottom width, which facilitates the filling of the gate material and can avoid or reduce cavity forming in the gate material.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Zhongshan Hong
  • Patent number: 8298919
    Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shoetsu Kogawa, Satoru Nakayama, Seigo Kamata, Shigemitsu Seito
  • Patent number: 8298011
    Abstract: A method for making a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: October 30, 2012
    Assignee: Sony Corporation
    Inventor: Yasushi Tateshita
  • Patent number: 8288262
    Abstract: A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 16, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chun-Hsien Lin
  • Patent number: 8278196
    Abstract: The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 2, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Mao-Rong Yeh, Chun Hsiung Tsai, Tsung-Hung Lee, Da-Wen Lin, Tsz-Mei Kwok
  • Patent number: 8252675
    Abstract: Provided is a method for manufacturing a MOS transistor.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongwon Lee, Boun Yoon, Sang Yeob Han, Chae Lyoung Kim
  • Patent number: 8242615
    Abstract: A COF package in exemplary form includes a flexible base film, inner leads each made of metal and having a thickness d1, which are disposed at a peripheral edge of a semiconductor chip-mounted predetermined spot on the base film and protruded into the semiconductor chip-mounted predetermined spot, dummy patterns having a thickness d2 (<(d1+d3), where d3 is the thickness of the electrodes), which are disposed at predetermined positions within the semiconductor chip-mounted predetermined spot, a semiconductor chip, and an encapsulating resin. The semiconductor chip has a plurality of the electrodes each protruded into a main surface thereof and having the thickness d3. The electrodes are bonded to the inner leads respectively. Further, the encapsulating resin is charged between the base film and the semiconductor chip. The shape and/or position of the dummy patterns may mark the function of one or more inner leads.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: August 14, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshikazu Takahashi
  • Patent number: 8222099
    Abstract: A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 17, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Wenwu Wang, Kai Han, Shijie Chen, Xiaolei Wang, Dapeng Chen
  • Patent number: 8153498
    Abstract: A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: April 10, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Pin Hsu, Chung-Long Cheng, Kong-Beng Thei, Harry Chuang
  • Patent number: 8084311
    Abstract: Embodiments of the present invention provide a method of forming borderless contact for transistor in a replacement metal gate process. The method includes forming a gate on top of a substrate and forming spacers adjacent to sidewalls of the gate; lowering height of the spacers to expose a top portion of the sidewalls of the gate; depositing an etch-stop layer covering the spacers and the upper portion of the sidewalls of the gate; making an opening at a level that is above the spacers and in the upper portion of the sidewalls to expose the gate; and replacing material of the gate from the opening with a new gate material thereby forming a replacement gate. The method further creates a via opening in an inter-level dielectric layer surrounding the gate and spacers, with the via opening exposing the etch-stop layer; removing the etch-stop layer and fill the via opening with a metal material to form borderless contact.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Su Chen Fan, Theodorus E. Standaert
  • Patent number: 8084279
    Abstract: According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The second wiring layer includes a second wiring and third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Kasaoka, Kiyohiko Sakakibara, Noboru Mori, Kazunobu Miki
  • Patent number: 8076205
    Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: December 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Maekawa
  • Patent number: 8053346
    Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Nam Gyu Ryu, Ho Ryong Kim, Won John Choi, Jae Hwan Kim, Seoung Hyun Kang, Young Hee Yoon
  • Patent number: 8048790
    Abstract: Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Patent number: 8021942
    Abstract: In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: September 20, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy Wei, Andrew Waite, Martin Trentzsch, Johannes Groschopf, Gunter Grasshoff, Andreas Ott
  • Patent number: 7981801
    Abstract: A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: July 19, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Kong-Beng Thei, Su-Chen Lai, Gary Shen
  • Patent number: 7977233
    Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: July 12, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Kei Kawahara, Yoshikazu Kasuya
  • Patent number: 7964487
    Abstract: An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Haining S Yang
  • Patent number: 7948021
    Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Maekawa
  • Patent number: 7943497
    Abstract: A substrate surface serving as an SOI region and a substrate surface serving as a bulk region are made to form the same plane easily and highly accurately, a thickness of a buried oxide film is made uniform, and the buried oxide film is also prevented from being exposed on the substrate surface. After partially forming a mask oxide film (19) on a surface of a silicon substrate (12), an oxygen ions (16) are implanted into the surface of the substrate through this mask oxide film, and the substrate is further subjected to annealing treatment to form a buried oxide film (13) inside the substrate. Between the step of forming the mask oxide film and the step of implanting the oxygen ions, a recess portion (12c) with a predetermined depth deeper than a substrate surface (12b) serving as the bulk region where the mask oxide film has been formed is formed in a substrate surface (12a) serving as the SOI region where the mask oxide film is not formed.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: May 17, 2011
    Assignee: Sumco Corporation
    Inventor: Tetsuya Nakai
  • Patent number: 7902671
    Abstract: A semiconductor device includes a semiconductor substrate with a pattern region and a dummy region, an interlayer dielectric film arranged on the semiconductor substrate, a semiconductor layer pattern arranged on the interlayer dielectric film in the pattern region, a dummy pattern arranged on the interlayer dielectric film in the dummy region, a contact plug arranged inside the interlayer dielectric film, and the contact plug connecting the semiconductor layer pattern to the semiconductor substrate, and a dummy plug arranged inside the interlayer dielectric film, the dummy plug corresponding to the dummy pattern. A method for fabricating the semiconductor device includes forming these structures.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Byung Ho Nam
  • Patent number: 7888195
    Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: February 15, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ting Lin, Li-Wei Cheng, Jung-Tsung Tseng, Che-Hua Hsu, Chih-Hao Yu, Tian-Fu Chiang, Yi-Wen Chen, Chien-Ming Lai, Cheng-Hsien Chou
  • Patent number: 7883951
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Patent number: 7879711
    Abstract: A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: February 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu, Jean Wang
  • Patent number: 7858481
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Patent number: 7846802
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: December 7, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald