Abstract: A method for manufacturing a Group III nitride semiconductor light-emitting element of the invention includes a substrate-processing process of forming a main surface including a flat surface and a convex portion 13 on the substrate 10, an epitaxial process of epitaxially growing an underlying layer on the main surface of the substrate 10 so as to cover the flat surface and the convex portion 13, and an LED lamination process of forming an LED structure by epitaxially growing a Group III nitride semiconductor. In the substrate-processing process, mask patterns 15 are sequentially formed in respective regions R1 and R2 of the flat surface using a polygonal reticle 51 having two pairs of parallel opposing ends in a plan view, by a stepper exposure method, and then the flat surface is etched to dispose and form three arbitrary convex portions 13, which are arranged to be adjacent to each other, in an isosceles triangular shape in a plan view.

Abstract: A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.

Abstract: A method of manufacturing a liquid crystal display device which includes pixel electrodes and common electrodes which are alternatively arranged in each pixel defined on a substrate, including the steps of: forming a conductive film on the substrate; forming a mask layer, of which etching selection ratio is different from the conductive layer, on the conductive layer; forming a photo-resist pattern of a fixed pattern on the mask layer; forming a mask pattern, which has an undercut shape to the photo-resist pattern, by etching the mask layer by use of the photo-resist pattern as an etching mask; removing the photo-resist pattern; and etching the conductive film by use of the mask pattern as an etching mask, to provide at least any one of the common electrode and the pixel electrode.

Abstract: This apparatus has two mask segments. Each mask segment has apertures that an ion beam may pass through. These mask segments can move between a first and second position using hinges. One or more workpieces are disposed behind the mask segments when these mask segments are in a second position. The two mask segments are configured to cover the one or more workpieces in one instance. Ions are implanted into the one or more workpieces through the apertures in the mask segments.

Abstract: A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract: A photonic crystal light emitting diode (“PXLED”) is provided. The PXLED includes a periodic structure, such as a lattice of holes, formed in the semiconductor layers of an LED. The parameters of the periodic structure are such that the energy of the photons, emitted by the PXLED, lies close to a band edge of the band structure of the periodic structure. Metal electrode layers have a strong influence on the efficiency of the PXLEDs. Also, PXLEDs formed from GaN have a low surface recombination velocity and hence a high efficiency. The PXLEDs are formed with novel fabrication techniques, such as the epitaxial lateral overgrowth technique over a patterned masking layer, yielding semiconductor layers with low defect density. Inverting the PXLED to expose the pattern of the masking layer or using the Talbot effect to create an aligned second patterned masking layer allows the formation of PXLEDs with low defect density.

Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

Abstract: A second substrate, e.g. a III/V compound semiconductor, is placed on a first substrate, e.g. a wafer, in the vicinity of placement marks on the first substrate. The second substrate is exposed to patterned radiation, e.g. for the manufacture of integrated circuits.

Abstract: Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circuit elements for electronic displays and low-cost integrated circuits such as radio frequency identification (RFID) circuits. In addition, the techniques can be advantageous in the fabrication of integrated circuits incorporating organic semiconductors, which typically are not compatible with wet processes.

Abstract: A rapid thermal processor, having a process chamber, including a stable heat source in the form of a heatable mass. Heat is provided to the heatable mass using a series of heating devices. The temperature of the heatable mass establishes the temperature of a semiconductor wafer placed in contact or in close proximity to the heatable mass. To reduce thermal gradients, the heatable mass can be included in an insulative compartment made of an insulating material, such as opaque quartz and the like. The top of the insulative compartment can include an access portion to allow the semiconductor wafer to be placed on the heatable mass disposed therein. During processing, the wafer may be further exposed to a high intensity radiation energy source for a short duration of time.

Abstract: A mask and method for contact hole exposure. First, a mask including a transparent substrate, a phase shift layer installed on the transparent substrate to define a series of patterns having contact hole areas set in array, an a plurality of metal lines installed on the phase shift layer between the adjacent contact hole areas is provided. Then, an exposure is performed by transmitting a light source, such as deep ultraviolet (UV), extreme ultraviolet, or X-ray, through the mask after the metal lines absorb high degree diffraction waves.

Abstract: In a method for manufacturing an under-bump metallurgy (UBM) layer, a plate having a plurality of openings is prepared. Then, the plate is placed on the wafer. Finally, the material of the under-bump metallurgy layer is sputtered on the wafer using the plate as a sputter mask so as to quickly form the under-bump metallurgy layer.

Abstract: A method for making transistors comprises depositing source electrode and drain electrode features onto a substrate through a single aperture in a stationary shadow mask, said aperture having at least two opposing edges; wherein the shapes of the features are defined by the aperture and location of source materials in relation to the substrate.

Abstract: A modular coating apparatus is disclosed which is adapted to couple to a host system, such as a cluster or in-line type coating system, as well as to operate in stand-alone fashion. The coating apparatus uses extrusion to initially deposit a film having a desired thickness. The substrate upon which the film is deposited may be spun to further distribute the film. Various embodiments of the coating apparatus are disclosed including embodiments utilizing a shim to mask the substrate and embodiments utilizing a rotatable chuck to facilitate cleaning of the substrate and/or the chuck. Preferably the various embodiments are sub-modules which may be interchanged in the main module as desired.

Abstract: In the construction of electronic devices with one or more flip chips and, in some cases, one or more leadless components, mounted on a substrate, the interconnections are made with conductive adhesive deposited using specialized masks. A magnetic metal mask fabricated of a membrane of magnetic material is placed temporarily onto the face of a semiconductor wafer or of a circuit or other substrate. When properly positioned with respect to the wafer or substrate, such as by relational guide holes, the mask is held in place by the magnetic forces produced by a controllable electromagnet. Contact pad openings in the magnetic metal mask are formed by suitable means such as laser cutting or photo-etching. The magnetic metal mask may include a flexible interface layer on the side facing the wafer or substrate to assure tight sealing thereto, so as to reduce smearing and bridging of the conductive adhesive paste and avoid bridging between contact pads that might otherwise occur during deposition of the paste.

Abstract: A method of forming patterns wherein a first exposure is performed using a first alternating phase shift mask, and a second exposure is performed using a second alternating phase shift mask. Phase shift regions and non-phase shift regions of the second mask are made to correspond respectively to non-phase shift regions and phase shift regions of the first mask. Consequently, light transmitted through phase shift regions of the first mask during the first exposure, is transmitted through second non-phase shift regions of the second mask during the second exposure, so that weak light intensity is compensated for. Intensities of light passed through phase shift regions and non-phase shift regions are thus the same. Therefore, the A CD phenomenon and the inversion phenomenon of critical dimensions between phase shift regions and non-phase shift regions with respect to different focuses, may be prevented.

Abstract: In one embodiment, a masking chuck (68) is placed in contact with an integrated circuit structure (70) that contains conductive members (90). The masking chuck (68) is used to deposit a dielectric layer (92) on the integrated circuit structure (70). The dielectric layer (92) is then cured, and the masking chuck (68) is separated from the integrated circuit structure (68) to define openings (96) within the dielectric layer (92) which expose a portion of the underlying conductive members (90). A conductive layer (100) is then deposited in the openings (96), and polished to form conductive members (102) within the openings (96), which are electrically shorted to the underlying conductive members (90).

Abstract: The present invention is a process for making complex structures with nanoscale resolution in parallel by placing an NCG replica-based mask (or other suitable mask) in close proximity to a substrate and controlling, with nanoscale accuracy and precision, the relative movement of the mask and substrate while sequentially or concurrently carrying out a patterning process or processes. Another aspect of the invention is a diamond film with submicron and/or nanoscale features, that can be made by the method of the invention.

Abstract: The present invention relates to a new process of the cantilever structure in the micro-electro-mechanical system (MEMS), and more particularly, to a process that could overcome the contamination problem on the undesired areas during the thin-film growth. Their advantages include not only to substitute the complex technique with sacrificial layer, but also to increase the yield for its simple structure and to deal the sub-micron microelectromechanical system technology for the mature stage on the wet-etching skill.

Abstract: A method for making a set of surface-emitting laser diodes comprises the making of reflectors by the epitaxial growth of at least one semiconductor material through a mask having apertures with inclined flanks. This method leads to the obtaining of the Bragg reflectors obtained in situ, removing the need for the ion etching of a semiconductor substrate followed by a phase for the conditioning of the surface of the sample before the preparation of the desired laser structure.Application: optical power source.