Heterojunction Patents (Class 438/94)
-
Publication number: 20120025212Abstract: Photodiode devices with GeSn active layers can be integrated directly on p+ Si platforms under CMOS-compatible conditions. It has been found that even minor amounts of Sn incorporation (2%) dramatically expand the range of IR detection up to at least 1750 nm and substantially increases the absorption. The corresponding photoresponse can cover of all telecommunication bands using entirely group IV materials.Type: ApplicationFiled: September 16, 2009Publication date: February 2, 2012Applicant: Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State UniversityInventors: John Kouvetakis, Jose Menendez, Radek Roucka, Jay Mathews
-
Publication number: 20120028406Abstract: Embodiments of the present invention involve photovoltaic (PV) cells comprising a semiconducting nanorod-nanocrystal-polymer hybrid layer, as well as methods for fabricating the same. In PV cells according to this invention, the nanocrystals may serve both as the light-absorbing material and as the heterojunctions at which excited electron-hole pairs split.Type: ApplicationFiled: January 27, 2011Publication date: February 2, 2012Inventors: James Harris, Nigel Pickett
-
Patent number: 8105866Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.Type: GrantFiled: February 24, 2010Date of Patent: January 31, 2012Assignee: Eudyna Devices Inc.Inventors: Yoshihiro Yoneda, Ryuji Yamabi
-
Patent number: 8093096Abstract: A high-resistance buffer layer and a window layer (transparent conductive film) are successively formed by the MOCVD method to obtain the same output characteristics as in conventional film deposition by the solution deposition method and to simplify a film deposition method and apparatus. Thus, the cost of raw materials and the cost of waste treatments are reduced to attain a considerable reduction in production cost. After a metallic base electrode layer 1B and a light absorption layer 1C are formed in this order on a glass substrate 1A, a high-resistance buffer layer 1D and a window layer 1E are successively formed in this order in a multi layer arrangement on the light absorption layer 1C of the resultant semifinished solar cell substrate by the MOCVD method. Consequently, a film deposition method and apparatus are simplified and the cost of raw materials and the cost of waste treatments can be reduced.Type: GrantFiled: May 24, 2006Date of Patent: January 10, 2012Assignee: Showa Shell Sekiyu K.K.Inventor: Katsumi Kushiya
-
Publication number: 20110315221Abstract: Method for making a photovoltaic device and structure thereof. The method includes providing a substrate including a glass layer, a first conductive layer on the glass layer, and a cadmium sulfide layer on the first conductive layer. Additionally, the method includes depositing one or more first materials on the cadmium sulfide layer. The one or more first materials include a first quantity of chemical element cadmium and a second quantity of chemical element tellurium. Moreover, the method includes performing a first thermal treatment to at least the first quantity of chemical element cadmium, the second quantity of chemical element tellurium, and a third quantity of chemical element chlorine, so that a polycrystalline layer composed of at least cadmium telluride is formed on the cadmium sulfide layer. Also, the method includes depositing one or more second materials on a surface of the polycrystalline layer.Type: ApplicationFiled: December 20, 2010Publication date: December 29, 2011Applicant: Alion, Inc.Inventors: Thomas HUNT, Mark TOPINKA, Christopher RIVEST
-
Publication number: 20110308607Abstract: A Group III-V solar cell and a manufacturing method thereof, wherein, three amorphous silicon layers are formed on a substrate, which includes a first type amorphous silicon layer, an intrinsic amorphous silicon layer, and a second type amorphous silicon layer. The lattice characteristics of amorphous silicon layer are utilized, and a Group III-V polycrystalline semiconductor layer is formed on said amorphous silicon layer, such that amorphous silicon and Group III-V material are able to perform photoelectric conversion simultaneously in raising photoelectric conversion efficiency of said Group III-V solar cell effectively by means of a direct energy gap of said Group III-V material.Type: ApplicationFiled: January 31, 2011Publication date: December 22, 2011Applicant: AN CHING NEW ENERGY MACHINERY & EQUIPMENT CO.,LTD.Inventors: YEE-SHYI CHANG, Chi-Jen Liu
-
Patent number: 8080484Abstract: A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma.Type: GrantFiled: March 9, 2009Date of Patent: December 20, 2011Assignee: Showa Denko K.K.Inventors: Yasunori Yokoyama, Hisayuki Miki
-
Publication number: 20110303273Abstract: There is disclosed a photovoltaic cell, such as a solar cell, incorporating one or more epitaxially grown layers of SiGe or another germanium material, substantially lattice matched to GaAs. A GaAs substrate used for growing the layers may be removed by a method which includes using a boundary between said GaAs and the germanium material as an etch stop.Type: ApplicationFiled: February 17, 2010Publication date: December 15, 2011Inventor: Robert Cameron Harper
-
Publication number: 20110303904Abstract: A photovoltaic device and method of manufacturing is disclosed. In one embodiment, the device includes a silicon layer and first and second organic layers. The silicon layer has a first face and a second face. First and second electrodes electrically are coupled to the first and second organic layers. A first heterojunction is formed at a junction between the one of the faces of the silicon layer and the first organic layer. A second heterojunction is formed at a junction between one of the faces of the silicon layer and the second organic layer. The silicon layer may be formed without a p-n junction. At least one organic layer may be configured as an electron-blocking layer or a hole-blocking layer. At least one organic layer may be comprised of phenanthrenequinone (PQ). A passivating layer may be disposed between at least one of the organic layers and the silicon layer. The passivating layer may be organic. At least one of the organic layers may passivate a surface of the silicon layer.Type: ApplicationFiled: May 23, 2011Publication date: December 15, 2011Inventors: Sushobhan Avasthi, James C. Sturm, Jeffrey Schwartz
-
Publication number: 20110297213Abstract: An energy efficient triple junction InGaP/GaAs/Ge solar cell. In one embodiment, the triple junction InGaP/GaAs/Ge solar cell includes: a bottom Ge layer; a first tunnel junction layer above the bottom Ge layer; a middle GaAs layer above the first tunnel junction layer; a second tunnel junction layer above the middle GaAs layer; and a top InGaP layer above the second tunnel junction layer.Type: ApplicationFiled: January 12, 2010Publication date: December 8, 2011Inventor: Michael Hideto Tsutagawa
-
Publication number: 20110291103Abstract: A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: STMicroelectronics S.r.lInventor: Massimo Cataldo MAZZILLO
-
Publication number: 20110287578Abstract: A method of fabricating on a semiconductor substrate bifacial tandem solar cells with semiconductor subcells having a lower bandgap than the substrate bandgap on one side of the substrate and with subcells having a higher bandgap than the substrate on the other including, first, growing a lower bandgap subcell on one substrate side that uses only the same periodic table group V material in the dislocation-reducing grading layers and bottom subcells as is present in the substrate and after the initial growth is complete and then flipping the substrate and growing the higher bandgap subcells on the opposite substrate side which can be of different group V material.Type: ApplicationFiled: May 24, 2010Publication date: November 24, 2011Inventors: Steven J. Wojtczuk, Philip T. Chiu, Xuebing Zhang, Edward Gagnon, Michael Timmons
-
Patent number: 8058090Abstract: The present invention relates to the field of thin film solar cells and particularly to an apparatus and method for manufacturing thin film solar cells. At least one material is deposited onto a substrate, whereby the deposited material is heated by means of heating means on a limited area of the deposited material. The substrate and the heating means are continuously moved in relation to each other until a predetermined area of the deposited material is heated, whereby the heated material is cooled in a controlled way, thus, obtaining a desired crystalline structure of the deposited material.Type: GrantFiled: October 6, 2005Date of Patent: November 15, 2011Assignee: Midsummer ABInventor: Sven Lindström
-
Patent number: 8053264Abstract: A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer.Type: GrantFiled: May 12, 2009Date of Patent: November 8, 2011Assignee: The Regents of the University of CaliforniaInventors: Adele Tamboli, Evelyn Lynn Hu, Mathew C. Schmidt, Shuji Nakamura, Steven P. DenBaars
-
Patent number: 8053271Abstract: A device and method for managing terahertz and/or microwave radiation are provided. The device can comprise one or more field effect transistors (FETs) that each include at least one channel contact to a central region of the device channel of the FET. The frequency of the radiation managed by the device can be tuned/adjusted by applying a bias voltage to the FET. The radiation can be impinged on the device, and can be detected by measuring a voltage that is induced by the radiation. Further, the device can generate terahertz and/or microwave radiation by, for example, inducing a voltage between two edge contacts on either side of the device channel and applying the voltage to the channel contact.Type: GrantFiled: December 1, 2009Date of Patent: November 8, 2011Assignee: Sensor Electronic Technology, Inc.Inventors: Michael Shur, Remigijus Gaska
-
Patent number: 8053666Abstract: A p type amorphous silicon layer is stacked, by a CVD method, on a main surface of an n type single-crystalline silicon substrate; an n type amorphous silicon layer is stacked, by the CVD method, on a surface opposite to the surface on which the p type amorphous silicon layer is stacked; and, by using a laser ablation processing method, through-holes are formed in the n type single-crystalline silicon substrate, the p type amorphous silicon layer, and the n type amorphous silicon layer. Subsequently, an insulating layer is formed on an inner wall surface of each of the through-holes, and then a conductive material is filled therein.Type: GrantFiled: May 15, 2008Date of Patent: November 8, 2011Assignee: Sanyo Electric Co., Ltd.Inventor: Yuji Hishida
-
Publication number: 20110269261Abstract: Methods for protecting a cadmium sulfide layer on a substrate are provided. The method can include sputtering a cadmium sulfide layer onto a substrate from a cadmium sulfide target at a sputtering pressure (e.g., about 10 mTorr to about 150 mTorr), and sputtering a cap layer directly on the cadmium sulfide layer. The cap layer can be sputtered directly onto the cadmium sulfide layer without breaking vacuum of the sputtering pressure. Methods are also provided for manufacturing a cadmium telluride based thin film photovoltaic device through depositing a cadmium sulfide layer on a substrate, depositing a cap layer directly on the cadmium sulfide layer, heating the substrate to sublimate at least a portion of the cap layer from the cadmium sulfide layer, and then depositing a cadmium telluride layer on the cadmium sulfide layer. An intermediate substrate for forming a cadmium telluride based thin-film photovoltaic device is also provided.Type: ApplicationFiled: April 30, 2010Publication date: November 3, 2011Applicant: PRIMESTAR SOLAR, INC.Inventors: Jennifer Ann Drayton, Richard Ernest Demaray
-
Publication number: 20110259424Abstract: A method of fabricating a solar cell involves electroplating a Group IIB-VIA material as a first or sub-layer over a junction partner layer, and then forming a second layer, also of a Group IIB-VIA material over the sub-layer. Both the sub-layer and the second layer comprise Te. The electroplating is performed at relatively low temperatures, as for example, below 100° C. Forming the sub-layer by low temperature electroplating produces a small grained compact film that protects the interface between the sub-layer and the junction partner during the formation of the second layer. The second layer may be formed by physical vapor deposition or ink deposition. A solar cell has a first layer of a stoichiometric Group IIB-VIA material formed on a CdS film, and a second layer of a Group IIB-V1A material. Both the first and second layers contain Te. The first layer may comprise CdTe with a grain size small than 0.5 microns and the second layer may comprise CdTe with a grin size in the range of 1-5 microns.Type: ApplicationFiled: April 12, 2011Publication date: October 27, 2011Applicant: EncoreSolar, Inc.Inventor: Bulent M. BASOL
-
Patent number: 8039290Abstract: Methods of making a photovoltaic (PV) cell are disclosed. The methods comprise at least the steps of, providing a first component comprising a cadmium telluride (CdTe) layer comprising an interfacial region, and subjecting the first component to a functionalizing treatment in the presence of a material comprising copper.Type: GrantFiled: December 16, 2009Date of Patent: October 18, 2011Assignee: General Electric CompanyInventors: Scott Feldman-Peabody, Bogdan Lita, Michael Burnash Cozens, Mehran Sadeghi, Yu Zhao, Renee Mary Whitney
-
Publication number: 20110250718Abstract: There is disclosed a modular lamination approach for processing organic photosensitive devices that allows the individual processing of device components, that once processed are brought together in a final step to make electrical contact. The disclosed method of preparing a laminated photosensitive device having at least one donor-acceptor heterojunction comprises: preparing a top electrode by depositing a functional material on a flexible substrate, such as an elastomer; optionally processing the functional material to obtain desired properties prior to lamination; preparing a bottom portion by depositing a second functional material over a substrate; optionally processing the second functional material to obtain desired properties prior to lamination; and coupling the top electrode to said bottom portion to form a laminated photosensitive device.Type: ApplicationFiled: April 8, 2011Publication date: October 13, 2011Inventors: Yueh-Lin Loo, Jong Bok Kim
-
Publication number: 20110248316Abstract: A semiconductor-based SWIR infrared detector sensitive to wavelengths shorter than about 2.5 microns comprises a stack of semiconductor layers based on III-V materials forming a PIN photodiode. The stack includes a naked electrical contact, called a lower electrical contact, serving as an optical window; and a detection layer sensitive to said wavelengths. The lower contact comprises at least one layer of indirect-bandgap III-V material(s) doped n-type, pseudomorphic or lattice matched with a substrate intended to serve as a temporary substrate possibly being made of a III-V material such as InP or GaAs or of silicon or germanium.Type: ApplicationFiled: December 8, 2009Publication date: October 13, 2011Applicant: THALESInventors: Philippe Bois, Olivier Parillaud, Xavier Marcadet, Michel Papuchon
-
Publication number: 20110248315Abstract: An electrode comprising a plurality of structured pillars dispersed across a base contact and its method of manufacture are described. In one embodiment the structured pillars are columnar structures having a circular cross-section and are dispersed across the base surface as a uniformly spaced two-dimensional array. The height, diameter, and separation of the structured pillars are preferably on the nanometer scale and, hence, electrodes comprising the pillars are identified as nanostructured pillar electrodes. The nanostructured pillars may be formed, for example, by deposition into or etching through a surface template using standard lithography processes. Structured pillar electrodes offer a number of advantages when incorporated into optoelectronic devices such as photovoltaic cells. These include improved charge collection efficiency via a reduction in the carrier transport distance and an increase in electrode-photoactive layer interface surface area.Type: ApplicationFiled: August 14, 2009Publication date: October 13, 2011Applicant: BROOKHAVEN SCIENCE ASSOCIATESInventors: Chang-Yong Nam, Charles T. Black, Ioana R. Gearba, Jonathan Edward Allen
-
Patent number: 8034697Abstract: Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping (ART) and epitaxial layer overgrowth (ELO). In general, in a first aspect, embodiments of the invention may include a method of forming a structure. The method includes forming a first opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semi-conductor material lattice-mismatched to the first semiconductor material, is formed within the first opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer.Type: GrantFiled: September 18, 2009Date of Patent: October 11, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: James Fiorenza, Anthony Lochtefeld, Jie Bai, Ji-Soo Park, Jennifer Hydrick, Jizhong Li, Zhiyuan Cheng
-
Patent number: 8030679Abstract: Disclosed is a nitride semiconductor light emitting device including: one or more AllnN layers; an In-doped nitride semiconductor layer formed above the AllN layers; a first electrode contact layer formed above the In-doped nitride semiconductor layer; an active layer formed above the first electrode contact layer; and a p-type nitride semiconductor layer formed above the active layer. According to the nitride semiconductor light emitting device, a crystal defect of the active layer is suppressed, so that the reliability of the nitride semiconductor light emitting device is increased and the light output is enhanced.Type: GrantFiled: October 6, 2005Date of Patent: October 4, 2011Assignee: LG Innotek Co., Ltd.Inventors: Hyo Kun Son, Suk Hun Lee
-
Publication number: 20110232730Abstract: An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 eV, namely, Ga1-xInxNyAs1-y-zSbz with a low antimony (Sb) content and with enhanced indium (In) content and enhanced nitrogen (N) content, achieving substantial lattice matching to GaAs and Ge substrates and providing both high short circuit currents and high open circuit voltages in GaInNAsSb subcells for multijunction solar cells. The composition ranges for Ga1-xInxNyAs1-y-zSbz are 0.07?x?0.18, 0.025?y?0.04 and 0.001?z?0.03.Type: ApplicationFiled: March 29, 2010Publication date: September 29, 2011Applicant: Solar Junction Corp.Inventors: Rebecca Elizabeth Jones, Homan Bernard Yuen, Ting Liu, Pranob Misra
-
Publication number: 20110227116Abstract: An object of the present invention is to provide a germanium laser diode that can be easily formed on a substrate such as silicon by using a normal silicon process and can emit light efficiently. A germanium light-emitting device according to the present invention is a germanium laser diode characterized in that tensile strain is applied to single-crystal germanium serving as a light-emitting layer to be of a direct transition type, a thin semiconductor layer made of silicon, germanium or silicon-germanium is connected adjacently to both ends of the germanium light-emitting layer, the thin semiconductor layer has a certain degree of thickness capable of preventing the occurrence of quantum confinement effect, another end of the thin semiconductor layer is connected to a thick electrode doped with impurities at a high concentration, the electrode is doped to a p type and an n type, a waveguide is formed so as not to be in direct contact with the electrode, and a mirror is formed at an end of the waveguide.Type: ApplicationFiled: October 21, 2009Publication date: September 22, 2011Applicant: HITACHI, LTD.Inventors: Shinichi Saito, Masahiro Aoki, Nobuyuki Sugii, Katsuya Oda, Toshiki Sugawa
-
Publication number: 20110214725Abstract: A photovoltaic device can include a graded bandgap buffer layer.Type: ApplicationFiled: February 25, 2011Publication date: September 8, 2011Applicant: First Solar, Inc.Inventor: Markus E. Beck
-
Patent number: 8012788Abstract: A method is provided for producing a film of compound material. The method includes providing a substrate and depositing a film on the substrate. The deposited film has a first chemical composition that includes at least one first chemical element and at least one second chemical element. At least one residual chemical reaction is induced in the deposited film using a source containing at least one second chemical element to thereby increase the content of at least one second chemical element in the deposited film so that the deposited film has a second chemical composition. The content of at least one second element in the second chemical composition is larger than the content of at least one second element in the first chemical composition.Type: GrantFiled: March 21, 2011Date of Patent: September 6, 2011Assignee: Sunlight Photonics Inc.Inventors: Sergey Frolov, Allan James Bruce, Michael Cyrus
-
Publication number: 20110210313Abstract: A method for manufacturing a semiconductor device, by which a multiple quantum well structure having a large number of pairs can be efficiently grown while maintaining good crystalline quality, and the semiconductor device, are provided. The semiconductor device manufacturing method of the present invention includes a step of forming a multiple quantum well structure 3 having 50 or more pairs of group III-V compound semiconductor quantum wells. In the step of forming the multiple quantum well structure 3, the multiple quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources (all metal-organic source MOVPE).Type: ApplicationFiled: July 7, 2010Publication date: September 1, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kei Fujii, Takashi Ishizuka, Katsushi Akita, Youichi Nagai, Tatsuya Tanabe
-
Publication number: 20110203651Abstract: A solar cell includes a graphite substrate, an amorphous carbon layer having a thickness of not less than 20 nm and not more than 60 nm formed on the graphite substrate, an AlN layer formed on the amorphous carbon layer, a n-type nitride semiconductor layer formed on the AlN layer; a light-absorption layer including a nitride semiconductor layer formed on the n-type nitride semiconductor layer; a p-type nitride semiconductor layer formed on the light-absorption layer; a p-side electrode electrically connected to the p-type nitride semiconductor layer; and an n-side electrode electrically connected to the n-type nitride semiconductor layer. The amorphous carbon layer is obtained by oxidizing the surface of the graphite substrate.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicants: Panasonic Corporation, Okuda & AssociatesInventors: Nobuaki NAGAO, Takahiro HAMADA, Akihiro ITOH
-
Publication number: 20110204214Abstract: A light detection system is disclosed. The system comprises a light absorbing layer made of a semiconductor having majority carriers and minority carriers, and being incorporated with bandgap modifying atoms at a concentration selected so as to allow generation of photocurrent indicative of absorption of photons at any wavelength at least in the range of from about 3 ?m to about 5 ?m.Type: ApplicationFiled: February 21, 2011Publication date: August 25, 2011Applicant: Technion Research & Development Foundation Ltd.Inventors: Gad Bahir, Dan Fekete, Asaf Albo
-
Publication number: 20110203666Abstract: A solar cell including a base of single crystal silicon with a cubic crystal structure and a single crystal layer of a second material with a higher bandgap than the bandgap of silicon. First and second single crystal transition layers are positioned in overlying relationship with the layers graduated from a cubic crystal structure at one surface to a hexagonal crystal structure at an opposed surface. The first and second transition layers are positioned between the base and the layer of second material with the one surface lattice matched to the base and the opposed surface lattice matched to the layer of second material.Type: ApplicationFiled: February 19, 2010Publication date: August 25, 2011Inventors: Michael Lebby, Andrew Clark
-
Patent number: 8003884Abstract: The present invention relates to a photovoltaic device, especially hybrid solar cells, comprising at least one layer comprising evaporated fluoride and/or acetate; and to a method for preparing the same.Type: GrantFiled: August 24, 2005Date of Patent: August 23, 2011Assignee: Sony Deutschland GmbHInventors: Tzenka Miteva, Gabriele Nelles, Akio Yasuda
-
Patent number: 7998789Abstract: A method and a system for forming a copper indium gallium sulfur selenide (CIGSSe) absorption layer and a cadmium sulfide (CdS) buffer layer under non-vacuum condition is disclosed. A coating layer is formed on the back electrode layer on the substrate by mixing the slurry on the back electrode layer, and the coating layer formed on the back electrode layer is densified by a densification device after initially dried, and then a primary selenization/sulfurization reaction process is carried out to form a primary CIGSSe layer, and then a thermal process is carried out to improve the lattice match of the primary CIGSSe layer, and then an impurity cleaning process is carried out by using potassium cyanide or bromide to remove the impurities of cuprous selenide and copper sulfide, and then a rear-stage selenization/sulfurization reaction process is carried out to produce the required rear-stage CIGSSe absorption layer.Type: GrantFiled: April 16, 2010Date of Patent: August 16, 2011Assignee: Jenn Feng New Energy Co., Ltd.Inventor: Chuan-Lung Chuang
-
Publication number: 20110186910Abstract: There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing flexible PV devices comprising a structure having a growth substrate, wherein the selective etching of protective layers yields a smooth growth substrate that us suitable for reuse.Type: ApplicationFiled: September 9, 2010Publication date: August 4, 2011Inventors: Stephen R. Forrest, Jeramy Zimmerman, Kyusang Lee, Kuen-Ting Shiu
-
Publication number: 20110189814Abstract: In a process for producing a photoelectric conversion device comprising a bottom electrode layer, a photoelectric conversion semiconductor layer, a buffer layer, and a transparent conductive layer, which are stacked in this order on a substrate, all film forming stages ranging from a stage of forming the buffer layer to a stage of forming the transparent conductive layer are performed with a liquid phase technique. The buffer layer is formed with a chemical bath deposition technique, and the transparent conductive layer is formed with an electrolytic deposition technique.Type: ApplicationFiled: January 31, 2011Publication date: August 4, 2011Applicant: FUJIFILM CorporationInventors: Tetsuo KAWANO, Takashi Koike, Ryouko Agui
-
Publication number: 20110180129Abstract: The disclosure relates to multiple quantum well (MQW) structures for intrinsic regions of monolithic photovoltaic junctions within solar cells which are substantially lattice matched to GaAs or Ge. The disclosed MQW structures incorporate quantum wells formed of quaternary InGaAsP, between barriers of InGaP.Type: ApplicationFiled: September 28, 2009Publication date: July 28, 2011Inventor: John Roberts
-
Publication number: 20110174363Abstract: Particular embodiments of the present disclosure relate to the use of sputtering, and more particularly magnetron sputtering, in forming absorber structures, and particular multilayer absorber structures, that are subsequently annealed to obtain desired composition profiles across the absorber structures for use in photovoltaic devices.Type: ApplicationFiled: January 12, 2011Publication date: July 21, 2011Applicant: AQT Solar, Inc.Inventor: Mariana Rodica Munteanu
-
Patent number: 7982242Abstract: A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces.Type: GrantFiled: May 7, 2009Date of Patent: July 19, 2011Assignee: Sanken Electric Co., Ltd.Inventor: Hirokazu Goto
-
Publication number: 20110168236Abstract: A luminescent solar concentrator (LSC) for receiving electromagnetic radiation of at least a first wavelength is disclosed. The LSC includes a core layer. A lower clad layer substantially underlies the core layer. At least one photovoltaic (PV) cell is partially embedded in at least one of the core layer and the lower clad layer. At least one dye layer substantially overlies the core layer. The at least one dye layer has embedded therein at least one absorption dipole and at least one emission dipole, the at least one emission dipole being coupled to the at least one absorption dipole.Type: ApplicationFiled: May 21, 2010Publication date: July 14, 2011Inventors: Winston Kong Chan, Michael G. Kane
-
Patent number: 7977139Abstract: Before a buffer layer deposition step P5, a pre-rinse step P4 is provided to remove deposits deposited on the surface of a CIS-based light absorbing layer 3D. Thus, the disturbing factors of the formation reaction of the buffer layer are removed, thereby to improve the coverage of the buffer layer, and to hold the transparency thereof. In addition, a rinse step P6 is provided after the step P5. Thus, the colloidal solid matter remaining on the buffer layer surface is cleaned and removed with a rinse solution, thereby to hold the high resistivity. The rinse solution from a second rinse tank of the step P6 is re-used. After the step P6, a draining/drying step P7 is provided. After drying, an n-type window layer (transparent conductive film) is deposited.Type: GrantFiled: March 28, 2007Date of Patent: July 12, 2011Assignee: Showa Shell Sekiyu K.K.Inventors: Katsumi Kushiya, Yousuke Fujiwara
-
Publication number: 20110155207Abstract: A multi junction photovoltaic cell includes at least two P-N junctions electrically connected to each other in series. Each P-N junction includes a P-type absorber layer and a N-type emitter layer, each P-type absorber layer including a plurality of alternating thin film layers of zinc telluride and lead telluride, wherein zinc telluride and lead telluride have respective bandgaps when in bulk thickness and the effective bandgap of each P-type absorber layer is between the respective bandgaps, The effective bandgap of at least one P-type absorber layer is different from that of at least one other P-type absorber layer.Type: ApplicationFiled: May 11, 2009Publication date: June 30, 2011Applicant: VILLANOVA UNIVERSITYInventor: Pritpal Singh
-
Publication number: 20110146774Abstract: The present invention relates to a solar cell having quantum dot nanowire array and the fabrication method thereof. The solar cell according to the present invention includes quantum dot nanowire array with a heterostructure including matrix and semiconductor quantum dots, and p-type and n-type semiconductor and electrodes each contacting the quantum dot nanowires. With the solar cell according to the present invention, the band gap energy of the semiconductor quantum dot can be easily controlled, the semiconductor quantum dots having different sizes are provided in the quantum dot nanowire so that the photoelectric conversion can be performed in the wide spectrum from visible rays to infrared rays, the quantum dot is embedded in the high density quantum dot nanowire array so that light absorption can be maximized, and the quantum dot nanowire contact p-type and n-type semiconductor over a wide area, conduction efficiency of electrons and holes can be improved.Type: ApplicationFiled: November 10, 2008Publication date: June 23, 2011Applicant: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCEInventors: Kyung Joong Kim, Woo Lee
-
Publication number: 20110146769Abstract: Photovoltaic devices and methods of making photovoltaic devices comprising at least one compositionally graded photoactive layer, said method comprising providing a substrate; growing onto the substrate a uniform intrinsic photoactive layer having one surface disposed upon the substrate and an opposing second surface, said intrinsic photoactive layer consisting essentially of In1-xAxN,; wherein: i. 0?x?1; ii. A is gallium, aluminum, or combinations thereof; and iii. x is at least 0 on one surface of the intrinsic photoactive layer and is compositionally graded throughout the layer to reach a value of 1 or less on the opposing second surface of the layer; wherein said intrinsic photoactive layer is isothermally grown by means of energetic neutral atom beam lithography and epitaxy at a temperature of 600° C. or less using neutral nitrogen atoms having a kinetic energy of from about 1.0 eV to about 5.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Applicant: LOS ALAMOS NATIONAL SECURITY, LLCInventors: Mark A. Hoffbauer, Todd L. Williamson
-
Publication number: 20110146784Abstract: A method for manufacturing a photovoltaic device may include depositing a semiconductor absorber layer on a substrate, depositing a molybdenum in the presence of a nitrogen to form a molybdenum nitride in contact with the semiconductor absorber layer, and doping the molybdenum nitride with a copper dopant.Type: ApplicationFiled: December 16, 2010Publication date: June 23, 2011Applicant: First Solar, Inc.Inventors: Pratima V. Addepalli, Oleh P. Karpenko, Thomas W. Shields
-
Patent number: 7964483Abstract: The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature, thereby, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.Type: GrantFiled: July 7, 2004Date of Patent: June 21, 2011Assignee: Seoul National University Industry FoundationInventors: Euijoon Yoon, Hyunseok Na
-
Publication number: 20110143475Abstract: Method for manufacturing of optoelectronic devices based on thin-film, intermediate band materials, characterized in that it comprises, at least, the following steps: a first stage wherein a substrate (1) is coated with a metal layer acting as electrode (2); a second stage, whereby atop the metal layer (2) a p-type semiconductor (3) is deposited; and a third stage, whereby the intermediate band material is processed; and wherein such an intermediate band material comprises nanoscopic structures (4) of multinary material of the type (Cu,Ag)(Al,Ga,In)(S,Se,Te)2 embedded in a matrix (5) of a similar composition, except for the absence of, at least, one cationic species present in the nanostructure.Type: ApplicationFiled: May 29, 2009Publication date: June 16, 2011Applicant: UNIVERSIDAD POLITÉCNICA DE MADRIDInventors: David Fuertes Marron, Antonio Marti Vega, Antonio Luque Lopez
-
Publication number: 20110143495Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.Type: ApplicationFiled: February 14, 2011Publication date: June 16, 2011Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
-
Publication number: 20110126891Abstract: A solar cell element having improved power generation efficiency is provided. A solar cell element 100 has a substrate 110, a mask pattern 120, semiconductor nanorods 130, a first electrode 150 and a second electrode 160. The semiconductor nanorods 130 are disposed in triangular lattice form as viewed in plan on the substrate 110. The ratio p/d of the center-to-center distance p between each adjacent pair of the semiconductor nanorods 130 and the minimum diameter d of the semiconductor nanorods 130 is within the range from 1 to 7. Each semiconductor nanorod 130 has a central nanorod 131 formed of a semiconductor of a first conduction type, a first cover layer 132 formed of an intrinsic semiconductor and covering the central nanorod 131, and a second cover layer 138 formed of a semiconductor of a second conduction type and covering the first cover layer 132.Type: ApplicationFiled: November 29, 2010Publication date: June 2, 2011Inventors: Hajime Goto, Hirotaka Endo, Kenji Hiruma, Junichi Motohisa, Takashi Fukui
-
Publication number: 20110124146Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.Type: ApplicationFiled: May 28, 2010Publication date: May 26, 2011Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel