Mechanical Polishing Of Wafer Patents (Class 438/959)
  • Patent number: 6350693
    Abstract: An improved and new process for fabricating a planarized structure of polysilicon plugs embedded in silicon oxide has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing using a first polishing slurry which is selective to polysilicon and the second CMP step comprises chemical-mechanical polishing using a second polishing slurry which polishes both polysilicon and silicon oxide. The processing time of the two-step CMP process is significantly less than the processing time of a one-step CMP process requiring an over-polish period. This reduced processing time reduces the cost of the CMP operation and at the same time produces a product with superior planarity and without reliability degradation due to residues of polysilicon.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: February 26, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung-Long Chang, Syun-Ming Jang
  • Patent number: 6346485
    Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: February 12, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takashi Nihonmatsu, Seiichi Miyazaki, Masahiko Yoshida, Hideo Kudo, Tadahiro Kato
  • Patent number: 6339026
    Abstract: In one aspect the invention includes a method of protecting aluminum within an aluminum-comprising layer from electrochemical degradation during semiconductor processing comprising, providing a material within the layer having a lower reduction potential than aluminum. In another aspect, the invention includes a semiconductor processing method of forming and processing an aluminum-comprising mass, comprising: a) forming the aluminum-comprising layer mass to comprise a material having a lower reduction potential than aluminum; and b) exposing the aluminum-comprising mass to an electrolytic substance, the material protecting aluminum within the aluminum-comprising layer from electrochemical degradation during the exposing. In yet another aspect, the invention includes an aluminum-comprising layer over or within a semiconductor wafer substrate and comprising a material having a lower reduction potential than aluminum.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: January 15, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Allen McTeer
  • Patent number: 6337257
    Abstract: Two contradictory problems of the reduction in the thickness of semiconductor chips or package parts including the semiconductor chips and the improvement in mechanical strength are solved. A semiconductor wafer where semiconductor elements are formed on a first surface thereof or semiconductor chips formed by dicing the semiconductor wafer are reduced in thickness by grinding the second surface opposite to the first surface, and grinding scratches formed by the grinding are removed to smooth the second surface. Since dicing scratches are formed on side surfaces of the semiconductor chips by dicing, the side surfaces are etched together with the second surface to remove the dicing scratches as well as the grinding scratches, thereby smoothing the second surface and the side surfaces.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: January 8, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kenji Toyosawa
  • Publication number: 20010036677
    Abstract: An identification indication is formed on a side surface of a semiconductor wafer, and thus even if various treatment processes are repeatedly conducted for forming a semiconductor circuit, or even by the wrapping treatment on the rear side of the wafer, the identification indication cannot disappear or become unclear so that the identification indication can be clearly recognized at least until the process for cutting the wafer into chips.
    Type: Application
    Filed: June 12, 2001
    Publication date: November 1, 2001
    Inventors: Hiroyuki Yano, Katsuya Okumura
  • Patent number: 6300250
    Abstract: A new method is provided to create metal bumps on a surface, metal contact pads have been provided in this surface. A layer of dielectric is deposited over a surface; an opening is created in the layer of dielectric that aligns with the contact pad. A barrier layer is deposited over the layer of dielectric including the inside of the opening; a seed layer is deposited over the barrier layer. The seed layer is selectively removed from above the layer of dielectric leaving the seed layer intact and deposited over the inside surfaces of the opening, the barrier layer is left intact over the layer of dielectric and inside the opening. Using Electrical Chemical Deposition (ECD) technology, the metal bump is now selectively grown thereby eliminating previously experienced disadvantages when creating metal bumps of decreased pitch and mask alignments and resolution.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: October 9, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Ming-Hsing Tsai
  • Publication number: 20010024877
    Abstract: The present invention provides exemplary cluster tool systems and methods for processing wafers, such as semiconductor wafers. One method includes providing a wafer having initial thickness variations between two wafer surfaces. The wafer is processed (Step 216) through a first module (300), with the first module having apparatus for performing a grinding process, a clean process and a metrology process, all preferably within a clean room environment (310). Wafer processing through the first module includes performing the grinding process, clean process and metrology process. The method further includes defining an edge profile on the wafer and processing (Step 222) the wafer through a second module (400).
    Type: Application
    Filed: March 15, 2001
    Publication date: September 27, 2001
    Inventors: Krishna Vepa, Duncan Dobson
  • Patent number: 6287942
    Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process the fully hermetic sealing of both sides and the edges of the semiconductor chip out the use of a separate package.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: September 11, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Salman Akram, Alan G. Wood
  • Patent number: 6284628
    Abstract: There is disclosed a method of recycling a delaminated wafer produced as a by-product in producing an SOI wafer according to a hydrogen ion delaminating method by reprocessing it for reuse as a silicon wafer, wherein at least polishing of the delaminated wafer for removing of a step in the peripheral part of the delaminated wafer and heat treatment in a reducing atmosphere containing hydrogen are conducted as the reprocessing. There are provided a method of appropriately reprocessing a delaminated wafer produced as a by-product in a hydrogen ion delaminating method to reuse it as a silicon wafer actually, and particularly, a method of reprocessing an expensive wafer such as an epitaxial wafer many times for reuse, to improve productivity of SOI wafer having a high quality SOI layer, and to reduce producing cost.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: September 4, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Susumu Kuwahara, Kiyoshi Mitani, Hiroji Aga, Masae Wada
  • Patent number: 6277501
    Abstract: The present invention has as an objective providing a silicon epi-wafer, and a manufacturing method therefor, which simplifies processing as much as possible in an attempt to lower the cost of an epi-wafer, and which is capable of manifesting a sufficient IG effect even in low-temperature device fabrication processing of under 1080° C. in an epi-wafer, and furthermore, in device processing, which enhances gettering capabilities for a variety of impurities in wafer device processing, without performing, following wafer slicing, any process from which an EG effect can be anticipated. As for the silicon single crystal, which is grown via the CZ method so as to make the oxygen concentration relatively high, and to intentionally make the carbon concentration high, outstanding gettering capabilities are manifested in the wafer itself, without performing EG processing.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: August 21, 2001
    Assignee: Sumitomo Metal Industries, Ltd.
    Inventor: Takashi Fujikawa
  • Patent number: 6268641
    Abstract: An identification indication is formed on a side surface of a semiconductor wafer, and thus even if various treatment processes are repeatedly conducted for forming a semiconductor circuit, or even by the wrapping treatment on the rear side of the wafer, the identification indication cannot disappear or become unclear so that the identification indication can be clearly recognized at least until the process for cutting the wafer into chips.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: July 31, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Yano, Katsuya Okumura
  • Patent number: 6265314
    Abstract: The present invention is directed to a method for manufacturing semiconductor devices. The method generally comprises forming a plurality of process layers on a wafer 14. The wafer has an edge region 20 with a number of defects 26 existing thereon. Thereafter, the method comprises removing all or a substantial portion of the defects 26 on the edge region 20 of the wafer 14.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: July 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hang Thi Yen Black, Edward E. Ehrichs
  • Publication number: 20010008801
    Abstract: A method and apparatus for lapping or polishing a semiconductor silicon single crystal wafer is provided for eliminating the transfer of waviness of a wafer cut by a wire saw apparatus, improving the quality of the wafer, realizing automated lapping or polishing processes, allowing for single crystal processing from a cassette to another cassette, and increasing the workability and labor productivity. A small amount of single-side lapping or single-side polishing is repeated alternately on the two surfaces of a semiconductor silicon single crystal wafer to get to a predetermined total lapping or polishing stock removal.
    Type: Application
    Filed: March 16, 1999
    Publication date: July 19, 2001
    Inventor: KOHEI TOYAMA
  • Patent number: 6261922
    Abstract: The invention includes polishing processes, methods of polishing materials, methods for slowing a rate of material removal of a polishing process, and methods of forming trench isolation regions. In one aspect, the invention includes a method comprising: a) forming a material over a surface of a substrate; b) providing a substantially non-porous polishing pad and a chemical composition proximate the material, the material being substantially wettable to the chemical composition, the substrate surface and substantially non-porous polishing pad being substantially non-wettable to the chemical composition; and c) polishing the material with the substantially non-porous polishing pad and the chemical composition.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: July 17, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Walker, Karl M. Robinson
  • Patent number: 6248667
    Abstract: A chemical mechanical polishing (CMP) method using a double polishing stopper by which it is possible to prevent a dishing phenomenon and a variation in the thickness of a polishing stopper, including the steps of stacking polishing stoppers to form the double polishing stopper on a semiconductor substrate, forming a trench, stacking an isolation layer, performing a first CMP process using a second polishing stopper, removing the second polishing stopper, and performing a second CMP process using a first polishing stopper. It is possible to remove the second polishing stopper by additionally interposing an etching stopper between the polishing stoppers which form the double polishing stopper.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: June 19, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-yup Kim, Chang-ki Hong
  • Patent number: 6221773
    Abstract: A method for processing semiconductor wafers, which provides planarized surface in a well controllable manner and with high accuracy by processing a film with uneven surface, formed over a semiconductor wafer, within the area of a working surface with a diameter larger than that of said semiconductor wafer by not more than two times, and by processing the film with a polishing liquid supplied from a supply unit disposed on a vertically arranged working surface is disclosed. Additionally, high quality dressing of the working surface can be easily performed by virtue of the smaller diameter of the working surface. Furthermore, the vertical arrangement of the working surface makes possible ready compatibility with semiconductor wafers of enlarged diameters.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: April 24, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Kan Yasui, Shigeo Moriyama, Katsuhiko Yamaguchi, Yoshio Homma
  • Patent number: 6218306
    Abstract: In the formation of metal vias, plugs or lines, a metal layer is deposited onto a non-planar non-metallic surface of a substrate. The metal layer is chemical mechanical polished with a first polishing pad until the metal layer is substantially planarized and a residual layer having a thickness about equal to the depth of potential microscratches, between about 200 and 1000 angstroms, remains over the non-metallic surface. The residual layer is chemical mechanical polished with a second, softer polishing pad until the non-metallic surface is exposed and the residual layer is removed.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: April 17, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Boris Fishkin, Kapila Wijekoon, Ronald Lin
  • Patent number: 6214734
    Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: April 10, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Subhas Bothra, Milind G. Weling
  • Patent number: 6150260
    Abstract: A new method of metal plug metallization utilizing a sacrificial layer as a CMP stop to protect the oxide layer from damage during CMP is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer covers the semiconductor device structures. A sacrificial titanium nitride layer is deposited overlying the insulating layer. An opening is etched through the sacrificial layer and the insulating layer to one of the semiconductor device structures. A glue layer is deposited conformally over the surface of the sacrificial layer and within the opening. A barrier layer is deposited overlying the glue layer. A metal layer is deposited overlying the barrier layer.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: November 21, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Sudipto Ranendra Roy
  • Patent number: 6110827
    Abstract: A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: August 29, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Sun-Chieh Chien, Der-Yuan Wu, Kun-Cho Chen
  • Patent number: 6110396
    Abstract: A slurry containing abrasive particles and a dual-valent rare earth ion or suspension of its colloidal hydroxide is especially useful for polishing surfaces, including those used in microelectronics. A suspension of a colloidal dual-valent rare earth hydroxide is especially useful for polishing silica.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventor: Maria Ronay
  • Patent number: 6096635
    Abstract: A method for creating via holes in a chip or a plurality of chips of a wafer is disclosed. The method is performed by using a pre-patterned transparent mask on the back of the chip or chips, and bombarding the chip(s) through the positioning holes on the transparent mask that correspond to the pre-formed pattern, with accelerated particles. According to this method, via holes can be created from the back of the chip(s) without interfering with the existing IC structure of the chip(s). The present method is highly efficient because a number of via holes can be formed simultaneously by using a large pre-pattered mask to cover the entire wafer. In addition, the present method is cost-effective because no precision apparatus is required.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: August 1, 2000
    Assignee: Microjet Technology Co., Ltd.
    Inventors: Tse-Chi Mou, Shiang Ching Cheng, Chin-Yi Chou, Arnold Chang-Mou Yang
  • Patent number: 6077785
    Abstract: The above objects and others are accomplished by a chemical mechanical polishing method and apparatus in accordance with the present invention. The apparatus includes a polishing pad having a polishing surface, and a wafer carrier for supporting a wafer disposed opposite to the polishing pad. The wafer carrier is positionable in a plane that is substantially parallel with the polishing surface, such that a surface of the wafer can be polished by contacting the polishing pad. The polishing surface and the wafer carrier are moved in parallel relative motion to mechanically abrade the wafer surface against the polishing surface in the presence of a polishing slurry. A slurry source containing the polishing slurry is connected to a slurry dispense line to dispense the slurry onto the polishing surface of the polishing pad.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: June 20, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Michael T. Andreas
  • Patent number: 6077720
    Abstract: A method for fabricating opto-electronic devices having a surface that includes a first mirror facet in a first semiconductor layer deposited on a wafer. The mirror facet is located in a first facet plane. In the method of the present invention, the wafer is divided along a first line to create a segment having the mirror facet located therein. The segment is fixed to a fixture that moves in relation to a dicing disk that has a first planar surface in which polishing grit is embedded. The segment is fixed to a mounting surface such that the first plane is aligned parallel to the first planar surface of the dicing disk. The dicing disk is caused to rotate while the first planar surface is in contact with the segment, but not in contact with the mounting surface, thereby polishing a surface of the segment.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: June 20, 2000
    Assignee: Agilent Technologies
    Inventors: Yoshifumi Yamaoka, Satoshi Watanabe, Norihide Yamada, Eric Marenger
  • Patent number: 6074895
    Abstract: A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the a surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O.sub.2 plasma or a microwave-generated Ar and N.sub.2 O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: June 13, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jean Dery, Frank D. Egitto, Luis J. Matienzo, Charles Ouellet, Luc Ouellet, David L. Questad, William J. Rudik, Son K. Tran
  • Patent number: 6068879
    Abstract: A process of inhibiting a corrosion of metal plugs formed in integrated circuits is described. The corrosion inhibiting process includes providing a partially fabricated integrated circuit surface including the metal plugs on a polishing pad to carry out chemical-mechanical polishing, introducing slurry including a corrosion inhibiting compound on the polishing pad in sufficient concentration to inhibit corrosion of the metal plugs of the partially fabricated integrated circuit surface, and polishing the partially fabricated integrated circuit surface.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: May 30, 2000
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Patent number: 6054362
    Abstract: A method of patterning a dummy layer is provided using the dark/clear ratio. First, the area of devices and the area of relevant devices are defined. The relevant devices are usually positioned around the devices. The devices, the relevant devices, and other regions are united according to the design rules to form a non-dummy pattern region. Then a dummy pattern region is defined. There are many dummy bulks in the dummy pattern region. Next, a known dark/clear ratio of the non-dummy pattern region is provided. A density of the dummy patterns is obtained from the known dark/clear ratio, the length of the dummy bulk, the width of the dummy bulk and a equation. The equation is as follows: the known dark/clear ratio=(the length-the parameter)(the width-the parameter)/[the length.times.the width-(the length-the parameter)(the width-the parameter)]. After obtaining the parameter, each dummy bulk is divided into two regions including a clear region and a dark region.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: April 25, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Andy Chuang
  • Patent number: 6054372
    Abstract: A stress-free wafer comprising a substrate formed of a semiconductor material having front side and back side planar and parallel surfaces and having a thickness ranging from 2 to 7 mils. The front side has electronic circuitry therein with exposed contact pads. The back side is ground and polished so that the wafer is substantially stress free and can withstand bending over a 2" radius without breaking or damaging.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: April 25, 2000
    Assignee: Aptek Industries, Inc.
    Inventors: H. Kelly Flesher, Albert P. Youmans
  • Patent number: 6048745
    Abstract: A method and apparatus for detecting scratches on a wafer surface. The method comprises the use of a monitor wafer which has a substrate, a first layer deposited on the substrate, and a second layer deposited on the first layer. The first and second layers have contrasting work functions such that when short wavelength light is directed on the monitor wafer, scratches through the second layer can be detected.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Francis Landers, Jyothi Singh
  • Patent number: 6037259
    Abstract: After identifying characters are written on the wafer surface 16 as a pattern of small holes 19 formed with a laser in the wafer I.D. stage of a semiconductor manufacturing process, the wafer surface in the region of the I.D. is polished to break loose deposits of silicon 20 that are left on the wafer surface and the region is then washed. The process prevents semiconductor material deposited on the wafer surface during the laser operation from later breaking off as hard particles that can scratch the surface of the wafer.
    Type: Grant
    Filed: May 11, 1998
    Date of Patent: March 14, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Bih-Tiao Lin, Fu-Liang Yang
  • Patent number: 6025262
    Abstract: A method of passivating an outer portion of a semiconductor wafer comprises: a) applying and patterning a metal layer to define conductive metal runners projecting atop the wafer, the conductive metal runners projecting outwardly from the wafer at given distances; b) applying an insulating dielectric layer atop the wafer to a thickness which is greater than the given distance of a furthest projecting metal runner; c) global planarizing the insulating dielectric layer to some point on the wafer which is elevationally above the underlying conductive metal runners; the preferred method is by chemical mechanical polishing; and d) applying a planar layer of an effective mechanical protection, chemical diffusion barrier and moisture barrier material atop the globally planarized layer of insulating dielectric.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: February 15, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Trung Tri Doan
  • Patent number: 6013564
    Abstract: In a method of manufacturing a semiconductor substrate, a first stage semiconductor substrate wafer is cut out from an ingot. Then, a chemical mechanical polishing process is performed to the first stage semiconductor substrate wafer to produce a second stage semiconductor substrate wafer respectively having mirror surfaces on front and rear surfaces of the second stage semiconductor substrate wafer. Subsequently, a third stage semiconductor substrate wafer is produced from the second stage semiconductor substrate wafer without performing an additional chemical mechanical polishing process, to have a blocking film on the rear surface and a mirror surface on the front surface. Finally, an epitaxial layer is grown on the front surface of the third stage semiconductor substrate wafer.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: January 11, 2000
    Assignee: NEC Corporation
    Inventor: Satoru Muramatsu
  • Patent number: 6008107
    Abstract: An integrated circuit device is fabricated upon a semi-conductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: December 28, 1999
    Assignee: National Semiconductor Corporation
    Inventors: John M. Pierce, Sung Tae Ahn
  • Patent number: 6004405
    Abstract: A wafer 1 has a chamfered edge 2 polished to specular glossiness, and a laser mark for indication of crystal orientation is put on the chamfered edge 2. Another laser mark 4 for indication of specification, production number, identification, etc. may be carved as a bar code on the chamfered edge 2. These marks 3, 4 are carved on the chamfered edge 2 by laser marking which does not put any harmful influences on the wafer 1.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: December 21, 1999
    Assignee: Super Silicon Crystal Research Institute Corp.
    Inventors: Hiroshi Oishi, Keiichiro Asakawa
  • Patent number: 5981301
    Abstract: A method for regenerating a used wafer or substrate by removing a functional coating film formed on the used wafer or substrate, comprising the steps of:(a) a step for sorting the used wafer or substrate according to the quality, structure or thickness of the functional coating film;(b) a step for removing the functional coating film, while in a state of holding the used wafer or substrate, (i) by lapping the objective face of the used wafer or substrate with a hard metal-bonded whetstone while applying an electrochemical in-process dressing, (ii) by polishing the objective face while dropping a fine-particle polishing slurry between a polishing plate provided with a pad and the functional coating film, or (iii) by electrolyzing the functional coating film on the objective face placed opposite to an electrode face in an electrolyte solution at a predetermined voltage;(c) a step for mechanically removing the functional coating film adhered to the end face at an adequate stage; and(d) a step for washing and dry
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: November 9, 1999
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Kazuo Muramatsu, Akihiro Kawai, Tsutomu Watanabe, Satoshi Shimamoto
  • Patent number: 5972802
    Abstract: A method of preventing edge stain in silicon wafers from the edge polishing step with an alkaline slurry, the method consisting of formation of an oxide layer by an ozone dipping step prior to edge polishing.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: October 26, 1999
    Assignee: SEH America, Inc.
    Inventors: Masami Nakano, Jim Woodling
  • Patent number: 5965459
    Abstract: A planarizing method involves a first polishing step in which a relatively hard, low compressibility pad removes excess material of a first layer and planarizes the first layer. Deep defects emanating from the polishing surface formed during the first polishing step are then enlarged and filled with a second layer. After filling, and optionally annealing, the second layer is planarized by polishing with a relatively soft and high compressibility pad or by anisotropic etching.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: October 12, 1999
    Assignee: International Business Machines Corporation
    Inventor: Klaus Dietrich Beyer
  • Patent number: 5964953
    Abstract: The present invention is directed to a process for removing aluminum contamination from the surface of an etched semiconductor wafer. The process is carried out by first lapping a semiconductor wafer in a lapping slurry containing aluminum, etching the wafer, and finally immersing the wafer in an aqueous bath, the bath comprising an alkaline component and a surfactant.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: October 12, 1999
    Assignee: MEMC Electronics Materials, Inc.
    Inventor: Gianpaolo Mettifogo
  • Patent number: 5966614
    Abstract: Trench isolation methods for integrated circuit substrates may be simplified by eliminating the steps of forming a silicon nitride layer, etching the silicon nitride layer and removing the silicon nitride layer. In particular, a silicon nitride-free mask pattern, such as a photoresist mask pattern, may be formed on a silicon nitride-free integrated circuit substrate. The silicon nitride-free integrated circuit substrate is etched through the silicon nitride-free mask pattern to form a trench in the substrate. An insulating layer is formed in the trench and is chemical-mechanical polished to form a trench isolating layer. By eliminating the silicon nitride layer, simplified processing and improved performance may be obtained.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: October 12, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tai-su Park, Ho-kyu Kang
  • Patent number: 5963821
    Abstract: This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution. Both the front and back sides of the etched wafer are polished using a double sided polishing apparatus so that the front side is a mirror surface and an unevenness remains on the back side to distinguish the front and back sides, thereof. The polished wafer is cleaned.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: October 5, 1999
    Assignee: Komatsu Electronic Metal Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 5945348
    Abstract: A region is formed in a semiconductor substrate and extends beyond the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount to improve the aspect ratio of the trench, to improve the cross-sectional profile of the trench, or both. The thickness of the third strip is reduced a second amount. The second amount may be smaller than the first amount.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: August 31, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Guy Blalock, Scott Meikle, Sung Kim, Kirk Prall
  • Patent number: 5932048
    Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: August 3, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroshi Furukawa, Hirotaka Kato, Hiroaki Yamamoto, Kazuaki Fujimoto
  • Patent number: 5920764
    Abstract: A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut.RTM. process. Because of the use of the variation on the Smart-Cut.RTM. process, diffusion regions are removed without significantly affecting the specifications of the semiconductor wafer. Therefore, a defective or rejected wafer can be restored to near original condition for use in semiconductor manufacturing.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: July 6, 1999
    Assignee: International Business Machines Corporation
    Inventors: David R. Hanson, Hance H. Huston, III, Kris V. Srikrishnan
  • Patent number: 5903058
    Abstract: The present invention relates to an improved method for forming UBM pads and solder bump connections for a flip chip which eliminates at least one mask step required in standard UBM pad forming processes. The method also includes repatterning bond pad locations.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: May 11, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 5895550
    Abstract: The above objects and others are accomplished by a chemical mechanical polishing method and apparatus in accordance with the present invention. The apparatus includes a polishing pad having a polishing surface, and a wafer carrier for supporting a wafer disposed opposite to the polishing pad. The wafer carrier is positionable in a plane that is substantially parallel with the polishing surface, such that a surface of the wafer can be polished by contacting the polishing pad. The polishing surface and the wafer carrier are moved in parallel relative motion to mechanically abrade the wafer surface against the polishing surface in the presence of a polishing slurry. A slurry source containing the polishing slurry is connected to a slurry dispense line to dispense the slurry onto the polishing surface of the polishing pad.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: April 20, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Michael T. Andreas
  • Patent number: 5882539
    Abstract: A wafer processing method which can polish the chamfered portion of a wafer quickly, is disclosed. The processing method comprises the steps of: chamfering a peripheral portion of a wafer obtained by slicing an ingot, by grinding; lapping the wafer; etching the chamfered or lapped wafer; thereafter honing the entirety of the chamfered peripheral portion of the wafer by using a grinding stone while applying a predetermined load to the grinding stone; and thereafter polishing the entirety of the chamfered peripheral portion and the front and rear surfaces of the wafer.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: March 16, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumihiko Hasegawa, Yasuyoshi Kuroda, Masayuki Yamada
  • Patent number: 5876508
    Abstract: A method for effectively cleaning the slurry remnants left on a polishing pad after the completion of a chemical mechanical polish (CMP) process is provided. This method is able to substantially thoroughly clean away all of the slurry remnants left on the polishing pad. In the method of the invention, the first step is to prepare a cleaning agent which is a mixture of H.sub.2 O.sub.2, deionized water, an acid solution, and an alkaline solution mixed to a predetermined ratio. The cleaning agent is subsequently directed to a nozzle formed in the pad dresser. This allows the cleaning agent to be jetted forcibly onto the slurry remnants on the polishing pad so as to clean the slurry remnants away from the polishing pad. The cleaning agent can be provided with predetermined ratios for various kinds of slurries so that the cleaning agent can be adjusted to be either acid or alkaline in nature.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: March 2, 1999
    Assignee: United Microelectronics Corporation
    Inventors: Kun-Lin Wu, Chien-Hsien Lai, Horng-Bor Lu, Jenn-Tarng Lin
  • Patent number: 5868896
    Abstract: An apparatus and method for uniformly planarizing a surface of a semiconductor wafer and accurately stopping CMP processing at a desired endpoint. In one embodiment, a planarizing machine has a platen mounted to a support structure, an underpad attached to the platen, a polishing pad attached to the underpad, and a wafer carrier assembly. The wafer carrier assembly has a chuck with a mounting cavity in which the wafer may be mounted, and the wafer carrier assembly moves the chuck to engage a front face of the wafer with the planarizing surface of the polishing pad. The chuck and/or the platen moves with respect to the other to impart relative motion between the wafer and the polishing pad. The planarizing machine also includes a pressure sensor positioned to measure the pressure at an area of the wafer as the platen and the chuck move with respect to each other and while the wafer engages the planarizing surface of the polishing pad.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: February 9, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Karl M. Robinson, Chris Chang Yu
  • Patent number: 5773360
    Abstract: Chemical-mechanical polishing is followed with a scrubbing procedure for the removal of any particulate contaminants. Scrubbing is succeeded by a plasma etching step, using a parallel electrode plasma etcher, a downstream plasma etcher, or similar apparatus. Plasma etching is performed for about 30 seconds using CF.sub.4 as the etching gas, so that about 300 Angstroms of the post CMP surface is removed. This results in the almost total elimination of residual mobile ions from the polished surface without the introduction of microgrooves and similar blemishes as is often the case when HF is used for this purpose.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: June 30, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Long Chang, Chen-Hua Yu, Syun-Ming Jang
  • Patent number: 5750434
    Abstract: A silicon carbide substrate is dry-polished using chromium oxide Cr.sub.2 O.sub.3, ion oxide Fe.sub.2 O.sub.3, or cerium oxide CeO.sub.2 to obtain a good polished surface free of mechanical defects and with less crystal distortion. Films are then formed on the surface to create an improved electronic device.
    Type: Grant
    Filed: April 18, 1995
    Date of Patent: May 12, 1998
    Assignee: Fuji Electric Co. Ltd.
    Inventors: Tatsuo Urushidani, Shinji Ogino