Amorphous Semiconductor Patents (Class 438/96)
-
Patent number: 8927857Abstract: A method of producing a photovoltaic device includes providing a stretchable substrate for the photovoltaic device; and stretching the substrate to produce a stretched substrate. The method further includes depositing a structure comprising hydrogenated amorphous silicon onto the stretched substrate; and subjecting the deposited hydrogenated amorphous silicon structure and the stretched substrate to a compressive force to form a compressively strained photovoltaic device.Type: GrantFiled: February 28, 2011Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Ahmed Abou-Kandil, Nasser Afify, Wanda Andreoni, Alessandro Curioni, Augustin J. Hong, Jeehwan Kim, Petr Khomyakov, Devendra K. Sadana
-
Publication number: 20150000732Abstract: A method for fabricating a solar cell includes the steps of providing a substrate, forming a transparent conductive layer on a surface of the substrate, forming a plurality of photoresist patterns on the transparent conductive layer, forming a dielectric layer on the photoresist patterns and the transparent conductive layer, in which a part of a sidewall of the photoresist pattern is exposed from the dielectric layer, removing the photoresist patterns and a part of the dielectric layer covering the photoresist pattern so that a plurality of openings are defined in the remaining part of the dielectric layer, and forming plural electrodes in the openings respectively. A solar cell fabricated by the method is also disclosed.Type: ApplicationFiled: June 25, 2014Publication date: January 1, 2015Inventor: Po-Chuan YANG
-
Patent number: 8921149Abstract: A first species selectively dopes a workpiece to form a first doped region. In one embodiment, a selective implant is performed using a mask with apertures. A soft mask is applied to the first doped region. A second species is implanted into the workpiece to form a second implanted region. The soft mask blocks a portion of the second species. Then the soft mask is removed. The first species and second species may be opposite conductivities such that one is p-type and the other is n-type.Type: GrantFiled: February 24, 2011Date of Patent: December 30, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas P. T. Bateman, William T. Weaver
-
Patent number: 8921148Abstract: The present invention provides strategies for improving the adhesion among two or more of transparent conducting oxides, electrically conductive grid materials, and dielectric barrier layers. As a consequence, these strategies are particularly useful in the fabrication of heterojunction photovoltaic devices such as chalcogenide-based solar cells. When the barrier is formed and then the grid is applied to vias in the barrier, the structure has improved moisture barrier resistance as compared to where the barrier is formed over or around the grid. Adhesion is improved to such a degree that grid materials and dielectric barrier materials can cooperate to provide a hermetic seal over devices to protect against damage induced by environmental conditions, including damage due to water intrusion. This allows the collection grids to be at least partially exposed above the dielectric barrier, making it easy to make electronic connection to the devices.Type: GrantFiled: January 12, 2011Date of Patent: December 30, 2014Assignee: Dow Global Technologies LLCInventors: Paul R. Elowe, Marty W. DeGroot, Michael E. Mills, Matt A. Stempki
-
Publication number: 20140373919Abstract: A photovoltaic cell including a semiconductor substrate of a first conductivity type provided with a main surface, a first layer made from amorphous semiconductor material of first conductivity type in contact with the main surface of the substrate, a first electric contact formed on the first amorphous layer, a second layer of amorphous semiconductor material of a second conductivity type in contact with the main surface of the substrate, a second electric contact formed on the second amorphous layer and an electrically insulating layer, a cell wherein the electrically insulating layer is formed completely on the first amorphous layer and the first and second contacts extend on the electrically insulating layer.Type: ApplicationFiled: January 3, 2013Publication date: December 25, 2014Inventors: Thibaut Desrues, Sylvain De Vecchi, Florent Souche
-
Patent number: 8916772Abstract: A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.Type: GrantFiled: August 8, 2013Date of Patent: December 23, 2014Assignee: Solexel, Inc.Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang
-
Publication number: 20140360571Abstract: A manufacturing method of a solar cell is discussed. The manufacturing method of the solar cell includes forming a tunneling layer on one surface of a semiconductor substrate, forming a semiconductor layer on the tunneling layer, doping the semiconductor layer with a first conductive dopant and a second conductive dopant to form a first conductive semiconductor layer and a second conductive semiconductor layer, and diffusing hydrogen into the first and second conductive semiconductor layers to hydrogenate the first and second conductive semiconductor layers.Type: ApplicationFiled: June 5, 2014Publication date: December 11, 2014Inventors: Kwangsun JI, Seungjik LEE, Sehwon AHN
-
Patent number: 8906734Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.Type: GrantFiled: October 22, 2012Date of Patent: December 9, 2014Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
-
Patent number: 8900915Abstract: Epitaxial structures, methods of making epitaxial structures, and devices incorporating such epitaxial structures are disclosed. The methods and the structures employ a liquid-phase Group IVA semiconductor element precursor ink (e.g., including a cyclo- and/or polysilane) and have a relatively good film quality (e.g., texture, density and/or purity). The Group IVA semiconductor element precursor ink forms an epitaxial film or feature when deposited on a (poly)crystalline substrate surface and heated sufficiently for the Group IVA semiconductor precursor film or feature to adopt the (poly)crystalline structure of the substrate surface. Devices incorporating a selective emitter that includes the present epitaxial structure may exhibit improved power conversion efficiency relative to a device having a selective emitter made without such a structure due to the improved film quality and/or the perfect interface formed in regions between the epitaxial film and contacts formed on the film.Type: GrantFiled: April 6, 2011Date of Patent: December 2, 2014Assignee: Thin Film Electronics ASAInventors: Joerg Rockenberger, Fabio Zürcher, Mao Takashima
-
Publication number: 20140345673Abstract: Photovoltaic sub-cell interconnect systems and methods are provided. In one embodiment, a photovoltaic device comprises a thin film stack of layers deposited upon a substrate, wherein the thin film stack layers are subdivided into a plurality of sub-cells interconnected in series by a plurality of electrical interconnection structures; and wherein the plurality of electrical interconnection structures each comprise no more than two scribes that penetrate into the thin film stack layers.Type: ApplicationFiled: May 21, 2014Publication date: November 27, 2014Applicant: Alliance for Sustainable Energy, LLCInventors: Marinus Franciscus Antonius Maria van Hest, Heather Anne Swinger Platt
-
Publication number: 20140345688Abstract: A silicon solar cell has doped amorphous silicon contacts formed on a tunnel silicon oxide layer on a surface of a silicon substrate. High temperature processing is unnecessary in fabricating the solar cell.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Inventor: Peter John COUSINS
-
Publication number: 20140349441Abstract: One embodiment of the present invention provides a solar cell. The solar cell includes a photovoltaic structure, a transparent-conductive-oxide (TCO) layer situated above the photovoltaic structure, and a front-side metal grid situated above the TCO layer. The TCO layer is in contact with the front surface of the photovoltaic structure. The metal grid includes at least one of: Cu and Ni.Type: ApplicationFiled: August 7, 2014Publication date: November 27, 2014Inventors: Jianming Fu, Zheng Xu, Chentao Yu, Jiunn Benjamin Heng
-
Patent number: 8895842Abstract: A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon containing layer formed on the second TCO layer. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first p-i-n junction on the second TCO layer.Type: GrantFiled: June 9, 2009Date of Patent: November 25, 2014Assignee: Applied Materials, Inc.Inventors: Shuran Sheng, Yong Kee Chae, Stefan Klein, Amir Al-Bayati, Bhaskar Kumar
-
Patent number: 8889456Abstract: A method for fabricating a photovoltaic device includes performing a gettering process in a processing chamber which restricts formation of a layer of gettering materials on a substrate and forming a solder layer on the substrate. The solder layer is annealed to form uniformly distributed solder dots which grow on the substrate. The substrate is etched using the solder dots to protect portions of the substrate and form cones in the substrate such that the cones provide a three-dimensional radiation absorbing structure for the photovoltaic device.Type: GrantFiled: August 29, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Augustin J. Hong, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana
-
Patent number: 8883608Abstract: An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening.Type: GrantFiled: May 15, 2013Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Kang, Tae-Gon Kim, Han-Mei Choi, Eun-Young Jo
-
Patent number: 8865588Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.Type: GrantFiled: December 24, 2013Date of Patent: October 21, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Takeshi Kagawa
-
Patent number: 8853524Abstract: A solar cell and method of fabrication are disclosed. In one embodiment of the present invention, the method comprises depositing a first doped amorphous silicon layer on a first surface of a silicon substrate, depositing a second doped amorphous silicon layer on the first surface of the silicon substrate. The second doped amorphous silicon layer is doped oppositely from the first doped amorphous silicon layer. An anneal is performed to transform the first doped amorphous silicon layer and second doped amorphous silicon layer to crystalline silicon layers.Type: GrantFiled: October 5, 2011Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventor: Harold John Hovel
-
Patent number: 8853521Abstract: The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through.Type: GrantFiled: July 28, 2011Date of Patent: October 7, 2014Assignee: Solexel, Inc.Inventors: Mehrdad Moslehi, David Xuan-Qi Wang
-
Patent number: 8847223Abstract: A method of forming a photosensitive pattern on a substrate with a photosensitive layer disposed thereon may include moving at least one of the substrate and a set of micro-mirrors in a first direction, the set of micro-mirrors being disposed above the substrate and being arranged as an array, the array having a first edge extending in a second direction, the second direction being at an acute angle with respect to the first direction. The method may also include selectively turning on one or more micro-mirrors of the set of micro-mirrors according to a position of the set of micro-mirrors relative to the photosensitive layer, thereby irradiating one or more spot beams on the photosensitive layer. The photosensitive layer exposed by the spot beams is developed to form a photosensitive pattern having an edge portion extending in a third direction crossing the first and second directions.Type: GrantFiled: February 28, 2012Date of Patent: September 30, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jung-In Park, Su-Yeon Sim, Sang-Hyun Yun, Cha-Dong Kim, Hi-Kuk Lee
-
Patent number: 8841161Abstract: The invention provides for a semiconductor wafer with a metal support element suitable for the formation of a flexible or sag tolerant photovoltaic cell. A method for forming a photovoltaic cell may comprise providing a semiconductor wafer have a thickness greater than 150 ?m, the wafer having a first surface and a second surface opposite the first and etching the semiconductor wafer a first time so that the first etching reduces the thickness of the semiconductor wafer to less than 150 ?m. After the wafer has been etched a first time, a metal support element may be constructed on or over the first surface; and a photovoltaic cell may be fabricated, wherein the semiconductor wafer comprises the base of the photovoltaic cell.Type: GrantFiled: February 5, 2012Date of Patent: September 23, 2014Assignee: GTAT.CorporationInventors: Venkatesan Murali, Gopal Prabhu, Thomas Edward Dinan, Jr., Orion Leland
-
Patent number: 8828788Abstract: The electrode of a phase change memory may be formed with a mixture of metal and a non-metal, the electrode having less nitrogen atoms than metal atoms. Thus, in some embodiments, at least a portion of the electrode has less nitrogen than would be the case in a metal nitride. The mixture can include metal and nitrogen or metal and silicon, as two examples. Such material may have good adherence to chalcogenide with lower reactivity than may be the case with metal nitrides.Type: GrantFiled: May 11, 2010Date of Patent: September 9, 2014Assignee: Micron Technology, Inc.Inventors: Davide Erbetta, Camillo Bresolin, Andrea Gotti
-
Patent number: 8828787Abstract: Processes for making a thin film solar cell on a substrate by providing a substrate coated with an electrical contact layer, depositing an ink onto the contact layer of the substrate, wherein the ink contains an alkali ion source compound suspended or dissolved in a carrier along with photovoltaic absorber precursor compounds, and heating the substrate. The alkali ion source compound can be MalkMB(ER)4 or Malk(ER). The processes can be used for CIS or CIGS.Type: GrantFiled: September 15, 2011Date of Patent: September 9, 2014Assignee: Precursor Energetics, Inc.Inventors: Kyle L. Fujdala, Zhongliang Zhu, David Padowitz, Paul R. Markoff Johnson, Wayne A. Chomitz, Matthew C. Kuchta
-
Patent number: 8815634Abstract: Dark currents within a photosensitive device are reduced through improved implantation of a species during its fabrication. Dark currents can be caused by defects in the photo-diode device, caused during the annealing, implanting or other processing steps used during fabrication. By amorphizing the workpiece in the photo-diode region, the number of defects can be reduced thereby reducing this cause of dark current. Dark current is also caused by stress induced by an adjacent STI, where the stress caused by the liner and fill material exacerbate defects in the workpiece. By amorphizing the sidewalls and bottom surface of the trench, defects created during the etching process can be reduced. This reduction in defects also decreases dark current in the photosensitive device.Type: GrantFiled: October 28, 2009Date of Patent: August 26, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak Ramappa, Dennis Rodier
-
Patent number: 8815635Abstract: A photoelectric conversion device has a structure that includes a first amorphous silicon layer and a second amorphous silicon layer that are in contact with a single crystalline silicon substrate, and a first microcrystalline silicon layer with one conductivity type and a second microcrystalline silicon layer with a conductivity type that is opposite the one conductivity type that are in contact with the first and second amorphous silicon layers, respectively. The first and second microcrystalline silicon layers are formed using a plasma CVD apparatus that is suitable for high pressure film formation conditions.Type: GrantFiled: October 31, 2011Date of Patent: August 26, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Fumito Isaka
-
Publication number: 20140231804Abstract: A sensor and its fabrication method are provided, the sensor comprises: a base substrate (32), a group of gate lines (30) and a group of data lines (31) arranged as crossing each other, and a plurality of sensing elements arranged in an array and defined by the group of gate lines (30) and the group of data lines (31), each sensing element comprising a TFT device and a photodiode sensing device, wherein a channel region of the TFT device is inverted and the source and drain electrodes (33, 34) are positioned between the active layer (36) and the gate electrode (38). The sensor reduces the number of mask as well as the production cost and simplifies the production process, thereby significantly improves the production capacity and the defect-free rate.Type: ApplicationFiled: December 3, 2012Publication date: August 21, 2014Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Changjiang Yan, Zhenyu Xie, Shaoying Xu, Tiansheng Li
-
Patent number: 8802484Abstract: A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.Type: GrantFiled: January 22, 2013Date of Patent: August 12, 2014Assignee: GlobalFoundries Singapore Pte. Ltd.Inventors: Purakh Raj Verma, Guowei Zhang, Kah Wee Ang
-
Patent number: 8803119Abstract: A technique capable of improving performances of a semiconductor memory device provided with a recording film having a super lattice structure is provided. The semiconductor memory device records information by changing an electric resistance of a recording film by use of a change in an atomic arrangement of the recording film. Moreover, the recording film is provided with a stacked layer portion in which a first crystal layer and a second crystal layer made of chalcogen compounds having respectively different compositions are stacked, an orientation layer that enhances an orientation of the stacked layer portion, and an adhesive layer that improves the flatness of the orientation layer.Type: GrantFiled: February 22, 2013Date of Patent: August 12, 2014Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Takahiro Morikawa, Toshimichi Shintani
-
Patent number: 8802485Abstract: In the frame of manufacturing a photovoltaic cell a layer (3) of silicon compound is deposited on a structure (1). The yet uncovered surface (3a) is treated in a predetermined oxygen (O2) containing atmosphere which additionally contains a dopant (D). Thereby, the silicon compound layer is oxidized and doped in a thin surface area (5).Type: GrantFiled: September 7, 2009Date of Patent: August 12, 2014Assignee: Tel Solar AGInventors: Johannes Meier, Markus Bronner, Markus Kupich, Tobias Roschek, Hanno Goldbach
-
Patent number: 8785233Abstract: Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer.Type: GrantFiled: December 19, 2012Date of Patent: July 22, 2014Assignee: SunPower CorporationInventors: Paul Loscutoff, David D. Smith, Michael Morse, Ann Waldhauer, Taeseok Kim, Steven Edward Molesa
-
Patent number: 8778724Abstract: A thin film solar cell and a method fabricating thin film solar cells on flexible substrates. The method includes including providing a flexible polymeric substrate, depositing a photovoltaic precursor on a surface of the substrate, such as CdTe, ZrTe, CdZnTe, CdSe or Cu(In,Ga)Se2, and exposing the photovoltaic precursor to at least one 0.5 microsecond to 10 second pulse of predominately infrared light emitted from a light source having a power output of about 20,000 W/cm2 or less to thermally convert the precursor into a crystalline photovoltaic material having a photovoltaic efficiency of greater than one percent, the conversion being carried out without substantial damage to the substrate.Type: GrantFiled: September 24, 2010Date of Patent: July 15, 2014Assignee: UT-Battelle, LLCInventors: Craig A. Blue, Art Clemens, Chad E. Duty, David C. Harper, Ronald D. Ott, John D. Rivard, Christopher S. Murray, Susan L. Murray, Andre R. Klein
-
Patent number: 8772075Abstract: A display region and a light sensing region are defined in each pixel region of the OLED touch panel of the present invention. The readout thin film transistor of the light sensing region is formed by the same processes with the drive thin film transistor of the display region. The top and bottom electrodes of the optical sensor are formed by the same processes with the top and bottom electrodes of the OLED. Accordingly, the present invention can just add a step of forming the patterned sensing dielectric layer to the processes of forming an OLED panel to integrate the optical sensor into the pixel region of the OLED panel. Thus, an OLED touch panel is formed.Type: GrantFiled: March 4, 2010Date of Patent: July 8, 2014Assignee: AU Optronics Corp.Inventors: An-Thung Cho, Jung-Yen Huang, Chia-Tien Peng, Chun-Hsiun Chen, Wei-Ming Huang
-
Patent number: 8766090Abstract: The present invention relates to cost effective methods for metallization and or metallization and interconnection of high efficiency silicon based back-contacted back-junction solar panels and solar panels thereof having a multiplicity of alternating rectangular emitter- and base regions on the back-side of each cell, each with rectangular metallic electric finger conductor above and running in parallel with the corresponding emitter- and base region, a first insulation layer in-between the wafer and finger conductors, and a second insulation layer in between the finger conductors and cell interconnections.Type: GrantFiled: September 28, 2012Date of Patent: July 1, 2014Assignee: Rec Solar Pte. Ltd.Inventors: Richard Hamilton Sewell, Alan Francis Lyon, Andreas Bentzen
-
Publication number: 20140174517Abstract: A solar cell includes a first photoelectric conversion unit based on crystalline semiconductor, a second photoelectric conversion unit on the first photoelectric conversion unit and including a plurality of conversion portions based on amorphous semiconductor, a bonding layer disposed between the first and second photoelectric conversion units to connect the first photoelectric conversion unit to the second photoelectric conversion unit, and electrodes electrically connected respectively to the first and second photoelectric conversion units.Type: ApplicationFiled: November 13, 2013Publication date: June 26, 2014Applicant: LG ELECTRONICS INC.Inventors: Soohyun KIM, Heonmin LEE, Hyun LEE, Jinwon CHUNG
-
Patent number: 8759928Abstract: A system and method for reducing cross-talk in complementary metal oxide semiconductor back side illuminated image sensors is provided. An embodiment comprises forming a grid around the pixel regions on an opposite side of the substrate than metallization layers. The grid may be formed of a material such as tungsten with a (110)-rich crystalline orientation. This orientation helps prevents defects that can occur during patterning of the grid.Type: GrantFiled: April 4, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Chi-Cheng Hung, Jun-Nan Nian, Chih-Chung Chang
-
Publication number: 20140170806Abstract: Methods are used to develop and evaluate new processes for cleaning and texturing substrates and layers used in HJCS solar cells. In some embodiments, methods are used to develop and evaluate new processes for the deposition of resistive metal oxide interface layers that are formed between the TCO layers and the a-Si:H layers. The resistive metal oxide interface layers form good ohmic contact to the a-Si:H layers. In some embodiments, methods are used to develop and evaluate new processes for the deposition of amorphous TCO layers. The amorphous TCO layers allow improved control over the layer thickness and morphology. In some embodiments, methods are used to develop and evaluate new processes for the deposition of anti-reflection coating materials. The anti-reflection coating materials are selected to decrease the reflectivity of the solar cell and maintain the high conductivity of the TCO materials.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: INTERMOLECULAR, INC.Inventors: Jeroen Van Duren, Minh Huu Le
-
Patent number: 8748296Abstract: A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.Type: GrantFiled: June 29, 2011Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Devendra K. Sadana, Davood Shahrjerdi, Norma E. Sosa Cortes
-
Patent number: 8742412Abstract: A thin film transistor includes a gate electrode, a gate insulation layer, a channel layer, a source electrode, and a drain electrode formed on a substrate, in which: the channel layer contains indium, germanium, and oxygen; and the channel layer has a compositional ratio expressed by In/(In+Ge) of 0.5 or more and 0.97 or less.Type: GrantFiled: January 30, 2009Date of Patent: June 3, 2014Assignee: Canon Kabushiki KaishaInventors: Amita Goyal, Naho Itagaki, Tatsuya Iwasaki
-
Patent number: 8735212Abstract: A silicon solar cell is manufactured by providing a carrier plate, and by applying a first contact pattern to the carrier plate. The first contact pattern includes a set of first laminar contacts. The silicon solar cell is further manufactured by applying a multitude of silicon slices to the first contact pattern, and by applying a second contact pattern to the multitude of silicon slices. Each first laminar contact of the set of first laminar contacts is in spatial laminar contact with maximally two silicon slices. The second contact pattern includes a set of second laminar contacts. Each second laminar contact of the set of second laminar contacts is in spatial laminar contact with maximally two silicon slices.Type: GrantFiled: January 13, 2009Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Rainer Klaus Krause, Gerd Pfeiffer, Hans-Juergen Eickelmann, Thorsten Muehge
-
Patent number: 8734583Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.Type: GrantFiled: April 4, 2006Date of Patent: May 27, 2014Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
-
Patent number: 8735715Abstract: Disclosed is a photovoltaic device that comprises: a first electrode including a transparent conductive oxide layer; a first unit cell being placed on the first electrode; a second unit cell being placed on the first unit cell; and a second electrode being placed on the second unit cell, wherein the intrinsic semiconductor layer of the first unit cell includes hydrogenated amorphous silicon or hydrogenated amorphous silicon based material, wherein an intrinsic semiconductor layer of the second unit cell includes hydrogenated microcrystalline silicon or hydrogenated microcrystalline silicon based material, and wherein a ratio of a root mean square roughness to an average pitch of a texturing structure formed on the surface of the first electrode is equal to or more than 0.05 and equal to or less than 0.13.Type: GrantFiled: January 9, 2011Date of Patent: May 27, 2014Assignee: Intellectual Discovery Co., Ltd.Inventor: Seung-Yeop Myong
-
Patent number: 8735213Abstract: A minute electrode, a photoelectric conversion device including the minute electrode, and manufacturing methods thereof are provided. A plurality of parallel groove portions and a region sandwiched between the groove portions are formed in a substrate, and a conductive resin is supplied to the groove portions and the region and is fixed, whereby the groove portions are filled with the conductive resin and the region is covered with the conductive resin. The supplied conductive resin is not expanded outward, and the electrode with a designed width can be formed. Part of the electrode is formed over the region sandwiched between the groove portions, thus, the area of a cross section in the short axis direction can be large, and a low resistance in the long axis direction can be obtained.Type: GrantFiled: December 14, 2011Date of Patent: May 27, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuji Oda, Takashi Hirose, Koichiro Tanaka, Sho Kato, Emi Koezuka
-
Patent number: 8716596Abstract: A silicon solar cell having a silicon substrate includes p-type and n-type emitters on a surface of the substrate, the emitters being doped nano-particles of silicon. To reduce high interface recombination at the substrate surface, the nano-particle emitters are preferably formed over a thin interfacial tunnel oxide layer on the surface of the substrate.Type: GrantFiled: February 3, 2010Date of Patent: May 6, 2014Assignee: SunPower CorporationInventor: Richard M. Swanson
-
Publication number: 20140116501Abstract: A photovoltaic cell may include a hydrogenated amorphous silicon layer including a n-type doped region and a p-type doped region. The n-type doped region may be separated from the p-type doped region by an intrinsic region. The photovoltaic cell may include a front transparent electrode connected to the n-type doped region, and a rear electrode connected to the p-type doped region. The efficiency may be optimized for indoor lighting values by tuning the value of the H2/SiH4 ratio of the hydrogenated amorphous silicon layer.Type: ApplicationFiled: October 16, 2013Publication date: May 1, 2014Applicant: STMICROELECTRONICS S.r.I.Inventors: Cosimo GERARDI, Cristina TRINGALI, Sebastiano RAVESI, Marina FOTI, NoemiGraziana SPARTA', Corrado ACCARDI, Stella LOVERSO
-
Patent number: 8704083Abstract: In a thin film photoelectric conversion deice fabricated by addition of a catalyst element with the use of a solid phase growth method, defects such as a short circuit or leakage of current are suppressed. A catalyst material which promotes crystallization of silicon is selectively added to a second silicon semiconductor layer formed over a first silicon semiconductor layer having one conductivity type, the second silicon semiconductor layer is partly crystallized by a heat treatment, a third silicon semiconductor layer having a conductivity type opposite to the one conductivity type is stacked, and element isolation is performed at a region in the second silicon semiconductor layer to which a catalyst material is not added, so that a left catalyst material is prevented from being diffused again, and defects such as a short circuit or leakage of current are suppressed.Type: GrantFiled: February 8, 2011Date of Patent: April 22, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kazuo Nishi
-
Patent number: 8703528Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.Type: GrantFiled: April 12, 2012Date of Patent: April 22, 2014Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Michel Marty, François Roy, Jens Prima
-
Patent number: 8697559Abstract: One method of implanting a workpiece involves implanting the workpiece with an n-type dopant in a first region with center and a periphery. The workpiece also is implanted with a p-type dopant in a second region complementary to the first region. This second region also has a center and a periphery. The periphery of the first region and the periphery of the second region at least partially overlap. A dose at the periphery of the first region or second region is less than a dose at the center of the first region or second region. The region of overlap may function as a junction where charge carriers cannot pass.Type: GrantFiled: July 7, 2011Date of Patent: April 15, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas P. T. Bateman, Peter L. Kurunczi, Benjamin B. Riordon, John W. Graff
-
Publication number: 20140096821Abstract: A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings. The semiconductor substrate and the doped layer have a first doping type. One of the doped polysilicon layer and the doping area has a second doping type, and the other one of the doped polysilicon layer and the doping area has the first doping type which is opposite to the second doping type.Type: ApplicationFiled: April 10, 2013Publication date: April 10, 2014Applicant: AU Optronics Corp.Inventors: Peng Chen, Shuo-Wei Liang
-
Publication number: 20140096823Abstract: One embodiment of the present invention provides a solar cell. The solar cell includes a photovoltaic structure and a front-side metal grid situated above the photovoltaic structure. The front-side metal grid also includes one or more electroplated metal layers. The front-side metal grid includes one or more finger lines, and each end of a respective finger line is coupled to a corresponding end of an adjacent finger line via an additional metal line, thus ensuring that the respective finger line has no open end.Type: ApplicationFiled: October 3, 2013Publication date: April 10, 2014Applicant: Silevo, Inc.Inventors: Jianming Fu, Jiunn Benjamin Heng, Christopher J. Beitel, Zheng Xu
-
Publication number: 20140087513Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.Type: ApplicationFiled: October 22, 2012Publication date: March 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: TZE-CHIANG CHEN, BAHMAN HEKMATSHOARTABARI, DEVENDRA K. SADANA, DAVOOD SHAHRJERDI
-
Patent number: 8679892Abstract: The present invention relates to a method for manufacturing silicon thin-film solar cells, including: providing a substrate; forming a first electrode on the substrate; forming a first doped semiconductor layer on the first electrode by chemical vapor deposition; forming an intrinsic layer on the first doped semiconductor layer by chemical vapor deposition, where the intrinsic layer includes a plurality of amorphous/nanocrystalline silicon layers, and the intrinsic layer has various energy bandgaps formed by varying average grain sizes of the amorphous/nanocrystalline silicon layers; forming a second doped semiconductor layer on the intrinsic layer by chemical vapor deposition, where one of the first doped semiconductor layer and the second doped semiconductor layer is a p-type amorphous silicon layer and the other is an n-type amorphous/nano-microcrystalline silicon layer; and forming a second electrode on the second doped semiconductor layer.Type: GrantFiled: January 4, 2012Date of Patent: March 25, 2014Assignee: National Central UniversityInventors: Tomi T. Li, Jeng-Yang Chang, Sheng-Hui Chen, Cheng-Chung Lee