Abstract: A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate wherein the first oxidation rate is greater than the second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layer to expose said second layer.

Abstract: The present invention provides a manufacturing method of a semiconductor device having a single semiconductor substrate, for forming a first processing circuit portion and a second processing circuit portion having mutually different thicknesses of gate oxide films on the single semiconductor substrate including the steps of: forming a first gate oxide film over the semiconductor substrate; sequentially forming an insulating film and a first conducting layer over the entire surface of the first gate oxide film; eliminating those portions ranging from the first gate oxide film to the first conducting layer, which portions are included within an element forming region of the first processing circuit portion; and forming, only in the element forming region of the first processing circuit portion, a second gate oxide film having a thickness different from that of the first gate oxide film.

Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.

Abstract: A method for forming variable oxide thicknesses across semiconductor chips comprises providing a silicon semiconductor substrate having pre-selected areas open to silicon surface using a photoresist layer; immersing the silicon semiconductor substrate in an HF type electrolytic bath to produce a porous silicon area; and removing the photoresist layer and oxidizing the silicon semiconductor substrate to produce a plurality of thicknesses of gate oxide on the silicon semiconductor substrate.

Abstract: A MOS transistor and a method for fabricating the MOS transistor which includes the forming a gate electrode containing an HLD film; etching the HLD film; etching a pad oxide film formed at a lower portion of the HLD film at a predetermined thickness; removing the nitride side wall spacer of an opening in the gate electrode; forming a LDD region by implanting impurity ions into the semiconductor substrate at both sides of the gate electrode; forming a side wall spacer at both sides of the gate electrode; and forming a source/drain by implanting impurity ions into the semiconductor substrate.

Abstract: A method of fabricating a semiconductor device applies a LOCOS profile characteristic to an edge portion of an STI in a HV region to thereby lower compressive stress that is concentrated on the side of the STI. A field oxide film is formed so that only edge portions of HV region (active region II) may be in contact with a comparatively stiff STI, and then, a thick gate oxide film is formed on the HV region by utilizing a nitride film as a mask. After the nitride film as a mask is removed, a thin gate oxide film is formed on a LV region (an active region I in which a thin gate oxide film is formed). As a result, a thinning phenomenon of a gate oxide film at an edge portion of STI is prevented that otherwise would occur when the gate oxide film for HV grows in a normal STI structure by utilizing a nitride film as a mask.

Abstract: According to one embodiment of the invention, a method of forming an asymmetric I/O transistor includes forming a first oxide layer outwardly from a semiconductor substrate, masking a first portion, less than a whole portion, of an I/O transistor region with a first photoresist layer, removing the first oxide layer from a core transistor region and a second portion of the I/O transistor region, removing the first photoresist layer, forming a second oxide layer outwardly from the substrate, forming gates for the core transistor region and the I/O transistor region, masking the first portion of the I/O transistor region with a second photoresist layer, doping a source region and a drain region of the core transistor region and a source region of the I/O transistor region with a first dopant, doping the source region and the drain region of the core transistor region and the source region of the I/O transistor region with a second dopant, removing the second photoresist layer, masking the core transistor region

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract: A method for forming dual thickness gate oxide layers comprising the following steps. A structure having at least a first area and a second area is provided. The second area of the structure is masked. Ion implanting Si4+ or Ge4+ ions into the unmasked first area of the structure to form an amorphous layer within the first area of the structure. The second area of the structure is unmasked. The first and second areas of the structure are oxidized to form: a first gate oxide layer upon the structure within the first area; and a second gate oxide layer upon the structure within the second area. The first gate oxide layer having a greater thickness than the second gate oxide layer, completing formation of the dual thickness gate oxide layers.

Abstract: There are formed a gate insulator 8 and a gate 3 of a power transistor Q having a trench-gate structure. There are then formed a channel region 5 and a source region 6 of the power transistor Q.

Abstract: A method of forming an NROM comprising mixed-signal circuits is provided. The method starts by providing a semiconductor substrate having a memory area and a periphery area. The periphery area has a plurality of active areas isolated by an isolation layer. A bottom electrode of a capacitor is formed atop the isolation layer in the periphery area. An ONO(oxide-nitride-oxide) process is performed. A photolithography, an anisotropic etching, and an ion implantation process are performed in order to etch the ONO dielectric layer in a bit line region not protected by the first photolithography process, and to form a plurality of buried bit lines. A photolithography and an ion implantation process are performed in order to form at least one ion well. The surface of the active area in the periphery area is wet etched.

Abstract: A method and article of manufacture of an ultra-thin base oxide or nitrided oxide layer in a CMOS device. The method and article of manufacture are formed by providing a silicon wafer with an initial oxide layer which is removed from the silicon wafer by a hydrogen baking step. A new oxide layer or nitrided oxide layer is formed by thermal growth on the silicon wafer surface. A portion of the new oxide layer is removed by hydrogen annealing. A MOSFET can be created by forming a gate electrode structure on a high-k dielectric material deposited on the new oxide layer.

Abstract: A method of integrating a photodiode and a CMOS transistor with a NVM on a semiconductor substrate is provided. A photo sensor region, a periphery circuit region, and a memory cell region are defined on the substrate. A first doped area is formed within the semiconductor substrate in the periphery circuit region, the photo sensor region and the memory cell region. A second doped area is formed within the semiconductor substrate in the periphery circuit region. An ONO dielectric layer is formed on the surface of the semiconductor substrate. A third doped area is formed on the first doped area in the photo sensor region, and a fourth doped area is formed on the first doped area in the memory cell region. Following removal of portions of the ONO dielectric layer covering the fourth doped region in the photo sensor region, the periphery circuit region and the memory cell region, an oxide layer is formed on the first doped area, the second doped area, the third doped area, and the fourth doped area.

Abstract: A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.

Abstract: Process sequences used to simultaneously form a first dielectric gate layer for a first group of MOSFET elements, and a second dielectric gate layer for a second group of MOSFET elements, with the thickness of the first dielectric gate layer different than the thickness of the second gate dielectric layer, has been developed. A first iteration of this invention entails a remote plasma nitridization procedure used to form a thin silicon nitride layer on a bare, first portion of a semiconductor substrate, while simultaneously forming a thin silicon oxynitride layer on the surface of a first silicon dioxide layer, located on second portion of the semiconductor substrate.

Abstract: A method of manufacturing semiconductor devices is provided for forming a tungsten plug or polysilicon plug and minimizing the step-height of the intermediate insulating layer. An etching composition for this process is also provided as are semiconductor devices manufactured by this process. The method of manufacturing semiconductor devices includes the steps of forming a tungsten film having a certain thickness on an insulating layer and burying contact holes formed in the insulating layer constituting a specific semiconductor structure, and spin-etching the tungsten film using a certain etching composition such that the tungsten film is present only inside the contact holes not existing on the insulating film.

Abstract: A memory array area and a periphery circuit region on the surface of a semiconductor wafer are defined, and a gate oxide layer and an undoped polysilicon layer are sequentially formed on the wafer. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer, followed by etching of the doped polysilicon layer in the memory array area down to a predetermined thickness. Next, a silicide layer and a protection layer are formed on the surface of the semiconductor wafer. A photo-etching-process (PEP) is used to etch portions of the protection layer, the silicide layer, the undoped polysilicon layer and the doped polysilicon layer to form a plurality of gates. Finally, a LDD and spacers of each MOS transistor, and a source and a drain of each MOS transistor in the periphery circuit region are formed.

Abstract: A shallow trench isolation (STI) structure is constructed in dual gate oxide device that requires a high voltage and low-voltage operation, for example in a LCD driver IC. The disclosed fabrication method prevents deterioration in operational characteristics of resulting transistors and prevents decrease in the reliability of the gate oxide film.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: Embodiments include a method for manufacturing a semiconductor device including a plurality of non-volatile memory transistors that include field effect transistors operated at a plurality of different voltage levels. The method includes the following steps: (a) forming a gate insulation layer 26 and a floating gate 40 of a non-volatile memory transistor 400 on a silicon substrate 10 in a memory region 4000; (b) forming, on the wafer, a first silicon oxide layer 50aL by a thermal oxidation method and a second silicon oxide layer 50bL by a CVD method; (c) removing the first and the second silicon oxide layers in the first transistor region; and (d) forming a silicon oxide layer 20L on the wafer by a thermal oxidation method. The silicon oxide layer formed in step (d) compose at least a portion of a gate insulation layer of a first voltage-type transistor and a gate insulation layer of a second voltage-type transistor.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the may reliably operate even at a low power-supply voltage.

Abstract: In a semiconductor device in which a non-volatile memory element and a p-channel IGFET are mounted on a single substrate, a nitride atom density of a tunnel insulating film of the non-volatile memory element is set to be higher than a nitride atom density of a gate insulating film of the p-channel IGFET. With respect to a manufacturing method, a region where the gate insulating film of the p-channel IGFET is covered by a thick buffer silicon oxide film when nitrifying the tunnel insulating film of the non-volatile memory element. The buffer silicon oxide film can be reliably removed when the gate insulating film is formed, because no nitride film is made between the substrate and the buffer silicon oxide film.

Abstract: In a non-volatile memory, memory cells have respective floating gates formed of a first polysilicon and respective control gates formed of a second polysilicon. Further, in the non-volatile memory, peripheral circuits include transistors having respective gates formed of the first polysilicon. In addition, a silicide layer is formed directly on the control gates of the memory cells and directly on the gates of the transistors.

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A method is provided for manufacturing a multiple voltage flash memory integrated circuit structure on a semiconductor substrate having a plurality of shallow trench isolations and a floating gate structure. A first dielectric layer is formed and a portion removed to expose regions of the semiconductor substrate for first and second low voltage devices. A second dielectric layer is formed over the first dielectric layer and the semiconductor substrate and a portion removed to expose a region of the semiconductor substrate for the second low voltage device. A third dielectric layer is formed over the second dielectric layer to form: a floating gatedevice including the first, second, and third dielectric layers; a first voltage device including the first, second, and third dielectric layers; a second voltage device including the second and third dielectric layers; and a third voltage device including the third dielectric layer.

Abstract: A method for forming a multiple thickness gate oxide layer by implanting nitrogen ions in a first area of a semiconductor substrate while a second area of the semiconductor substrate is masked; implanting argon ions into the second area of the semiconductor substrate while the first area of the semiconductor substrate is masked; and thermally growing a gate oxide layer wherein, the oxide growth is retarded in the first area and enhanced in the second area. A threshold voltage implant and/or an anti-punchthrough implant can optionally be implanted into the semiconductor substrate prior to the nitrigen implant using the same implant mask as the nitrogen implant for a low voltage gate, and prior to the argon implant using the same implant mask as the argonm implant for a high voltage gate, further reducing processing steps.

Abstract: The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a gate oxide film of a semiconductor device by which semiconductor devices having different electrical characteristics can be implemented in the same chip. The present invention provides a method for fabricating a gate oxide film of a semiconductor device which includes the steps of: forming a screen oxide film on the top surface of a semiconductor substrate; forming an ion implantation mask on parts of the top surface of the screen oxide film; implanting nitrogen ions into the semiconductor substrate using the ion implantation mask; removing the ion implantation mask and the screen oxide film; forming an oxide film on the top surface of the semiconductor substrate; and annealing the semiconductor substrate in a N2O or O3 atmosphere.

Abstract: First, an isolation region is formed on a surface portion of a semiconductor substrate of silicon, thereby defining first and second regions, which are isolated from each other by the isolation region, on the semiconductor substrate. Next, a tantalum oxide film is formed in the first region on the semiconductor substrate. Then, a silicon dioxide film is formed in the second region on the semiconductor substrate by heat-treating the semiconductor substrate within an ambient containing oxygen as a main component. Subsequently, first and second gate electrodes are formed on the tantalum oxide and silicon dioxide films, respectively. Thereafter, first and second gate insulating films are formed by etching the tantalum oxide and silicon dioxide films using the first and second gate electrodes as respective masks.

Abstract: A method for forming a laterally diffused metal-oxide semiconductor is disclosed. The invention normally is for forming a transistor device, which includes the following steps. Firstly a semiconductor layer is provided. Then a field insulating region is formed into the semiconductor layer. Sequentially forming a gate dielectric layer over a portion of the field insulating region is carried out. Then forming a deep portion of a first drain/source region within the semiconductor layer and spaced from the field insulating region/the top surface. Here, the deep portion is doped with dopants of a conductivity type, with the deep portion having a first doping concentration. The next step is forming a lightly doped portion of the first drain/source region within the semiconductor layer and a neighbouring portion of the field insulating region/the oxide top surface and adjacent the channel region. Generally the lightly doped portion is doped with dopants of the conductivity type.

Abstract: A process for preparing a semiconductor which is capable of implanting indium effectively during the process of forming a gate insulation film with different levels of thickness includes a 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed thereon to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, a 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, a 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, a 4th step of forming a P-well region inside the 1st gate insulation film partially removed region before forming a 2nd N-channel region containing indium on this P-well region, and a 5th step of removing the 2nd resist mask before forming a 2nd gat

Abstract: A method is disclosed for the oxidation of a substrate and the formation of oxide regions in the substrate by implantation of fluorine into the silicon lattice and subsequently forming an oxide region by a typical oxide growth process. The oxide growth process may be those such as thermal oxidation or the local oxidation of silicon. The process according to the present invention allows for the simultaneous growth of oxides having different thicknesses at the same time by tailoring the fluorine implantation.

Abstract: A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate.

Abstract: A transistor having a gate insulation layer whose peripheral portion has an increased thickness and a method of fabricating these transistor devices is disclosed. The peripheral portions with increased thickness of the gate insulation layer significantly reduce the injection of charge carriers into the gate insulation layer. Accordingly, the transistors described in the present application exhibit an improved long-time reliability. In addition, the lateral penetration of ions beneath the gate insulation layer for forming the lightly-doped drain and/or the lightly doped source is increased since the implantation may be performed at a tilt angle with respect to the perpendicular direction which is the conventionally used direction of the implantation step.

Abstract: The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a gate oxide film of a semiconductor device by which semiconductor devices having different electrical characteristics can be implemented in the same chip. The present invention provides a method for fabricating a gate oxide film of a semiconductor device which includes the steps of: forming a screen oxide film on the top surface of a semiconductor substrate; forming an ion implantation mask on parts of the top surface of the screen oxide film; implanting nitrogen ions into the semiconductor substrate using the ion implantation mask; removing the ion implantation mask and the screen oxide film; forming an oxide film on the top surface of the semiconductor substrate; and annealing the semiconductor substrate in a N2O or O3 atmosphere.

Abstract: A dual gate oxides' process for mixed-mode IC is provided. More particularly, the present invention relates to a dual gate oxides' process for mixed-mode IC, which protects and improves the dual gate oxides' quality.

Abstract: A method for forming a dual oxide layer on a silicon substrate provides that layer having varying thicknesses by using a damage layer formed on the silicon substrate, or a silicon nitride layer deposited on the silicon substrate. The damage layer is formed on the silicon substrate by dry etching a designated part of the silicon substrate, and the dual oxide layer is formed by using the properties of SiO2 by which the oxide layer growth speed on the damage layer is slower than that on the silicon substrate. A pattern of the damage layer is defined by photolithography, and the damage layer having a depth of about 20 to 5,000 Å is formed using CF4, CHF3, or Ar gas at a pressure of 900 mTorr or less, or using Cl2 or HBr. In the preoxidation cleaning step, a solution containing NH4F, HF, and H2O, a standard solution containing NH4OH, H2O2, and H2O, and/or HF are used.

Abstract: A method and structure for forming an integrated circuit chip having multiple-thickness gate dielectrics includes forming a gate dielectric layer over a substrate, forming a sacrificial layer over the gate dielectric layer, forming first openings through the sacrificial layer to expose the gate dielectric layer in the first openings, growing a first gate dielectric having a thickness greater than that of the gate dielectric layer in the first openings, depositing a first gate conductor above the first gate dielectric in the first openings, forming a second opening through the sacrificial layer to expose the gate dielectric layer in the second opening, and depositing a second gate conductor in the second opening.

Abstract: A method for fabricating an embedded dynamic random access memory (DRAM) is provided. The method contains implanting ions onto the substrate at a DRAM active area and a logic circuit with different dopant concentration. A thermal oxidation process is performed to form a DRAM gate oxide layer with a greater thickness than that of a logic gate oxide layer. A DRAM MOS transistor is formed at a DRAM region and a logic MOS transistor is formed at a logic region. The DRAM MOS transistor has a polycide gate structure. The logic transistor has a first self-aligned silicide (Salicide) layer on its gate structure, and a second Salicide on its interchangeable source/drain region. A dielectric layer is formed over the substrate. A contact opening is formed in the dielectric layer by patterning the dielectric layer to expose the interchangeable source/drain region of the DRAM transistor. A stack capacitor is formed on the dielectric layer.

Abstract: A method is disclosed for the oxidation of a substrate and the formation of oxide regions in the substrate by implantation of fluorine into the silicon lattice and subsequently forming an oxide region by a typical oxide growth process. The oxide growth process may be those such as thermal oxidation or the local oxidation of silicon. The process according to the present invention allows for the simultaneous growth of oxides having different thicknesses at the same time by tailoring the fluorine implantation.

Abstract: A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions.

Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Abstract: Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

Abstract: A method of manufacturing a semiconductor device having a high Vth MOS FET and a low Vth MOS FET which have respective gate insulating films different in thickness from each other without covering the gate insulating film with a resist film. A silicon oxide film on a low Vth region is etched away, and in the nitriding process a nitride film is formed on the low Vth region. The silicon oxide film on a high Vth region is etched away without forming a resist film on the nitride film. A semiconductor substrate is thermally oxidized to form relatively a thick gate insulating film on the high Vth region and also to form a thin gate insulating film on the low Vth region. Gate electrodes are formed and then impurity diffusion layers forming a source and drain region are formed.

Abstract: In the present invention, a method of forming multitude of growth rates of oxide layer on the surface of a substrate is provided. The method comprises providing a first oxide layer on the substrate. A photoresist layer is formed on the first oxide layer. The photoresist layer exposes a portion of the first oxide layer. The exposed portion of the first oxide layer is subjected to plasma fluoridation. Then the photoresist layer is removed. Again, the first oxide layer is removed and a second oxide layer is formed on the substrate.

Abstract: A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion.

Abstract: A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.

Abstract: In one embodiment, the present invention relates to a method of forming a NAND type flash memory device involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N2O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous

Abstract: The method for manufacturing semiconductor devices, according to the present invention, that include transistors for peripheral circuits to which input and output signal lines are connected and transistors for internal circuits that have lower operation voltage than that of the transistors for peripheral circuits consists of the steps of exposing a surface of a first region forming the transistors for peripheral circuits of a semiconductor substrate, forming a first gate oxide layer by oxidizing the exposed surface of the first region in an oxidizing atmospheric gas including hydrogen atoms, exposing a surface of a second region forming the transistors for internal circuits of the semiconductor substrate, and forming a second gate oxide layer by oxidizing the exposed surface of the second region in an oxidizing atmospheric gas without hydrogen atoms and subsequently by oxidizing the exposed surface in a nitrogen monoxide atmosphere.

Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.