Having Organic Semiconductive Component Patents (Class 438/99)
  • Patent number: 10243157
    Abstract: A thin film transistor array includes a substrate, a gate electrode formed on the substrate, a gate insulation film covering the gate electrode, a source electrode formed on the gate insulation film, a drain electrode formed on the gate insulation film, a semiconductor layer connected to the source electrode and the drain electrode, an interlayer insulation film formed on the drain electrode and the semiconductor layer, and a pixel electrode formed on the interlayer insulation film. The interlayer insulation film has a via hole that reaches a portion of the drain electrode, and the drain electrode has a liquid repellent coating on the portion positioned in the via hole.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: March 26, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Minoru Kumagai, Noriaki Ikeda
  • Patent number: 10236204
    Abstract: The semiconductor processing system includes a reactor chamber that has an upper wall and a lower wall. A hold member is disposed in the reactor chamber to hold a semiconductor substrate in such a way that it faces the lower wall of the reactor chamber.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 19, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Manfred Engelhardt
  • Patent number: 10212822
    Abstract: Provided are a structure for which ink wettability/spreadability in the width direction of a line drawn on a substrate is limited and a high aspect ratio can be achieved, a manufacturing method for said structure, and a line pattern. The present invention provides a structure comprising: a droplet overlapping solidification layer obtained by droplets sloping and continuously overlapping each other in the direction of movement of a substrate and solidifying, a droplet flow solidified layer obtained by the droplets flowing on the droplet overlapping solidification layer and continuously being solidified without the droplets overlapping, and recesses formed at the boundary region between the droplet overlapping solidification layer and the droplet flow solidified layer.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 19, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Jun Akedo, Akito Endo
  • Patent number: 10205094
    Abstract: A raw material solution (6), in which an organic semiconductor material is dissolved in a solvent, is supplied to a substrate (1). The solvent is evaporated so that crystals of the organic semiconductor material are precipitated. Thus, an organic semiconductor thin film (7) is formed on the substrate (1). An edge forming member (2) having a contact face (2a) on one side is used and located opposite the substrate (1) so that the plane of the contact face (2a) intersects the surface of the substrate (1) at a predetermined angle. The raw material solution (6) is supplied to the substrate (1) and formed into a droplet (6a) that comes into contact with the contact face (2a).
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: February 12, 2019
    Assignee: PI-CRYSTAL INC.
    Inventors: Junichi Takeya, Junshi Soeda
  • Patent number: 10199586
    Abstract: A process for preparing a device and a device including a substrate; an interlayer disposed on the substrate, wherein the interlayer comprises a cured film formed from an interlayer composition, wherein the interlayer composition comprises: an epoxy compound; a polyvinyl phenol; a melamine resin; a solvent; an optional surfactant; and an optional catalyst; a source electrode and a drain electrode disposed on a surface of the interlayer; a semiconductor layer disposed on the interlayer, wherein the semiconductor layer is disposed into a gap between the source and drain electrode; a back channel interface comprising an interface between the semiconductor layer and the interlayer, wherein the interlayer serves as a back channel dielectric layer for the device; a dielectric layer disposed on the semiconductor layer; a gate electrode disposed on the dielectric layer. Also an interlayer composition and an organic thin film transistor comprising the interlayer composition.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 5, 2019
    Assignees: Xerox Corporation, Palo Alto Research Center Incorporated
    Inventors: Guiqin Song, Ping Mei, Nan-Xing Hu, Gregory Whiting, Biby Esther Abraham
  • Patent number: 10180354
    Abstract: An imaging device which does not include a color filter and does not need arithmetic processing using an external processing circuit is provided. A first circuit includes a first photoelectric conversion element, a first transistor, and a second transistor; a second circuit includes a second photoelectric conversion element, a third transistor, and a fourth transistor; a third circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and a second capacitor; the spectroscopic element is provided over the first photoelectric conversion element or the second photoelectric conversion element; and the first circuit and the second circuit is connected to the third circuit through a first capacitor.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10121662
    Abstract: A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 10090212
    Abstract: An embodiment of the present disclosure discloses an evaporation method, including: providing a flexible substrate having an original size; stretching the flexible substrate to have an evaporation size, wherein, the evaporation size is greater than the original size; arranging a mask on a side of the flexible substrate having the evaporation size; evaporating a material onto the flexible substrate having the evaporation size by using the mask, to form a patterned film layer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 2, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Shixin Ruan, Fuyi Cui, Xuefei Bai, Fashun Li
  • Patent number: 10046548
    Abstract: A method for fabricating a flexible device is provided. The method includes forming a sacrificial layer on a substrate; and forming a reflective layer to reflect a laser for subsequently de-bonding the sacrificial layer from the rigid substrate back to the sacrificial layer to reduce required de-bonding energy of the laser over at least a portion of the rigid substrate. Further, the method includes forming a flexible device over the reflective layer; and separating the substrate from the sacrificial layer by irradiating the sacrificial layer using the laser.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 14, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lu Liu, Ming Che Hsieh
  • Patent number: 10032630
    Abstract: There is provided a technique for facilitating a patterning process by the DSA appropriately and efficiently. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including (a) accommodating in a process chamber a substrate having a guide pattern thereon; (b) supplying a plasma of a first process gas into the process chamber to subject the substrate to first one of a first process for hydrophilizing the substrate and a second process for hydrophobilizing the substrate; and (c) supplying a plasma of a second process gas into the process chamber to subject the substrate to second one of the first process and the second process other than the first one of the first process and the second process.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 24, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Katsuhiko Yamamoto, Hajime Karasawa, Kazuyuki Toyoda
  • Patent number: 10014494
    Abstract: Provided is a method of detaching a display module. The method of detaching the display module includes providing a carrier substrate, forming a display module, which is divided into a first area and a second area, on the carrier substrate, disposing a protective film covering the first area and exposing the second area on the display module, performing a first detaching process of detaching the second area from the carrier substrate by using a first detaching unit, and performing a second detaching process of detaching the protective film and the display module from the carrier substrate by using a second detaching unit.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gilhwan Yeo, Min-woo Lee, Seungjun Moon
  • Patent number: 9911609
    Abstract: A method of forming a nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 9881789
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate having an oxide film; performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate, supplying a carbon-containing gas to the substrate, and supplying a nitrogen-containing gas to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate and supplying a gas containing carbon and nitrogen to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas containing carbon to the substrate and supplying a nitrogen-containing gas to the substrate, the oxide film being used as an oxygen source to form a nitride layer containing oxygen and carbon as a seed layer; and forming a nitride film containing no oxygen and carbon as a first film on the seed layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 30, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Shingo Nohara, Ryota Sasajima, Katsuyoshi Harada, Yuji Urano
  • Patent number: 9864248
    Abstract: An aim of the present invention is to reduce manufacturing costs and lower the electrical resistance of composite metal electrodes while lowering the contact resistance of the composite metal electrodes with respect to an organic semiconductor film. A TFT (semiconductor device) of the present invention includes an organic semiconductor film formed from an organic semiconductor material, and a source electrode and a drain electrode that are composite metal electrodes that contact the organic semiconductor film. The source electrode and the drain electrode are configured such that a low-resistance metal material that makes ohmic contact with the organic semiconductor film, the contact resistance thereof being lower than that of a base metal material formed of a metal material, is mixed with the base metal material, and the low-resistance metal material is disposed so as to be exposed at least at a contact surface with the organic semiconductor film.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: January 9, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yasumori Fukushima
  • Patent number: 9850132
    Abstract: Provided is a method for growing carbon nanotubes that enables the growth of high-density carbon nanotubes. A high frequency bias voltage is applied to a loading table on which a wafer W having a catalytic metal layer is mounted to generate a bias potential on the surface of the wafer W, and oxygen plasma is used to micronize the catalytic metal layer to form catalytic metal particles. Thereafter, hydrogen plasma is used to reduce the surface of the catalytic metal particles to form activated catalytic metal particles having an activated surface. By using each activated catalytic metal particles as a nucleus, carbon nanotubes are formed.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 26, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Matsumoto, Kenjiro Koizumi
  • Patent number: 9837608
    Abstract: A mask assembly includes: a mask frame; and a mask sheet disposed on the mask frame, wherein the mask sheet is stretched by applying tensile force and affixed onto the mask frame, wherein the mask sheet includes a pattern including a plurality of openings, and wherein a thickness of the pattern is different from thicknesses of other portions of the mask sheet.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: December 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngmin Moon, Minho Moon, Sungsoon Im, Soonchul Chang, Kyuhwan Hwang
  • Patent number: 9818909
    Abstract: A light emitting diode (LED) containing device including a light emitting diode (LED) structure, and a light transmissive substrate in contact with the LED structure. The light transmissive substrate has a texture surface tuned to include features with dimensions greater than a wavelength of light produced by the LED structure. In some embodiments, increasing the feature size of the texture to be comparable to the wavelength of light produced by the LED increases light extraction from the LED in comparison to when the feature size of the texture is substantially less or substantially larger than the wavelength of light.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Patent number: 9793505
    Abstract: A light emitting device including an emissive material comprising quantum dots is disclosed. In one embodiment, the device includes a cathode, a layer comprising a material capable of transporting and injection electrons comprising an inorganic material, an emissive layer comprising quantum dots, a layer comprising a material capable of transporting holes, a layer comprising a hole injection material, and an anode. In certain embodiments, the hole injection material can be a p-type doped hole transport material. In certain preferred embodiments, quantum dots comprise semiconductor nanocrystals. In another aspect of the invention, there is provided a light emitting device wherein the device has an initial turn-on voltage that is not greater than 1240/?, wherein ? represents the wavelength (nm) of light emitted by the emissive layer. Other light emitting devices and a method are disclosed.
    Type: Grant
    Filed: October 2, 2010
    Date of Patent: October 17, 2017
    Assignee: QD VISION, INC.
    Inventors: Zhaoqun Zhou, Peter T. Kazlas, Mead Misic, Zoran Popovic, John Spencer Morris
  • Patent number: 9768402
    Abstract: A method of preparing a bulk heterojunction organic photovoltaic cell through combinations of thermal and solvent vapor annealing are described. Bulk heterojunction films may prepared by known methods such as spin coating, and then exposed to one or more vaporized solvents and thermally annealed in an effort to enhance the crystalline nature of the photoactive materials.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: September 19, 2017
    Assignees: University of Southern California, The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Mark E. Thompson, Guodan Wei, Siyi Wang
  • Patent number: 9745657
    Abstract: A deposition apparatus includes a chamber, a support in the chamber, the support supporting a substrate, a deposition source in the chamber, the deposition source being above the support and emitting one or more deposition materials toward the substrate, a mask between the support and the deposition source, the mask including a deposition region having one or more openings, the one or more deposition materials passing through the one or more openings, and an edge region having a plurality of first slits, the edge region surrounding the deposition region, and a first coating layer on a first surface of the mask, the first surface of the mask facing the substrate.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: August 29, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hakmin Kim
  • Patent number: 9748498
    Abstract: Use of transition metal complexes of the formula (I) in organic light-emitting diodes where: M1 is a metal atom; carbene is a carbene ligand; L is a monoanionic or dianionic ligand; K is an uncharged monodentate or bidentate ligand selected from the group consisting of phosphines; CO; pyridines; nitriles and conjugated dienes which form a ? complex with M1; n is the number of carbene ligands and is at least 1; m is the number of ligands L, where m can be 0 or ?1; o is the number of ligands K, where o can be 0 or ?1; where the sum n+m+o is dependent on the oxidation state and coordination number of the metal atom and on the denticity of the ligands carbene, L and K and also on the charge on the ligands carbene and L, with the proviso that n is at least 1, and also an OLED comprising these transition metal complexes, a light-emitting layer comprising these transition metal complexes, OLEDs comprising this light-emitting layer, devices comprising an OLED according to the present invention, and specific tr
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: August 29, 2017
    Assignee: UDC Ireland Limited
    Inventors: Markus Bold, Christian Lennartz, Martina Prinz, Hans-Werner Schmidt, Mukundan Thelakkat, Markus Baete, Christian Neuber, Wolfgang Kowalsky, Christian Schildknecht, Hans-Hermann Johannes
  • Patent number: 9740323
    Abstract: Disclosed are a touch sensor and a method of fabricating the same. An insulator of the touch sensor contains a polymer and has an array of vertically aligned nanowires structure. Therefore, the touch sensor can be easily changed in thickness, which facilitates change in electrostatic capacity, thereby increasing sensitivity of the touch sensor. In addition, the present invention can simplify an existing complicated process of fabricating a touch sensor.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 22, 2017
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Myung-Han Yoon, Jaehyuk Lee
  • Patent number: 9650716
    Abstract: A method is used to provide an electrically conductive article. The method includes: (i) providing a continuous polymeric web of a transparent polymeric substrate; (ii) forming a first photocurable pattern on at least a first portion on a first supporting side of the continuous polymeric web using a photocurable composition comprising metal particles; (iii) exposing the photocurable pattern to form a photocured pattern on the first portion of the first supporting side; (iv) electrolessly plating the photocured pattern with an electrically-conductive metal to form an electrically-conductive metal pattern; and (v) forming a dry outermost polymeric coating over at least part but not all of the electrically-conductive pattern, the dry polymeric coating having a dry thickness of less than 5 ?m, an integrated transmittance of at least 80%, and comprising a non-crosslinked thermoplastic polymer having a glass transition temperature (Tg) that is equal to or greater than 65° C.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: May 16, 2017
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Marcus Stephen Bermel, Lisa Baxter Todd, Linda Mae Franklin, Thomas Henry Mourey, Christine Joanne Landry-Coltrain
  • Patent number: 9627490
    Abstract: Layered oxide structures comprising an overlayer of high quality VO2 and methods of fabricating the layered oxide structures are provided. Also provided are high-speed switches comprising the layered structures and methods of operating the high-speed switches. The layered oxide structures include high quality VO2 epitaxial films on isostructural SnO2 growth templates.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 18, 2017
    Inventors: Chang-Beom Eom, Daesu Lee
  • Patent number: 9629020
    Abstract: A dynamic spectrum arbitrage (DSA) system may include a dynamic spectrum policy controller (DPC) and a dynamic spectrum controller (DSC) that together dynamically manage the allocation and use of resources (e.g., spectrum resources) across different networks. The DPC and DSC may store DSC context information, and use this information to perform various DSA operations. For example, the DSC may determine whether there is bandwidth available for allocation within cells in a first telecommunication network, generate a resource register request message that identifies the amount of bandwidth that is available, and send the generated resource register request message to the DPC using a DSAAP component/protocol. The DSC may receive the resource register response message and a bid success message via the DSAAP, and send a resources allocated message to the DPC via the DSAAP to commit the requested amount of bandwidth for use by the second telecommunication network.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: April 18, 2017
    Assignee: Rivada Networks, LLC
    Inventors: Clint Smith, Nageswara Rao Deekshitha Devisetti, Samuel Smith
  • Patent number: 9620728
    Abstract: A thin film transistor (TFT) has a gate electrode; a gate insulation layer, a semiconducting channel separated from the gate electrode by the gate insulation layer; a source electrode and a drain electrode. The gate insulation layer is a cross-linked cyanoethylated polyhydroxy polymer, e.g. a cross-linked cyanoethylated pullulan, having a high dielectric constant and the semiconducting channel has a network of semiconducting carbon nanotubes. The semiconducting channel is adhered to the gate insulation layer through a polymeric material. The carbon nanotubes adhere to the polymeric material and the polymeric material reacts or interacts with the gate insulation layer. TFTs have high mobilities while maintaining good on/off ratios.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 11, 2017
    Assignee: National Research Council of Canada
    Inventors: Naiying Du, Patrick Malenfant, Zhao Li, Jacques Lefebvre, Girjesh Dubey, Gregory Lopinski, Shan Zou
  • Patent number: 9606095
    Abstract: Disclosed herein are a method of manufacturing large area graphene nanoribbons, which have no residual layer by interposing a chromium layer between a resist layer and a graphene layer, and a sensor including the graphene nanoribbons.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: March 28, 2017
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Gun-young Jung, yusin Pak
  • Patent number: 9590192
    Abstract: The present invention relates to a transistor and a method for manufacturing the same. The transistor according to an embodiment of the present invention includes a substrate, a drain electrode formed on the substrate, a source electrode formed on the substrate and spaced apart from the drain electrode, a channel layer formed on the substrate and including a channel region electrically connecting the drain electrode and the source electrode to each other, a gate electrode formed on the substrate and spaced apart from the channel region, and a liquid crystal layer formed on the substrate to connect the channel layer and the gate electrode to each other.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: March 7, 2017
    Assignee: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Youngkyoo Kim, Jooyeok Seo, Hwajeong Kim
  • Patent number: 9589352
    Abstract: A position controller, including a moving part configured to process or measure a workpiece, a laser unit disposed on one side of the moving part and configured to radiate a laser, a mask on which a laser image is formed corresponding to the irradiated laser, and a position control unit configured to position the moving part based on information of the laser image.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 7, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jeong-Won Han
  • Patent number: 9554473
    Abstract: An apparatus for providing a patterned structure includes a deposition facility for depositing an electrically conductive material on a cylindrical surface of a transfer roll, a supply facility for providing a flexible substrate with a carrier layer, a press-roll for pressing the flexible substrate with the carrier layer against the surface of the transfer roll, the press-roll being positioned in the rotation direction of the transfer roll with respect to a position where the first deposition facility deposits the substance on the transfer roll, and being arranged for embedding the deposited substance in said carrier layer, wherein the adhesion between the printed substance and the cylindrical surface of the transfer roll is less than the adhesion between the printed substance and said carrier layer, a transport facility for releasing the flexible substrate with the carrier layer embedding the substance as the patterned structure from the transfer roll.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 24, 2017
    Assignee: Nederlandse Organisatie voor toegepastnatuurwetenschappelijk onderzoek TNO
    Inventors: Tim Johannes Van Lammeren, Eric Rubingh
  • Patent number: 9553153
    Abstract: A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 9548454
    Abstract: Method for the oriented crystallization of materials. The present invention relates to a method useful for orienting the crystallization of a material over a surface zone of at least one face of a substrate, comprising at least the steps consisting in: i. determining, on said face, the surface over which the crystalline deposit must be formed, referred to as the zone of interest, ii. depositing, on said face and at the periphery of said zone of interest, at least one particle dedicated to forming a crystallization nucleus, iii. bringing said particle into contact with at least said material to be crystallized, iv.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 17, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Mohammed Benwadih
  • Patent number: 9527098
    Abstract: Provided are: a vapor deposition mask which can be light weight and have high definition even when the size is increased; a method for producing a vapor deposition mask device whereby it is possible to accurately position the aforementioned vapor mask on a frame; and a method for producing an organic semiconductor element whereby it is possible to produce a high-definition organic semiconductor element. A metal mask on which slits are disposed, and a resin mask which is positioned on the surface of the metal mask and on which multiple openings corresponding to the pattern formed by means of vapor deposition are horizontally and vertically arranged in rows are laminated.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: December 27, 2016
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yoshinori Hirobe, Yutaka Matsumoto, Masato Ushikusa, Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata, Takashi Takekoshi
  • Patent number: 9508931
    Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishal Nirmal Ramaswamy, Qian Tao
  • Patent number: 9490309
    Abstract: An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate. The frame may be formed using, as frame members, two L-shaped semiconductor members in combination or four or more stick semiconductor members in combination.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: November 8, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Kuwabara
  • Patent number: 9484196
    Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: November 1, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Zhe Song, Tuman E. Allen, Cole S. Franklin, Dan Gealy
  • Patent number: 9472760
    Abstract: In the present invention, an organic semiconductor film is formed by using a cover member which is disposed on a substrate for forming the organic semiconductor film and forms a space relative to the substrate, filling the space between the cover member and the substrate with a solution, and drying the filled solution, wherein the cover member has a control surface on which an uppermost part most separated from the substrate and a descending part provided on both sides in the y-direction of the uppermost part so as to descend from the uppermost part toward the substrate are formed.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: October 18, 2016
    Assignee: FUJIFILM Corporation
    Inventor: Yoshihisa Usami
  • Patent number: 9388931
    Abstract: There is provided a substrate processing apparatus to perform a predetermined process on a substrate on which a pattern mask is formed, comprising a compartment mechanism configured to switch between a compartmented state and an open state. The compartmented state includes a first section having the evaporation source formation part, and a second section configured to transfer the substrate between an outside of processing vessel and a mounting table. The substrate processing apparatus comprises a substrate transfer hole formed in the processing vessel and configured to open and close with respect to the second section being in the compartmented state; and an exhaust hole formed to connect to the second section and configured to exhaust the second section in the compartment state to remove a solvent atmosphere of the second section.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 12, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Shinji Kobayashi
  • Patent number: 9385332
    Abstract: Disclosed are organic-inorganic hybrid self-assembled multilayers that can be used as electrically insulating (or dielectric) materials. These multilayers generally include an inorganic primer layer and one or more bilayers deposited thereon. Each bilayer includes a chromophore or “?-polarizable” layer and an inorganic capping layer composed of zirconia. Because of the regularity of the bilayer structure and the aligned orientation of the chromophore resulting from the self-assembly process, the present multilayers have applications in electronic devices such as thin film transistors, as well as in nonlinear optics and nonvolatile memories.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 5, 2016
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Young-geun Ha, Antonio Facchetti
  • Patent number: 9384963
    Abstract: Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: July 5, 2016
    Assignee: American Air Liquide, Inc.
    Inventors: Venkateswara R. Pallem, Christian Dussarrat, Wontae Noh
  • Patent number: 9379324
    Abstract: A method for producing a vapor deposition mask capable of satisfying both enhancement in definition and reduction in weight even when a size is increased, and a method for producing an organic semiconductor element capable of producing an organic semiconductor element with high definition are provided. A vapor deposition mask is produced by the steps of preparing a metal plate with a resin layer in which a resin layer is provided on one surface of a metal plate, forming a metal mask with a resin layer by forming a slit that penetrates through only the metal plate, for the metal plate in the metal plate with a resin layer, and thereafter, forming a resin mask by forming openings corresponding to a pattern to be produced by vapor deposition in a plurality of rows lengthwise and crosswise in the resin layer by emitting a laser from the metal mask side.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: June 28, 2016
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Hiroyuki Nishimura, Katsunari Obata
  • Patent number: 9337273
    Abstract: A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: May 10, 2016
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Amirhasan Nourbakhsh, Mirco Cantoro, Cedric Huyghebaert, Mark Heyns, Stefan DeGendt
  • Patent number: 9331306
    Abstract: An organic optical device which can suppress deterioration due to moisture or an impurity is provided. An organic optical device includes a supporting body, a functional layer provided over the supporting body, and a light-emitting body containing an organic compound provided over the functional layer. The functional layer includes an insulating film containing gallium or aluminum, zinc, and oxygen. The supporting body and the functional layer each have a property of transmitting light with a wavelength of greater than or equal to 400 nm and less than or equal to 700 nm. By using the insulating film containing gallium or aluminum, zinc, and oxygen as a protective film, entry of moisture or an impurity into an organic compound or a metal material can be suppressed.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 3, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisao Ikeda, Kengo Akimoto
  • Patent number: 9327982
    Abstract: Methods of forming a graphene material on a surface are presented. A metal material is disposed on a material substrate or material layer and is infused with carbon, for example, by exposing the metal to a carbon-containing vapor. The carbon-containing metal material is annealed to cause graphene to precipitate onto the bottom of the metal material to form a graphene layer between the metal material and the material substrate/material layer and also onto the top and/or sides of the metal material. Graphene material is removed from the top and sides of the metal material and then the metal material is removed, leaving only the graphene layer that was formed on the bottom of the metal material. In some cases graphene material that formed on one or more side of the sides of the metal material is not removed so that a vertical graphene material layer is formed.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 3, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Boris N. Feygelson
  • Patent number: 9324944
    Abstract: A selection device, non-volatile memory cell, and method of fabricating the same. The selection device employs an oxide laminate structure including a tunneling oxide layer and a metal-cluster oxide layer between first and second electrodes, enabling a high selection ratio and sufficient on-current density to allow program data recordation in a memory cell at relatively low voltage. The non-volatile memory cell includes the selection device electrically connected to a resistive random access memory device, including a resistance change layer, enabling suppression of current leakage from a non-selected adjacent memory cell in an array structure. In the method of fabrication, a tunneling oxide layer is formed by depositing and oxidizing a metal layer to control oxygen vacancy density in the metal-cluster oxide layer, and an interface oxide layer is formed in the tunneling oxide layer by doping of metal-clusters in the metal-cluster oxide layer, improving on-current density of the selection device.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: April 26, 2016
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyunsang Hwang, WooTae Lee
  • Patent number: 9276226
    Abstract: Disclosed are organic-inorganic hybrid self-assembled multilayers that can be used as electrically insulating (or dielectric) materials. These multilayers generally include an inorganic primer layer and one or more bilayers deposited thereon. Each bilayer includes a chromophore or “?-polarizable” layer and an inorganic capping layer composed of zirconia. Because of the regularity of the bilayer structure and the aligned orientation of the chromophore resulting from the self-assembly process, the present multilayers have applications in electronic devices such as thin film transistors, as well as in nonlinear optics and nonvolatile memories.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: March 1, 2016
    Assignee: Northwestern University
    Inventors: Tobin J. Marks, Young-geun Ha, Antonio Facchetti
  • Patent number: 9275871
    Abstract: A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 1, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 9269904
    Abstract: A method for manufacturing large-area organic solar cells utilizes a hot solvent vapor annealing manufacturing process while manufacturing the organic solar cells via a large-area proceeding method, such as spraying. Namely, a heated solvent vapor is utilized to modify an active layer after the active layer of the organic solar cells is formed, which ensures a flatness and an uniformity thereof and increases a crystallinity of the active layer and an element charge transport rate so that a power conversion efficiency of the large area organic solar cells is increased, a proceeding time is quite short, and the performance thereof is quite obvious. Therefore, the method not only reduces the cost by a large area production but obtains organic solar cells with higher conversion efficiency.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: February 23, 2016
    Assignee: Atomic Energy Council—Institute of Nuclear Energy Research
    Inventors: Yu-Ching Huang, Hou-Chin Cha, Fan-Hsuan Hsu, Cheng-Wei Chou, De-Han Lu, Yeong-Der Lin, Chih-Min Chuang, Charn-Ying Chen, Cheng-Si Tsao
  • Patent number: 9240319
    Abstract: Disclosed are chalcogenide-containing precursors for use in the manufacture of semiconductor, photovoltaic, LCD-TFT1 or flat panel type devices. Also disclosed are methods of synthesizing the chalcogenide-containing precursors and vapor deposition methods, preferably thermal ALD, using the chalcogenide-containing precursors to form chalcogenide-containing films.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: January 19, 2016
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Julien Gatineau, Mao Minoura, Hana Ishii
  • Patent number: 9233842
    Abstract: A method of fabricating a passivation layer and a passivation layer for an electronic device. The passivation layer includes at least one passivation film layer and at least one nanoparticle layer. A first film layer is formed of an insulating matrix, such as aluminum oxide (Al2O3) and a first layer of a noble metal nanoparticle layer, such as a platinum nanoparticle layer, is deposited on the first film layer. Additional layers are formed of alternating film layers and nanoparticle layers. The resulting passivation layer provides a thin and robust passivation layer of high film quality to protect electronic devices, components, and systems from the disruptive environmental conditions.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: January 12, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Ando Lars Feyh, Fabian Purkl, Andrew Graham, Gary Yama