Abstract: A multichannel receiver system comprises a first plurality of receiver circuits, each having a first input connected to a corresponding one of a second plurality of input lines, each being arranged to provide a corresponding one of a third plurality of received signals; a second input connected to a local oscillator arranged to provide a local oscillator signal; and an output arranged to provide a corresponding one of a fourth plurality of output signals; and an upconversion mixer having a first mixer input for receiving a reference signal; a second mixer input connected to the local oscillator; and a mixer output providing an upconverted reference signal to a fifth plurality of directional couplers, each directional coupler connected to a corresponding one of the second plurality of input lines.

Abstract: A frequency synthesizer includes: a first oscillator (1) controlled by a first control device, the first oscillator having a high quality factor that is greater than 300 and produces a first clock signal (2) RF having a fixed frequency, the first control device (30) controlling the frequency of the first controlled oscillator (1) on the basis of a first reference frequency; a second oscillator (3) controlled by a second control device and producing a second clock signal (4); the second control device (31) controlling the frequency of the second controlled oscillator (3) on the basis of a second reference frequency; and an integer frequency divider (5) dividing the frequency of the second clock signal (4) by a variable integer factor N1 and producing a third clock signal (6), the frequency of which is continuously variable by modifying the factor N1 and the control of the second oscillator.

Abstract: A system and a method in which a first frequency correction is determined for a frequency of a local oscillator with respect to a frequency of a first time slot of a received signal. The first frequency correction is applied to adjust the frequency of the local oscillator. A second frequency correction is determined for the frequency of the local oscillator with respect to a frequency of a second time slot of the received signal. The second frequency correction is applied to adjust the frequency of the local oscillator. A third frequency correction is determined for the frequency of the local oscillator with respect to a frequency of a third time slot and a fourth time slot of the received signal, and the third frequency correction is applied to adjust the frequency of the local oscillator.

Abstract: Embodiments provide a receiver and a method for receiving data transmitted via a combination of a first signal modulated at a first carrier frequency, and a second signal modulated at a second carrier frequency, different to the first carrier frequency. In one embodiment the receiver includes a local oscillator and is configured to adaptively configure the local oscillator to operate at a first local oscillator frequency and a second local oscillator frequency, different to the first frequency, in dependence on a signal strength of the first signal relative to a signal strength of the second signal.

Abstract: A method for generating phase signals includes triggering a phase register to output a binary number stored in the phase register, wherein the phase register is triggered based at least in part on a voltage signal provided by a voltage controlled oscillator. The method also includes providing an input signal to a decoder, wherein the input signal is based at least in part on the binary number output by the phase register and the decoder is operable to generate phase signals in response to the input signals. The method further includes incrementing the binary number stored in the phase register and repeating the triggering and providing steps after the binary number is incremented.

Abstract: Electronic devices contain radio-frequency receivers such as direct conversion receivers. A receiver may receive radio-frequency antenna signals from an antenna in an electronic device. The receiver may include notch filters that attenuate signals in the center of the communications channel that is being received by the receiver. An electronic device may include a clock source. The clock source may be used to clock electrical components in the electronic device. During operation, the clock source may produce radio-frequency interference signals at an associated interferer frequency. The potential for the interference signals to disrupt operation of the receiver can be reduced by configuring the electronic device so that the interferer frequency is aligned with the center of the communications channel. The clock source may be adjusted dynamically to accommodate changes in the communications channel.

Abstract: In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.

Abstract: A system and method of operating a wireless network having a plurality of nodes. Each node determines whether to replace the beacon node. When a node determines that the beacon node is to be replaced, the node determines whether it should nominate itself as a potential replacement beacon node. The decision whether to nominate itself as a potential replacement beacon node is a function of a random number generated by the node. If the node determines that it should nominate itself as a potential replacement beacon node, the node sends out one or more beacon signals. Beacon signals are received by potential replacement nodes and, if the potential replacement beacon node has received a beacon signal from a higher ranking potential replacement beacon node, the node removes itself as a candidate for the replacement beacon node.

Abstract: Disclosed is a method of adjusting the receive frequency of a radio frequency (RF) receiver die (4), the RF receiver die (4) comprising a mixer (8) with an associated local oscillator (10) and a first low-noise amplifier (6) arranged to operate over a first frequency range, the method comprising affixing a second low-noise amplifier (40) arranged to operate over a second frequency range to the RF receiver die (4).

Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.

Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.

Abstract: Efficient carrier aggregation is enabled in a receiver employing a single frequency source, and dividing the frequency source by different frequency dividing factors to generate two or more RF LO frequencies. Received signals are down-converted to intermediate frequencies by mixing with the respective RF LO frequencies. By utilizing only a single high frequency source, embodiments of the present invention avoid spurious and injection locking issues that arise when integrating two or more frequency sources, and additionally reduce power consumption as compared to a multiple frequency source solution.

Abstract: An oscillation detector having an RF oscillator configured to be synchronized with a first frequency and a comparator for distinguishing the synchronized state from the non-synchronized state of the radiofrequency oscillator on the basis of an oscillating signal produced by the radiofrequency oscillator and indicating the presence of oscillations in a frequency band around the first frequency in response to identifying the synchronized state and, in alternation, indicating the absence of oscillations in this frequency band otherwise.

Abstract: Systems and methods for sharing an oscillator between receivers are disclosed. A representative method (among others) of responding to a change in frequency of a voltage-controlled temperature-compensated oscillator (VCTCXO), includes: determining a new value for VCTCXO frequency; determining a time at which the new value will be applied to the VCTCXO; transmitting the time and the new value to a subsystem that uses a second receiver which shares the VCTCXO with a first receiver; and in the subsystem, updating channel context data to use the time of the change in frequency and the new value.

Abstract: A method and apparatus for compensating an oscillator in a location-enabled wireless device is described. In an example, a mobile device includes a wireless receiver for receiving wireless signals and a GPS receiver for receiving GPS signals. The mobile device also includes an oscillator having an associated temperature model. A frequency error is derived from a wireless signal. The temperature model is adjusted in response to the frequency error and a temperature proximate the oscillator. Frequency error of the oscillator is compensated using the adjusted temperature model. In another example, a frequency error is derived using a second oscillator within the wireless receiver.

Abstract: Embodiments related to analog front-ends for wireless and wired are described and depicted.

Abstract: According to one embodiment, an oscillator circuit includes a first comparator circuit, a second comparator circuit, a first voltage control circuit, a second voltage control circuit, a clock generation circuit. The first comparator circuit is configured to compare a first voltage with a first threshold voltage to generate a first comparison result. The second comparator circuit is configured to compare a second voltage with a second threshold voltage to generate a second comparison result. The first voltage control circuit is configured to decrease the first voltage by a first voltage value in synchronization with timing when the first comparison result changes. The second voltage control circuit is configured to decrease the second voltage by a second voltage value in synchronization with timing when the second comparison result changes.

Abstract: A system and method for dynamically swapping master and slave physical layer devices (PHYs) in energy efficient Ethernet (EEE). A physical layer communication mechanism can be used to dynamically reassign the master/slave assignments to facilitate the asymmetric application of EEE to a link.

Abstract: A radio-frequency (RF) apparatus, which may reside in a receiver or transceiver, includes receive-path circuitry. The receive-path circuitry includes a poly-phase filter and a harmonic filter. The poly-phase filter accepts an input signal and generates two output signals. One output signal of the poly-phase filter constitutes an in-phase (I) signal. The other output signal of the poly-phase filter constitutes a quadrature (Q) signal. The a harmonic filter couples to the poly-phase filter. The harmonic filter accepts as input signals the in-phase and quadrature output signals of the poly-phase filter.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: A first programmable frequency oscillator, which includes a first ramp comparator and programmable signal generation circuitry is disclosed. The programmable signal generation circuitry provides a ramping signal, which has a first frequency, based on a desired first frequency. The first ramp comparator receives the ramping signal and provides a first ramp comparator output signal based on the ramping signal. The first ramp comparator output signal is fed back to the programmable signal generation circuitry, such that the ramping signal is based on the desired first frequency and the first ramp comparator output signal. However, the first ramp comparator has a first propagation delay, which introduces a frequency error into the programmable frequency oscillator. Therefore, the first frequency is not proportional to one or more slopes of the ramping signal. As a result, the programmable signal generation circuitry compensates for the frequency error based on the desired first frequency.

Abstract: Disclosed is a radio frequency (RF) receiver for receiving a communication channel modulated on one or more carrier frequencies. The receiver may include a gain adjustable RF amplifier, a wideband signal power measurement circuit, and control logic. The control logic may be adapted to use outputs of one or more measurement circuits to classify interfering signals based on measured signal power and spectral proximity to the one or more channel carrier frequencies, and to adjust the gain of the radio frequency amplifier based on the classification.

Abstract: Disclosed is a radio frequency (RF) receiver for receiving a communication channel modulated on one or more carrier frequencies. The receiver may include a gain adjustable RF amplifier, a wideband signal power measurement circuit, and control logic. The control logic may be adapted to use outputs of one or more measurement circuits to classify interfering signals based on measured signal power and spectral proximity to the one or more channel carrier frequencies, and to adjust the gain of the radio frequency amplifier based on the classification.

Abstract: In an ADPLL circuit, on the basis of a gain of a digitally controlled oscillator estimated when a loop gain of a certain value is set in the loop filter and on the basis of a device parameter of the digitally controlled oscillator, the DCO gain estimation unit estimates a gain of the digitally controlled oscillator when a loop gain of another value is set in the loop filter.

Abstract: An apparatus includes a signal processing circuit and at least two oscillators that provide, respectively, at least first and second reference signals. The apparatus further comprise a selection circuit. The selection circuit provides to the signal processing circuit one of the first and second reference signals depending on a mode of operation of the signal processing circuit.

Abstract: A method and apparatus for non-linear frequency control tracking of a control loop of a voltage controlled oscillator (VCO) in a wireless mobile device receiver is provided. A channel metric based on one or more channel quality indicators associated with a received radio frequency channel is determined and a state metric associated with the current operating state of the control loop are determined. One or more state metric threshold value associated with the determined channel metric, providing hysteresis between operating states, are determined wherein each state metric threshold value is associated with a transition to a possible operating state of the control loop. The control loop transitions from the current operating state to the operating state associated with an exceeded state metric threshold value. Coefficients are provided to an adaptive loop filter of the control loop, wherein the coefficients coefficient are associated with the transitioned operating state.

Abstract: Systems and devices for controlling frequency drift in satellite broadcast systems. A receiver antenna system for a direct broadcast satellite signal communications system in accordance with one or more embodiments of the present invention comprises an oscillator, a mixer, coupled to the oscillator, for converting satellite signals at a first frequency to signals at an intermediate frequency, an analog-to-digital (A/D) converter, coupled to the mixer, for receiving the signals at the intermediate frequency and for converting the signals at the intermediate frequency at near-real-time to a digital data stream, a Digital Signal Processor (DSP), coupled to the A/D converter, for processing the digital data stream, and a drift estimator, coupled to the DSP, the drift estimator determining a frequency drift of the oscillator, wherein the receiver antenna system corrects the frequency drift of the oscillator using the determined frequency drift.

Abstract: A polar receiver using injection-locking technique includes an antenna, a first filter, a first voltage-controlled oscillator, a first mixer, a frequency discriminator, a second filter, a third filter, a first analog-digital converter, a second analog-digital converter and a digital signal processing unit. Mentioned polar receiver enables to separate an envelope signal and a frequency-modulated signal from a radio frequency signal received from the antenna via the injection locking technique of the first voltage-controlled oscillator and the frequency discriminator. The envelope component and the frequency-modulated component can be digitally processed by the digital signal processing unit to accomplish polar demodulation.

Abstract: Digital logic circuitry is disclosed. The circuitry includes local oscillator drift and phase compensation logic that compensates the frequency drift and the phase noise of a local oscillator generated by a digitally controlled oscillator.

Abstract: In an oscillating apparatus, a detection unit detects a frequency offset between an input signal and a reference signal. A code generation unit specifies a relationship among a code having a predetermined number of bits, the frequency offset, and a voltage to be applied to a voltage-controlled oscillator by a DAC, in accordance with a frequency offset detection state of the detection unit. The code generation unit also generates a frequency offset correction code having a predetermined number of bits in accordance with the specified relationship. The DAC applies the voltage to the voltage-controlled oscillator, in accordance with the relationship described above and the code generated by the code generation unit. The voltage controlled oscillator outputs an oscillator signal having an oscillation frequency corresponding to the voltage applied by the DAC.

Abstract: A clock generator for a mobile device, capable of operating in one of a full-power mode and a low-power mode according to a standby signal to generate a high-frequency clock signal and a low-frequency clock signal is disclosed. The clock generator includes a crystal oscillator, for generating an oscillation signal of a specific frequency according to the power mode of the clock generator; a frequency division block, for dividing the oscillation signal by a specific divisor according to the power mode of the clock generator to generate the low-frequency clock signal; and a buffer block, for amplifying the oscillation signal to generate the high-frequency clock signal; wherein during each power mode, a frequency of the low-frequency clock signal is substantially the same.

Abstract: A method and device for managing a reference oscillator within a wireless device is presented. The method includes selecting reference oscillator parameters associated with the lowest reference oscillator error, where the selection is based upon reference oscillator parameters derived using different technologies within a wireless device, acquiring a satellite based upon the selected reference parameters, determining the quality of the satellite-based position fix, and updating the reference oscillator parameters based upon the quality of the satellite-based position fix.

Abstract: A wireless communication unit comprises a frequency generation circuit employing a phase locked loop (PLL) circuit comprising a voltage controlled oscillator having a modulation port for directly modulating a signal output from the voltage controlled oscillator. The voltage controlled oscillator is operably coupled to at least one switch and a capacitor bank comprising one or more varactors. A controller is arranged to switch in one or more varactors associated with the modulation port of the phase locked loop circuit to provide an inverse cubic relationship to the direct modulated signal. In addition, or alternatively, the phase locked loop (PLL) circuit may comprise a voltage controlled oscillator having a tuning port for controlling a frequency of a signal output from the voltage controlled oscillator. The controller here is arranged to switch in one or more varactors associated with the tuning port of the phase locked loop circuit in an inverse square relationship.

Abstract: In embodiments of the present disclosure, a method may include determining an ambient temperature of an oscillator. The method may also include estimating an approximate frequency of operation of the oscillator. The method may additional include determining a process-based compensation to be applied to a resonator of the oscillator based on the approximate frequency. The method may further include setting a capacitance of a variable capacitor coupled to the resonator in order to compensate for temperature-dependent and process-dependent frequency variation of the oscillator based on the ambient temperature and the process-based compensation.

Abstract: Systems and methods are disclosed for transmitting and receiving RF signals. An exemplary RF transceiver includes a signal generator, a frequency multiplier circuit, a receiver circuit, a transmitter circuit, and a switching device. The signal generator is configured to output a first signal and a second signal. The first signal comprises a local oscillator signal, and a frequency of the second signal is derived from a frequency of the first signal. The frequency multiplier circuit is configured to upconvert the output of the signal generator by frequency multiplication. The receiver circuit is configured to process a received signal using an upconverted first signal, and the transmitter circuit is configured to provide an upconverted second signal to a transmitter channel. The switching device is configured to provide the upconverted first signal to the receiver circuit and the upconverted second signal to the transmitter circuit.

Abstract: Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.

Abstract: Embodiments provide a receiver and a method for receiving data transmitted via a combination of a first signal modulated at a first carrier frequency, and a second signal modulated at a second carrier frequency, different to the first carrier frequency. In one embodiment the receiver includes a local oscillator and is configured to adaptively configure the local oscillator to operate at a first local oscillator frequency and a second local oscillator frequency, different to the first frequency, in dependence on a signal strength of the first signal relative to a signal strength of the second signal.

Abstract: Aspects of a method and system for reducing the complexity of multi-frequency hypothesis testing using an iterative approach may include estimating a frequency offset of a received signal via a plurality of iterative frequency offset hypotheses tests. The iterative frequency offset hypotheses may be adjusted for each iteration. A correlation may be done between a primary synchronization signal (PSS), and one or more frequency offset versions of a received signal to control the adjustment of the iterative frequency offset hypotheses. A frequency of the received local oscillator signal may be adjusted based on the estimated frequency offset. One or more frequency offset version of the received signal may be generated via one or more multiplication, and the multiplication may be achieved via a multiplication signal corresponding to one or more frequency offsets. The frequency offset of the received signal may be estimated via the correlation.

Abstract: A mobile wireless communications device includes a circuit board carried by a housing. A microprocessor, RF transceiver and circuitry are carried by the circuit board and operative with each other. Clock buffer circuitry is carried by the circuit board and connected to the RF transceiver and circuitry and microprocessor for isolating a clock signal from the noise of the microprocessor and allowing greater isolation for the RF transceiver from RF circuitry.

Abstract: An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.

Abstract: Aspects of a method and system for frequency selection using microstrip transceivers for high-speed applications may include determining an operating frequency for operating one or both of a transmitter and a receiver. A frequency response and/or impedance of one or more transmission lines that may be utilized by the transmitter and/or the receiver may be controlled by adjusting one or more capacitances, communicatively coupled to the transmission lines based on the determined operating frequency. The capacitances may be coupled to the one or more transmission line at arbitrary physical spots, and may comprise capacitors and/or varactors. The capacitors and/or the varactors may be adjusted with a digital signal or an analog signal. The capacitances may comprise a matrix arrangement of capacitors and/or varactors. The one or more transmission lines may comprise a microstrip.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: Disclosed is a frequency scouting circuit with an adjustable frequency synthesizer. The scouting circuit may be collocated with other radio frequency integrated circuits on the same die. The synthesizer may include a dedicated oscillator, and the synthesizer may be adapted to generate a mixing signal at a given frequency. A channel monitoring circuit block may be adapted to determine availability of a carrier frequency corresponding to the mixing signal frequency, and control logic may be adapted to select the given frequency from a set of possible transmission carrier frequencies for a functionally associated transmitter.

Abstract: A direct-conversion transmitter with resistance to local oscillator pulling effect comprises a local oscillation circuit, a quadrature modulator connected with the local oscillation circuit, a power amplifier connected with the quadrature modulator, a first variable analog delay device connected with the power amplifier, a variable analog attenuator connected with the first variable analog delay device, an inner self-injection loop, and a power combiner connected with the variable analog attenuator and the inner self-injection loop. The local oscillation circuit comprises a two point voltage-controlled oscillator and a phase locked loop connected with the two point voltage-controlled oscillator. The inner self-injection loop comprises a second variable analog delay device, a phase shifter connected with the second variable analog delay device and a variable gain amplifier connected with the phase shifter.

Abstract: A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Abstract: A device is provided for dividing a clock signal by even and odd integers. The device includes a divider, a delay portion and a duty cycle corrector. The divider is arranged to receive the clock signal and can divide the clock signal and output a divided clock signal. The delay portion can output a delayed signal based on the divided clock signal. The duty cycle corrector can output a first signal based on the delayed signal and the divided clock signal.

Abstract: Systems and methods of clock generation for radio frequency receiver. In radio frequency receiver, the system requires accurate local oscillating (LO) signal and system clocks for proper operation and to ensure high quality performance. In order to achieve accurate LO frequency and system clock, a crystal or and accurate reference clock is provide to the clock generation circuit. How a low-cost receiver, it is desirable to eliminate the requirement for a crystal or an accurate reference clock. The present invention discloses systems and methods to utilize a pilot signal embedded in the transmitted signal. The pilot signal usually has very accurate frequency which is particular true for broadcast system such as FM broadcast. In various embodiments of the present invention, the systems and methods measure the relation between the frequency of the pilot signal and the current clock generated.

Abstract: An oscillator circuit having a source of an oscillating signal, a tank circuit including an inductor and a capacitor, and a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit. The discretely switchable capacitance module includes, in one embodiment, a capacitor coupled between a first node and a second node, a switch, having a control node, coupled between the second node and a third node; and a DC feed circuit, having a first end coupled to the second node and a second end configured to receive a first or second control signal. The control node of the switch is tied to a predetermined bias voltage. When the first control signal is applied, the capacitor is coupled between the first node and the third node via the switch such that the capacitor is coupled in parallel with the capacitor of the tank circuit, and when the second control signal is applied the capacitor is decoupled from the tank circuit.