Abstract: A radio-frequency (RF) receiver device for a wireless communication system includes a first filter for filtering out a first RF signal within a first frequency band, a first frequency converter for using a first oscillating signal to convert the first RF signal of the first frequency band to generate a second RF signal, a second filter for filtering out a second RF signal within a second frequency band, a second frequency converter for using a second oscillating signal to convert the second RF signal of the second frequency band to generate a third RF signal, a third filter for filtering out a third RF signal within a third frequency band, and a controller for controlling the first frequency converter and the second frequency converter.

Abstract: A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation.

Abstract: In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e.g., equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Abstract: A method for receiving a signal having a succession of symbols, transmitted by a digital modulation, each symbol transmitted having a phase and an amplitude belonging to a set of values in finite number, the method includes evaluating a phase error (PHE) on a received symbol (S), resulting from a signal transmission noise, correcting the phase of the received symbol according to the phase error evaluated, demodulating the symbol corrected in phase, and modeling the transmission noise by a Gaussian component not correlated with the signal received and defined by a power and an interference component defined by an amplitude and which phase is substantially uniformly distributed, the phase error of the received symbol evaluated on the basis of the power of Gaussian component and the amplitude of the interference component.

Abstract: A method of mitigating interference in a mobile wireless communication device by adaptively adjusting transmit power levels of a wireless cellular transceiver. A receive signal quality for a wireless non-cellular transceiver that includes interference from signals transmitted by the wireless cellular transceiver is estimated. The wireless non-cellular and wireless cellular transceivers are co-located in the mobile wireless communication device, and both transceivers are active. An actual transmit power of the wireless cellular transceiver is adjusted based on the estimated receive signal quality to a level less than a requested transmit power. The estimation of the receive signal quality and the adjusting of the actual transmit power is periodically repeated. The estimation accounts for operational properties of the wireless cellular and non-cellular transceivers as well as operational characteristics of wireless connections through the transceivers.

Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device.

Abstract: A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

Abstract: A receiving device of a dual polarization transmission system includes: a receiver that receives an RF signal that is transmitted with the use of two orthogonal polarizations; two reception local oscillators that include PPL circuits to convert the received RF signal of each of the polarizations into an IF signal; and a demodulator that demodulates an IF signal of one polarization, which is obtained by the conversion, into a baseband signal. The reception local oscillators control a loop band of the PLL circuits in response to a signal from the demodulator.

Abstract: An apparatus for digitally controlling the launch of high-power broad-band RF waves with high linearity for use with a software defined air-interface system. A wave launcher contains an Eplane array containing a plurality of Epixel partition elements is configured with a master digital controller. The master digital controller processes all signals to be launched as RF waves and develops the digital images necessary for digital synthesizers to format the signals to be converted to analog. A plurality of digital-analog converters coupled with power amplifiers convert the digital signal to analog, and the analog signal is then sent to the partition elements to be transmitted as RF waves.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to generate a synthesized frequency signal from the reference signal. The synthesized frequency generation logic comprises programmable divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period substantially equal to N times that of the reference signal, where N comprises a programmable integer value. The synthesizer frequency generation logic is arranged to generate the synthesized frequency signal comprising a frequency with a period substantially equal to 1/M that of the divided signal, where M comprises a further programmable integer value.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltage based upon an add signal and a subtract signal. A threshold generator generates a high threshold voltage and a low threshold voltage using and including at least one process dependent resistor and at least two temperature and process dependent current sources. The PLL responds during calibration to the control voltage being above the high threshold voltage by asserting the add signal directing the capacitor array to increase the capacitive load on the control voltage line, and to the control voltage being below the low threshold voltage by asserting the subtract signal to decrease the capacitive load.

Abstract: In accordance with various exemplary embodiments of the present invention, systems, methods and devices are configured to facilitate RF envelope amplitude control. For example, a RF envelope amplitude control system comprises: a RF amplifier, wherein the RF amplifier is associated with a feedback device that is configured to create a first feedback signal representing the power in an RF output signal; a transmit waveform generator configured to generate a reference waveform signal; an adaptive table waveform generator configured to compare the reference waveform signal and the first feedback signal and to create a second feedback signal based on that comparison; and a loop filter configured to combine the reference waveform signal, the first feedback signal, and the second feedback signal to form an amplifier control signal, wherein the amplifier control signal is provided to the RF amplifier to adjust the RF output signal to conform to a specified RF envelope.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: In an ADPLL circuit, on the basis of a gain of a digitally controlled oscillator estimated when a loop gain of a certain value is set in the loop filter and on the basis of a device parameter of the digitally controlled oscillator, the DCO gain estimation unit estimates a gain of the digitally controlled oscillator when a loop gain of another value is set in the loop filter.

Abstract: A receiver includes a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesired signals that may be present in the output signal of the mixer. The received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and generate a feedback signal in response. The control loop is adapted to vary its bandwidth in response to the feedback signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer.

Abstract: A method and apparatus for non-linear frequency control tracking of a control loop of a voltage controlled oscillator (VCO) in a wireless mobile device receiver is provided. A channel metric based on one or more channel quality indicators associated with a received radio frequency channel is determined and a state metric associated with the current operating state of the control loop are determined. One or more state metric threshold value associated with the determined channel metric, providing hysteresis between operating states, are determined wherein each state metric threshold value is associated with a transition to a possible operating state of the control loop. The control loop transitions from the current operating state to the operating state associated with an exceeded state metric threshold value. Coefficients are provided to an adaptive loop filter of the control loop, wherein the coefficients coefficient are associated with the transitioned operating state.

Abstract: A pixel clock generator includes a frequency divider 4 that generates a pixel clock PCLK based on a high frequency clock VCLK, a comparator 5 that calculates an error Lerr in the time obtained by integrating a cycle of the pixel clock PCLK for a target number RefN from a time when synchronization signals SPSYNC and EPSYNC are detected, a filter 6, and a frequency calculating unit 7 that sets a frequency dividing value M of the frequency divider 4. The filter 6 and the frequency calculating unit 7 calculate an average of a frequency of the pixel clock PCLK based on the error Lerr, determine a reference error value from the error Lerr in N-cycles, calculate offset values of the frequencies of N pieces of pixel clocks PCLK based on a difference between the reference error value and the error Lerr, and calculate the frequency dividing value M based on a result obtained by adding the circularly selected offset values and the average of the frequency of the pixel clock PCLK.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.

Abstract: An oscillator is described, comprising at least one transistor having a first terminal connected to a power supply voltage. The oscillator comprises at least one inductive element connected to a second terminal of the transistor and to a bias voltage and at least one capacitive element coupled between a third terminal of the transistor and ground. The oscillator further comprises means to collect the output signal of the oscillator on the second terminal of the transistor. The oscillator is of the millimeter wave type, i.e., both the inductive element and the capacitive element are sized such that the oscillation frequency is between 30 and 300 gigahertz.

Abstract: In an oscillating apparatus, a detection unit detects a frequency offset between an input signal and a reference signal. A code generation unit specifies a relationship among a code having a predetermined number of bits, the frequency offset, and a voltage to be applied to a voltage-controlled oscillator by a DAC, in accordance with a frequency offset detection state of the detection unit. The code generation unit also generates a frequency offset correction code having a predetermined number of bits in accordance with the specified relationship. The DAC applies the voltage to the voltage-controlled oscillator, in accordance with the relationship described above and the code generated by the code generation unit. The voltage controlled oscillator outputs an oscillator signal having an oscillation frequency corresponding to the voltage applied by the DAC.

Abstract: A television broadcast receiving apparatus can change an oscillation frequency of a local oscillation signal or a tuning frequency of an intermediate frequency signal in a reception channel, and changes the reception characteristic to an optimum reception characteristic. In this way, the television broadcast receiving apparatus effectively reduces SN ratio deterioration due to interference of the outside of a reception band such as adjacent channel interference.

Abstract: A frequency signal generator includes a controller for generating a frequency generation signal, a reference frequency signal generator for generating a first frequency signal and generate a second frequency signal by dividing a first frequency signal from the controller, an assistance frequency signal generator adapted to generate a third, fourth, and fifth frequency signals and to output a sixth frequency signal in response to an assistance frequency select signal, a mixer for selecting a sign of the sixth frequency signal in response to a sign select signal and generating a seventh frequency signal and a eighth frequency signal by mixing the sixth frequency signal of the selected sign and the first frequency signal, a switch adapted to output the seventh or eighth frequency signal in response to a dividing select signal, and a first divider outputting a ninth frequency signal by dividing the eighth frequency signal from the switch.

Abstract: A wideband receiver for a wireless communication system and a method for controlling the same are provided. In the wideband receiver for a wireless communication system, a receive path includes a mixer for receiving a Radio Frequency (RF) signal having a frequency fSG and for converting the RF signal into an Intermediate Frequency (IF) signal having a frequency fIF by mixing the RF signal with a first local oscillation signal having a first local oscillation frequency fLO1, and at least one Phase Locked Loop (PLL) for providing the local oscillation signal to the mixer. A control block determines whether a half-IF signal having a center frequency of fSG?fIF/2 exists in the IF signal, and when the half-IF signal exists, controls the at least one PLL to generate a second local oscillation signal having a second local oscillation frequency fLO2 greater than the first local oscillation frequency fLO1.

Abstract: According to one embodiment, a register outputs a first control code in first and second operation modes, saves the first control code as a third control code at an end of the first operation mode, and outputs the third control code at a beginning of a third operation mode. In the first operation mode, a digital-to-analog converter supplies a control signal with a control voltage to a voltage controlled oscillator. In the second operation mode, the control signal is supplied to a buffer amplifier, the amplifier drives a bandlimiting filter, and the filter generates the control voltage. In the third operation mode, the control signal is supplied to the filter, and the filter generates the control voltage.

Abstract: A high performance and cost effective method of RF-digital hybrid mode power amplifier systems with high linearity and high efficiency for multi-frequency band wideband communication system applications is disclosed. The present disclosure enables a power amplifier system to be field reconfigurable and support multiple operating frequency bands on the same PA system over a very wide bandwidth. In addition, the present invention supports multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels.

Abstract: Methods and systems for programmable baseband filters supporting auto-calibration in a mobile digital cellular television environment are provided. Aspects of the method may include generating within a single-chip multi-band RF receiver, at least one control signal based on signal strength of a baseband frequency signal generated within the single-chip multi-band RF receiver. A bandwidth of a filter integrated within the single-chip multi-band RF receiver may be adjusted via the generated at least one control signal. The filter may be used for filtering the generated baseband frequency signal. A frequency response signal of the filter integrated within the single-chip multi-band RF receiver may be determined via a reference frequency signal. An attenuated reference frequency signal may be generated by attenuating the reference frequency signal. The attenuated reference frequency signal may be compared with the frequency response signal. The at least one control signal may be generated based on the comparison.

Abstract: A multimedia conferencing system includes a loud speaker system, one or more microphones for receiving a local audio signal and a remote audio signal, a state machine and an echo canceller that operates in conjunction with two reference signals to remove substantially all of a feedback signal component in the local audio signal that results from reinforcing and playing the local audio signal over the loud speaker system. The state machine operates to detect that only the local audio is active, and if so controls the operation of the echo canceller such that only the feedback component of the local audio signal is removed and the local audio signal is not suppressed.

Abstract: One embodiment of the present invention relates to a system that provides a high frequency local oscillator (LO) signal. The system comprises a first LO that generates a first frequency LO signal component, a mixer that generates a difference signal from the first frequency LO signal component and a second frequency LO signal component, and a second LO that generates the second frequency LO signal component that is a harmonic of the difference signal.

Abstract: A system including a first frequency divider, a plurality of second frequency dividers, and a control module. The first frequency divider includes a first plurality of components and is configured to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of the plurality of second frequency dividers includes a second plurality of components and is configured to divide the input frequency of the input signal to generate a second signal having the first frequency and a second phase. The control module is configured to connect the second plurality of components of one of the second frequency dividers to the first plurality of components of the first frequency divider.

Abstract: A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

Abstract: A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

Abstract: A wireless transmission system for multimedia information having plural layers includes a base station (BTS) and a mobile station (MS) that can select which layers to transmit based on reported channel conditions, mobile location, and/or forward error correction (FEC) used for a particular layer. A respective FEC rate and/or power level can be dynamically established for each layer by a mobile station dependent on available bandwidth and/or reception and decoding capability of the BTS.

Abstract: Digital transmitters having improved characteristics are described. In one design of a digital transmitter, a first circuit block receives inphase and quadrature signals, performs conversion from Cartesian to polar coordinates, and generates magnitude and phase signals. A second circuit block (which may include a delta-sigma modulator or a digital filter) generates an envelope signal based on the magnitude signal. A third circuit block generates a phase modulated signal based on the phase signal. The third circuit block may include a phase modulating phase locked loop (PLL), a voltage controlled oscillator (VCO), a saturating buffer, and so on. A fourth circuit block (which may include one or more exclusive-OR gates or an amplifier with multiple gain states) generates a digitally modulated signal based on the envelope signal and the phase modulated signal.

Abstract: An on-board communication device and a cooperative road-to-vehicle/car-to-car communication system that are adaptable to a road-to-vehicle communication system and a car-to-car communication system. The on-board communication device includes a car-to-car communication transfer service processing section, a car-to-car communication management service processing section, an application processing section, a transaction managing section, a transfer service processing section, a transmission/reception service processing section, and a transmission/reception service managing section, in which the car-to-car communication transfer service processing section and the car-to-car communication management service processing section include interfaces to the transfer service processing section that is an existing road-to-vehicle communication protocol.

Abstract: A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit.

Abstract: A wireless identification system can include a directed-energy device configured as a reader. The reader can include a charged particle generator configured to generate energized particles and a charge transformer configured to receive the energized particles that include charged particles from the charged particle generator and to output a wavefront including energized particles that include particles having substantially zero charge. The system can also include an identification tag configured to be activated when impinged by the wavefront from the reader so as to transmit a signal configured to be used by the reader. A method of using a directed-energy device as a tag reader in a wireless identification system can include generating a wavefront that includes particles at substantially zero charge, impinging an identification tag with the wavefront so as to activate the identification tag so as to send a signal and detecting a signal transmitted by the identification tag.

Abstract: A frequency synthesizer includes a phase-locked loop circuit having an output. A frequency divider is connected to the output of the phase-locked loop circuit for receiving the signal therefrom and dividing the frequency of the signal. A tunable bandpass filter is connected to the frequency divider and is tuned for selecting a harmonic frequency to obtain a fractional frequency division for a signal output from the phase-locked loop circuit.

Abstract: A device for double frequency transposition includes means for controlling the frequencies FOL1, FOL2 of a first and a second synthesizer, which are adapted to carry out the steps of (a) initializing the frequency FOL2 at a first given value FOL2,A; and (b) for a given pair of frequencies FRF, FFI2, determining the frequency FOL1 with the aid of the following relations: if FRF>FOL1 and FFI1<FOL2, FRF=FOL1+FOL2?FFI2??(5), if FRF>FOL1 and FFI1>FOL2, FRF=FOL1+FOL2+FFI2??(6), if FRF<FOL1 and FFI1>FOL2, FRF=FOL1?FOL2?FFI2??(7), if FRF<FOL1 and FFI1<FOL2, FRF=FOL1?FOL2+FFI2??(8); and (c) if the value obtained for FOL1 lies in a frequency band of lower bound A·FREF?B·X and upper bound A·FREF+B·X, where A is a strictly positive integer and X is a given parameter, modifying the frequency FOL2 to a second value FOL2,B determined so that the difference in absolute value between FOL2,A and FOL2,B satisfies the following two conditions: |FOL2,B?FOL2,A|>AFREF+2B·X |FOL2,B?FOL2,A|<AFREF

Abstract: Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

Abstract: A receiver is provided. The receiver includes a differential amplifier amplifying differential input signals input to input terminals and outputting differential output signals through output terminals and an oscillator connected to the output terminals of the differential amplifier. The differential amplifier and the oscillator operate alternatively in response to an enable signal.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage.