Abstract: A chopped intermediate frequency (IF) wireless receiver is disclosed. The wireless receiver includes a local oscillator (LO), a first and a second mixers, an LO frequency control module, an IF filter, a digital down converter and a down conversion controller. The LO provides a local oscillating signal to the first and second mixers. The first and second mixers converts a received radio frequency signal to an in-phase IF signal and a quadrature IF signal, respectively. The LO frequency control module alternately down converts a channel frequency by changing an oscillation frequency of the LO. Coupled to the digital down converter, the down conversion controller adjusts a complex sine wave within the digital down converter while the in-phase IF signal and the quadrature IF signal are being down-converted by the digital down converter to a baseband signal.

Abstract: The present invention provides an apparatus for compensating a phase difference of a receiver, the apparatus including: an accumulating unit for accumulating a radio frequency (RF) input signal and generating an accumulated RF signal in order to minimize an effect of a background noise of the RF input signal; a early-local oscillating unit for generating a phase-early local oscillated signal based on a local oscillated signal of the receiver; a late-local oscillating unit for generating a phase-late local oscillated signal based on a local oscillated signal of the receiver; a phase early-late compensating unit for compensating a phase early-late based on the accumulated RF input signal and the phase-early and phase-late local oscillated signals; a look-up table data mapping unit for controlling a phase of the local oscillated signal with respect to a phase difference; and a feedback transmitting unit for transmitting a phase compensating data to the local oscillator.

Abstract: An adaptive dc compensation technique (100) eliminates dc error for both digital and constant envelope modulation protocols (108). For analog modulation, a dc averaging technique utilizes piece-wise continuous dc averaging (110) that calculates discrete dc error values over a variable number of samples (112) and updates the dc compensation value as a fixed value for a specified sample length (114). The piece-wise “update-and-hold” technique (110) results in a pseudo high pass filter response with an equivalent corner. For digital modulation, a continuous high pass filter section of the receiver is enabled (120).

Abstract: A direct conversion receiver includes a local oscillator for generating a sinusoid, a mixer for receiving an incoming signal and for mixing the incoming signal with the sinusoid, an analog-to-digital converter for converting the mixed analog signal into a digital signal, and a digital signal processor for outputting the digital signal so that an I-channel signal and a Q-channel signal are output separately and for transmitting to the local oscillator a phase control signal that determines the phase of a sinusoid to be generated by the local oscillator. The direct conversion receiver may further include a low noise amplifier for amplifying the incoming while preventing noise included in the input signal from being amplified, a baseband amplifier for amplifying the mixed analog signal in a baseband, and a baseband low pass filter for removing low frequency noise from a signal amplified by the baseband amplifier.

Abstract: Aspects for measuring receiver mixer IQ mismatch in a transceiver are described. The measuring includes providing a training signal for a receiver mixer, the training signal having periodic, uncorrelated I and Q signals. A phase mismatch in the receiver mixer is determined from IQ correlation over a unit period. A gain mismatch in the receiver mixer is determined from a power estimate of both I and Q signal for the unit period.

Abstract: A direct conversion receiver (DCR) calibrated for phase and gain mismatch is provided. The DCR comprises a poly-phase filter that generates mismatched in-phase and quadrature-phase differential signals; the in-phase differential signal is mixed with first and second local oscillation signals; the quadrature-phase differential signal is mixed with third and fourth local oscillation signals; the first and second local oscillation signals have a first adjustable phase mismatch, and the third and fourth oscillation signals have a second adjustable phase mismatch; A mismatch estimation unit (MEU) estimates the entire phase/gain mismatch (signal distortion) of the DCR, The first and second adjustable phase mismatches are adjusted so that the signal distortion of the DCR, as estimated by the MEU is minimized. Thereafter, reduced-component DCRs (without an MEU), calibrated for the mismatches of a poly-phase filter, may be mass produced.

Abstract: In a radio apparatus, the band of a loop filter of a synthesizer in a blank channel searching state is narrower than the band in a communicating state. In addition, a radio wave environment is measured. A characteristic necessary for the radio apparatus is determined corresponding to the measured-radio wave environment. The power is controlled corresponding to the performance of the radio apparatus. Thus, the power consumption is decreased. In addition, the efficiency of the output power is improved. In the radio apparatus, the current consumption of a power amplifier PA is measured. A matching circuit (LNA or MIX) of the antenna is adjusted with the measured result so as to decrease an antenna loss. In the radio apparatus, a DC offset is removed from the transmitted power and the reflected wave. When the DC offset is removed using an AC coupling capacitor, the deterioration of the frequency characteristic of the receiving portion is compensated with a capacitor in a digital signal process.

Abstract: A determining section (18) and gain variation amount detecting section (9) detect a period having a possibility of a DC-component offset in an internal circuit of a direct conversion receiver increasing beyond an allowable value due to AGC operation, and during the period, a cut-off frequency of each of high-pass filters (12a to 12d) is set at a frequency higher than that in general operation, thereby rapidly converging transient responses of signals passed through the high-pass filters, while controlling precisely operation timings of reception power measuring section (16), gain calculating section (22), gain control section (23) and circuit power supply control section (24) composing an AGC loop, whereby the DC offset is prevented from increasing and stable circuit operation is assured. It is thereby possible to achieve further reductions in size and power consumption of a CDMA receiver using the direct conversion receiver.

Abstract: A DCR RF front-end removes the DC term resulting from mixer port to port leakage and feeds RF and LO signals into the mixers with different phase combinations. The signal inputs to the mixers result in the intermediate frequency (IF) output of mixers being 180 degrees out of phase and their DC terms in phase. When subtracting the two outputs from each other the IF signals add up while the DC terms cancel giving a DC free output. A DC offset feedback tuning loop detects the DC offset in the IF domain and then feeds back the tuning voltage to current injection mixers. A multiplier cancels the IF signals and amplifies the DC offset and a comparator compares the amplified DC offset with a threshold voltage and controls the gain of current injection mixers. The feedback tuning loop thus tracks time-varying DC offsets in real-time.

Abstract: A radio communications device such as a receiver, transmitter or transceiver provides direct conversion of quadrature signals between a radio frequency signal and a plurality of resolved channels. The device provides block processing of multiple RF carriers in a wireless communication system using a direct conversion transmitter/receiver and baseband signal processing.

Abstract: A single chip radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, received signal strength indicators for adjusting frontal and rear amplification stages accordingly, and, finally, filtering circuitry to filter high and low frequency interfering signals, including DC offset.

Abstract: A direct conversion receiver including a filtering system for improving signal reception in the receiver is disclosed. In one embodiment, the direct conversion receiver comprises a first filter adapted to receive a plurality of receive signals comprising a receive band. The first filter is configured to attenuate a frequency range of the receive band to de-emphasize signals within of the frequency range. The direct conversion receiver also comprises a second filter coupled to a signal processing logic output and is configured to amplify the signals in the frequency range of the receive band, the signal processing logic being coupled to the output of the first filter and configured to substantially attenuate a plurality of unwanted signals in the receive band.

Abstract: The invention relates to a method for forming at least two intermediate frequency signals with different phases in a mixer (1), to which a first signal (RF) and a second signal (LO) are conducted. According to the method, the first intermediate frequency signal is formed by shifting the phase of the first signal (RF) and by mixing the phase-shifted first signal (RF) and the second signal (LO). The second intermediate frequency signal is formed by mixing the first signal (RF) and the second signal (LO). The phase shift of the first signal (RF) is performed in the mixer (1).

Abstract: A direct conversion receiver with DC offset compensation. The receiver includes an antenna receiving a RF signal, a mixture module converting the RF signal to a baseband signal, a gain amplifier amplifying the baseband signal, an adder subtracting a DC offset current from the baseband signal, a DC offset cancellation circuit obtaining and converting a DC offset value to the DC offset current, a track-and-hold circuit receiving the baseband signal, holding and transferring a DC offset voltage to the DC offset current, and a switching circuit alternatively coupling and decoupling the DC offset cancellation and track-and-hold circuit to receive the baseband signal.

Abstract: The invention relates to a mixing circuit for mixing a first signal RF with a second signal LO including a conversion stage T3 to convert the first signal RF into a current, a mixing core T1 and T2 to mix said current with the second signal LO, said mixing core being loaded via at least one load element ZC. Said circuit includes noise optimization means taking into account the contribution of the load element or elements ZC to the noise inversely proportional to the frequency that is present in the output signal. In particular the load elements can be selected from inductive resistors or silicon resistors or be constituted by resistors of a size selected to optimize the noise inversely proportional to frequency. The invention allows the production of mixers with very good performance at low frequency via a simple micro-electronic process of resistor forming.

Abstract: A direct conversion circuit that not only down-converts the received modulated signal using a down-converting mixer into a baseband signal, but also, after performing a passive low pass filtering to remove higher-order components, performs up-conversion of the baseband signal using an up-converting mixer. Active elements such as highly sensitive amplifiers do not operate on the baseband signal itself, but on the up-converted version of that baseband signal, thereby reducing the 1/f noise introduced by those active elements. The downstream circuitry after the up-conversion may be coupled by intervening capacitors since the downstream circuitry is operating on a higher frequency signal. Accordingly, the DC offset introduced by the downstream active elements is reduced.

Abstract: The present invention is directed to a channel calibrator and a method of calibrating in-phase and quadrature phase channels for use with a quadrature mixing receiver. In one embodiment, the channel calibrator includes a balancer and an equalizer. The balancer reduces frequency dependent imbalance between an in-phase channel and a quadrature phase channel associated with the receiver. The equalizer decreases frequency independent mismatch between the in-phase channel and the quadrature phase channel.

Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a wireless communication transmitter employs a control process to implement numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. By monitoring a plurality of parameters associated with the analog radio, such as temperature, bias current or the like, enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters may be implemented.

Abstract: A direct conversion receiver is disclosed wherein a received RF signal is mixed in a mixer with a local oscillation signal having a frequency the same as a desired central frequency, and is down-converted to a base band signal. The receiver comprises a divider for dividing the received RF signal; an adder provided at a received RF signal input side of the mixer; a phase shifter provided before the input of the mixer, for shifting a phase of the divided signal of the received RF signal; and a gain adjustable amplifier provided after the divider, and before or after the phase shifter, for amplifying the divided signal to supply the phase-shifted and amplified signal to the adder. Accordingly a DC offset due to the direct conversion can be removed and an adverse effect due to transient response when the DC offset changes can be prevented.

Abstract: A radio receiver is configurable to operate in both low-IF and zero-IF modes with maximum re-use of of analogue and digital circuitry between modes. The receiver comprises a quadrature down-converter (108,110,112,114) for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter (516) for performing image rejection filtering. In the low-IF mode, one of the outputs (Q) of the filter (516) is terminated, the other (I) is digitised by a non-complex ADC (520), then the digital signal is filtered and decimated. Quadrature-related IF signals are then re-generated before down-conversion and demodulation. In the zero-IF mode, both outputs of the filter (516) are digitised and processed in parallel before demodulation. By enabling analogue-to-digital conversion and channel filtering to be performed at low-IF on non-complex signals, use of just two non-complex ADCs (120,1620) is possible, thereby avoiding duplication of circuitry and providing significant power savings.

Abstract: A radio receiver configurable to operate in either a low-IF or a zero-IF mode comprises a quadrature down-converter (108,110,112,114) for generating in-phase (I) and quadrature (Q) signals at an intermediate frequency and a complex filter (202) for performing image rejection filtering. One of the outputs (Q) of the filter (202) is terminated, the other (I) is passed to a non-complex ADC (206). The output from the ADC is processed digitally then a quadrature signal generator (212,214) generates quadrature-related IF signals which are passed to a down-converter (216,218) for conversion to baseband signals. By enabling analogue-to-digital conversion and channel filtering to be performed at IF on non-complex signals, significant power savings are possible. Further, the flexibility of the receiver is enhanced, enabling it to operate efficiently in both low-IF and zero-IF modes.

Abstract: A receiver circuit that includes a direct conversion receiver that receives a modulated signal, and generates an in-phase differential signal and a quadrature-phase differential signal. The receiver circuit includes an in-phase branch that processes the in-phase differential signal, and a quadrature-phase branch that processes the quadrature-phase differential signal. Each branch includes an amplifier and a summer. The amplifier is configured to receive and amplify the respective in-phase or quadrature-phase differential signal. The summer receives the resulting amplified differential signal and sums the signals to generate a single signal. A log amplifier receives the summed in-phase and quadrature-phase signal, and generates an RSSI signal that is proportional to the log of the difference between the two summed signals. The data may then be extracted based on the amplitude of the RSSI signal.

Abstract: Cell search synchronization in spread spectrum communications systems using primary and second synchronization codes with symbol partitioning for shorter coherent combinations (despreading) which are combined non-coherently, and Fourier transform analysis automatically adjusts for phase rotation of the despread sub-symbols.

Abstract: A smart radio incorporating Parascan® varactors embodied within an intelligent adaptive RF front end. More specifically, this is provided for by a smart radio incorporating Parascan® varactors embodied within an intelligent adaptive RF front end that comprises at least one tunable antenna; at least one antenna null steering facility associated with said at least on tunable antenna; at least one tunable duplexer receiving the output from and providing input to said at least one antenna null steering facility; a first tunable RF filter receiving the output from said at least one tunable duplexer and providing the input to an analog to digital converter, said analog to digital converter providing the input to a digital signal processor, the output of which is input for a digital to analog converter; a second tunable RF filter receiving the analog output of said digital to analog converter and providing an input to said at least one tunable duplexer.

Abstract: A multiple-mode multiple band transceiver is disclosed. Some embodiments include a multiple-channel transmitter including a plurality of selectable transmit-channel components, the plurality of selectable transmit-channel components sharing at least one element coupled to a modulator, the plurality of selectable transmit channel components forming at least first and second transmit channels configured to generate radio-frequency signals using at least a first and a second multiple-access modulation technique, and a first switch configured to enable at least one of the first and second transmit channels to transmit a communication signal using at least one of the first and the second multiple-access modulation techniques.

Abstract: A radio frequency receiver includes an amplifier and a detector that produces a bias control signal indicating the level of the signal environment in which the receiver is currently operating. A bias generator sets the bias level of the amplifier according to the bias control signal, where the bias level tends to increase as the signal level increases. Further, the receiver, includes a first circuit adapted to receive a radio frequency input signal, the circuit having an adjustable bias level, a bias control having more than one level of control for generating a bias control signal based upon a base-band signal for controlling the first circuit and generating an output signal; and an alternative bypass switch across the first circuit so as to send a DC signal corresponding to the total power generated by said feedback means.

Abstract: A radio transceiver includes amplification circuitry that is coupled to receive a down converted signal and to provide infinite rejection of any DC component added by the down conversion circuitry. Specifically, an amplification stage includes a voltage integrator that is coupled within a feedback loop of the amplification circuitry to produce a DC charge having a magnitude that equals the added DC component but a polarity that is opposite. Accordingly, the voltage produced by the voltage integrator is added to the signal received from the down conversion circuitry to cause the amplification circuitry to merely amplify the wireless communication signals characterized by a frequency of oscillation. Logic circuitry is used for selectively coupling the voltage integrator to an output port of the amplification circuitry.

Abstract: A method and apparatus is disclosed for improving performance of a communication receiver. In one embodiment a method and apparatus is configured to process a communication signal by adjusting the amplification level of the signal and monitoring for a corresponding change in the error rate which indicates the increased error rate is caused by an interference or jammer signal. A method and apparatus is disclosed which reduces the error rate if the error rate can be reduced by activating error reducing operations. In one embodiment current flow to a mixer is increased to reduce the error rate. The apparatus may be further configured to periodically monitor the error rate during periods when error reducing operations are active. If the monitoring determines the error rate has sufficiently decreased then the receiver operation is restored to normal operation. Phase offset adjustment may also occur to further reduce the error rate.

Abstract: A half duplex radio transceiver comprises a transmitter (100) and a low IF receiver (200). The difference between the transmit frequency and the receive frequency is equal to the low IF. A common frequency generator (300) is shared between the transmitter and receiver without needing to be retuned. An upconversion signal at the transmit frequency is used for down conversion in the receiver. Transceivers at opposite ends of a communication link, such as in a master/slave network, have their transmit and receive frequencies interchanged. Optionally a transceiver may be configurable to either form e.g. as either a master of a slave station. Channel sensing for Carrier Sense Multiple Access (CSMA) may be performed on the transmit frequency without retuning the receiver.

Abstract: An automatic gain control (AGC) and DC estimation and correction technique for wireless communication devices is provided. An AGC signal, which controls a gain applied to a received signal by a gain stage to generate a scaled signal, is assigned one of a relatively small number of values in accordance with the amplitude of the scaled signal. An estimate of a DC offset in the scaled signal corresponding to each value of the AGC signal is stored in a memory. A DC estimation arrangement then reads the stored estimate associated with the particular value of the AGC signal from the memory and generates a current DC estimate based thereon. The current estimate is then used to correct the scaled signal for DC offset and to update the stored estimate.

Abstract: A radiotelephony device employing filters and methods for eliminating a DC component from an electronic signal provide for circuitry having a zero corresponding to a cut-off frequency, and circuitry for shifting the zero by an amount corresponding to the absolute value of that cut-off frequency. In such radiotelephony device, the filters and methods, which include integration and operation of gyrators, tend to be (a) suited for incorporation in integrated circuits by virtue of reducing the physical size of the required capacitors and (b) reduce time-dependent inertia.

Abstract: In a cellular telephone provided with a receiving circuit of a direct conversion type, a passive low-pass filter is arranged between a mixer for an I-channel and a base band circuit for removing interference waves of or above a channel next to a channel neighboring to the I-channel, and another passive low-pass filter is arranged between a mixer for a Q-channel and the base band circuit for removing interference waves of or above a channel next to a channel neighboring to the Q-channel. Since the low-pass filters for removing the interference waves of or above the channel next to the neighboring channel are of a differential type, the circuit scale can be small, and the power consumption is small. Since the interference waves are removed by the passive low-pass filters and the active low-pass filters, only the desired channel can be reliably received.

Abstract: A mixer circuit with image frequency rejection comprising a quadrature phase divider (30, 30?) presenting an input connected to the input (Fi) of the mixer circuit and two outputs respectively delivering two signals in phase quadrature which are applied respectively to two simple mixers (31, 32; 31?, 32?), said mixer circuit comprising a quadrature phase and frequency divider (33, 33?) having a frequency division ratio and presenting two inputs respectively connected to the respective outputs of the two simple mixers (31, 32; 31?, 32?) and a first output delivering a first output signal (Fo) of the mixer circuit, which signal is applied to the inputs of the two simple mixers.

Abstract: In a quadrature mixer circuit for receiving a radio frequency signal to generate first and second quadrature output signals, a first three-input mixer receives the radio frequency signal, a first local signal having a first frequency and a second local signal having a second frequency to generate the first quadrature output signal, and a second three-input mixer receives the radio frequency signal, the first local signal and the second local signal to generate the second quadrature output signal. The second local signal received by the first three-input mixer and the second local signal received by the second three-input mixer being out of phase by ?/2 from each other.

Abstract: The present invention relates to improvement of even order distortion noise, DC offset, and non-linearity of mixer circuits. According to the present invention, a mixer circuit is provided, which comprises a splitter for splitting an input signal to the first and second signal having phase difference of 180 degree, a local oscillator, first mixer for mixing the first signal with the local oscillation signal, second mixer for mixing the second signal with the local oscillation signal, and subtractor for subtracting the output of the second mixer from the output of the first mixer.

Abstract: In a system and method for simultaneously receiving or switching between dual frequency carrier signals in a GPS receiver, the GPS receiver is adapted to utilize different harmonics of a sub-harmonic frequency generator, which may include a lower frequency voltage controlled oscillator (VCO) to detect the L1 and L2 GPS carriers. A sub-harmonic mixer may be used to simultaneously down convert the L1 and L2 signals to a lower intermediate frequency (IF). A second mixer may be an image reject (IR) mixer used to separate the downconverted L1 and L2 signals. This mixer may be configured to simultaneously monitor the L1 and L2 signals, or to switch between the L1 and L2 signals. High frequency switching is not required of the radio frequency (RF) input or local oscillator signals, and simultaneous L1 and L2 reception is enabled without a 3 dB image noise degradation.

Abstract: A system and method are provided for direct-conversion of a modulated radio-frequency (RF) signal. After receiving an RF signal, the RF signal is mixed with a plurality of oscillator signals with different phases in an interleaving manner.

Abstract: A direct conversion quadrature receiver and method are provided according to the invention. The receiver according to one embodiment includes a primary local oscillator (LO) that down-converts a received RF signal to a quadrature intermediate frequency (IF) signal. The receiver further includes a dithering controller responsive to the quadrature IF signal generated by the primary LO. The dithering controller communicates a feedback signal back to the primary LO. The feedback signal controls the primary LO in order to offset down-conversion of the RF signal by the quadrature IF signal. The dithering controller offsets the primary LO from a zero-IF signal in order to reduce a phase and gain error of the quadrature IF signal.

Abstract: An AMPS receiver system utilizing a ZIF architecture and processing received forward link signals in the digital domain. The AMPS receiver system includes an antenna (105), a direct converter (110), high dynamic A/D converters (120,130), low pass filters (140, 150), a phase shifter (160), a digital VGA (170), a digital FM demodulator (180), an accumulator (185) and a controller (190). The direct converter (110) further includes a low noise amplifier (112), a splitter (113), mixers (114,116) and low pass filters (118,119). The controller (190) adjusts the gains of the low noise amplifier (112) and the digital VGA (170) based on the average power of the signal outputted by the digital VGA (170).

Abstract: The application of a non-zero voltage offset to rotating capacitors 1111 and 1112 permit the use of a single positive voltage supply. However, the precharging of the rotating capacitors 1111 and 1112 is power inefficient. A power efficient and low-noise precharging operation is realized through the sharing of the charge on a feedback capacitor 1075 and 1080 that is significantly larger than the rotating capacitors 1111. Once a precharging operation is complete, the charge on the feedback capacitor 1075 and 1080 is refreshed from its residual charge level (rather than zero charge level) to a desired charge level.

Abstract: A receiver of the direct conversion system by which problems arising from interference between a reception signal and a local signal used by a quadrature demodulator on the reception side are moderated. Where the carrier frequency of a transmission signal is represented by ft and the carrier frequency of a reception signal by fr while the frequency interval between the transmission and reception carrier frequencies is represented by fs (=fr?ft), first and second local oscillators generate first and second local signals fLO1, fLO2 having frequencies fLO1?ft?fs and fLO2 ?2·fs, respectively. A mixer mixes the first and second local signals to generate an internal local signal which is a sum frequency component. The internal local signal is supplied to a quadrature demodulator of the reception side. The mixer and a band-pass filter are formed in the same LSI chip as the quadrature demodulator.

Abstract: In a telecommunications transmitter and receiver two IQ-mixers of the same type are operated in 180 degrees phase shift. In both the transmitter and receiver, an input signal is coupled to each IQ-mixer and the output signal of the mixers are combined so as to cancel unwanted error components in each individual output signal. In the transmitter, residual carrier signals are cancelled, and in the receiver, DC-offsets are cancelled. In both, the wanted signals are added, doubling the amplitude of the resultant output signal leading to four times more output power and improved dynamic range.

Abstract: A passive harmonic switch mixer is shown that is immune to self mixing of the local oscillator greatly reducing leakage noise, pulling noise, and flicker noise when used in a direct conversion receiver or direct conversion transmitter circuit. The passive harmonic switch mixermixes an input signal received on an input port with an in-phase oscillator signal and a quadrature-phase oscillator signal and outputs an output signal on an output port. Because the quadrature-phase oscillator signal is the in-phase oscillator signal phase shifted by 90 °, the passive harmonic switch mixer operates with a local oscillator running at half the frequency of the carrier frequency of an RF signal. Additionally, because the passive harmonic switch mixer has no active components, the DC current passing through each switch device is reduced and the associated flicker noise of the mixer is also greatly reduced.

Abstract: An image rejection mixer of reduced power dissipation includes a signal distributor supplied with local signals having a phase difference to distribute the local signals, a first and a second signal mixer for mixing the distributed local signals and RF signals having a phase difference and outputting respective IF current signals, a phase shifter for shifting in phase the respective mixed IF current signals so as to provide them with a relative phase difference of 90 degrees, and a signal adder for adding the respective phase shifted intermediate frequency current signals. The shifter shifts the phases of the respective IF current signals outputted from the first and the second signal mixers.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

Abstract: A radio frequency (RF) integrated circuit (IC) includes a local oscillation module, analog radio receiver, analog radio transmitter, digital receiver module, digital transmitter module, and digital optimization module. The local oscillation module is operably coupled to produce at least one local oscillation. The analog radio receiver is operably coupled to directly convert inbound RF signals into inbound low intermediate frequency signals based on the local oscillation. The digital receiver module is operably coupled to process the inbound low IF signals in accordance with one of a plurality of radio transceiving standards to produce inbound data. The digital transmitter is operably coupled to produce an outbound low intermediate frequency signal by processing outbound data in accordance with the one of the plurality of radio transceiving standards. The analog radio transmitter is operably coupled to directly convert the outbound low IF signals into outbound RF signals based on the local oscillation.

Abstract: This patent describes a method of removing the LO-leakage and 1/f noise problems associated with direct conversion RF receivers and other demodulators. In order to solve this problem a virtual LO™ signal is generated within the RF signal path which is tuned to the incoming RF signal. The virtual local oscillator (VLO) signal is constructed using signals that do not contain a significant amount of power (or no power at all) at the LO frequency. Any errors in generating the virtual LO signal are minimized using a closed loop correction scheme.

Abstract: A method and arrangement for receiving a frequency modulated signal, includes mixing the frequency modulated signal into a low-frequency signal, detecting the falling and rising edges of said low-frequency signal and forming a second signal on the basis of the edge detection, where the frequency of the second signal is twice the frequency of the low-frequency signal, and frequency detecting the second signal to form a demodulated signal.

Abstract: A RF down/up-conversion circuit comprising: 1) a local oscillator chopping circuit comprising: a) a frequency divider circuit for receiving a first local oscillator (LO) signal having a frequency of LO and generating a frequency-divided second local oscillator (LO) signal having a frequency of LO/N and synchronized with the first LO signal; and b) a multiplier for receiving the first and second LO signals and generating a product signal of the first and second LO signals; and 2) a differential radio frequency (RF) mixer having a first differential input port for receiving the product signal from the multiplier and a second differential input port for receiving a first differential modulated radio frequency (RF) signal and a second differential modulated radio frequency (RF) signal, wherein the differential RF mixer generates a differential output signal.