Circuit Tuning (e.g., Potentiometer, Amplifier) Patents (Class 702/107)
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Patent number: 7777497Abstract: Embodiments describe methods of correcting S-parameter measurements for a DUT. The method includes coupling at least one tracking module associated with a set of electrical standards to a S-parameter measurement device to form a test system. An initial calibration for the test system is then determined. This may include measuring the S-parameters of the electrical standards, generating a calibration along a calibration plane, generating a calibration along a correction plane and determining at least one error adapter from the calibrations. The DUT is coupled to the test system and the S-parameters of the DUT are measured. Changes in the initial calibration are tracked using the tracking modules. Tracking may include measuring the S-parameters of the electrical standards, generating a correction plane calibration and generating a corrected calibration plane calibration from the correction plane calibration and the error adapter(s). The measured S-parameters are corrected using the tracked changes.Type: GrantFiled: January 17, 2008Date of Patent: August 17, 2010Assignee: Com Dev International Ltd.Inventors: Xavier M. H. Albert-Lebrun, Mario Lisi, Charles Van Lingen, Robert Christopher Peach
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Patent number: 7778787Abstract: A time-of-flight PET nuclear imaging device (A) includes radiation detectors (20, 22, 24), electronic circuits (26, 28, 30, 32) for processing output signals from each of detectors (20), a coincidence detector (34), a time-of-flight calculator (38) and image processing circuitry (40). A calibration system (48) includes an energy source (50, 150) which generates an electrical or optical calibration pulse. The electrical calibration pulse is applied at an input to the electronics at an output of the detector and the optical calibration pulse is applied to a preselected point adjacent a face of each optical sensor (20) of the detectors. A calibration processor (52) measures the time differences between the generation of the calibration pulse and the receipt of a trigger signal from the electronic circuitry by the coincidence detector (34) and adjusts adjustable delay circuits (44, 46) to minimize these time differences.Type: GrantFiled: August 2, 2005Date of Patent: August 17, 2010Assignee: Koninklijke Philips Electronics N.V.Inventors: Klaus Fiedler, Michael Geagan, Gerd Muehllehner, Walter Ruetten, Andreas Thon
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Patent number: 7774152Abstract: A method of calculating node potentials in a network including current flow nodes on wirings with high precision at high speed is provided. Provided are a drive method of making voltages applied to electron-emitting devices uniform using the calculating method and an apparatus for manufacturing an image display apparatus including the electron-emitting devices. Assume that n nodes are located between one end of a wiring in which a potential DL is set and the other end of the wiring in which a potential DR is set. At a j-th node counted from the one end, when a current value flowing therefrom is Ij, a node potential is Vj, resistance elements between a terminal and a node and between adjacent nodes are R0 to Rn+1, and a resistance between both end of the wiring is Rall, the node potential Vj is calculated by the following expression.Type: GrantFiled: December 28, 2005Date of Patent: August 10, 2010Assignee: Canon Kabushiki KaishaInventor: Yasuhiro Hamamoto
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Patent number: 7770042Abstract: A microprocessor includes core logic that operates according to a core clock signal in order to execute program instructions, clock generation circuitry controllable to generate the core clock signal having one of N different possible frequencies, wherein N is more than two, and a control circuit. The control circuit, in response to a request to operate the core logic at a destination frequency, iteratively controls the clock generation circuitry to generate the core clock signal having a new frequency until the core clock signal frequency is the destination frequency. The new core clock signal frequency on each iteration is one of the N different possible frequencies monotonically closer to the destination frequency. The number of iterations is between zero and N?1 depending upon the destination frequency specified and the core clock signal frequency when the request is received.Type: GrantFiled: June 11, 2007Date of Patent: August 3, 2010Assignee: VIA Technologies, Inc.Inventor: Darius D. Gaskins
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Patent number: 7761253Abstract: Measurement of error factors of a signal source when a connection tool is connected to a signal source whether error factors of the connection tool are known or not is enabled.Type: GrantFiled: September 26, 2007Date of Patent: July 20, 2010Assignee: Advantest CorporationInventor: Yoshikazu Nakayama
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Patent number: 7742893Abstract: A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop.Type: GrantFiled: February 21, 2008Date of Patent: June 22, 2010Assignee: STMicroelectronics S.r.l.Inventors: Pierangelo Confalonieri, Riccardo Martignone, Marco Zamprogno
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Publication number: 20100145642Abstract: A meter device for measuring electrical energy is provided. The meter device includes circuitry for measuring at least one parameter of electrical energy provided to the meter device. A storage device is provided for storing at least one calibration factor for compensating for errors associated with at least one of at least one external current transformer (CT) and at least one external potential transformer (PT) that operates on the electrical energy provided to the meter device. At least one processor is provided for processing the at least one calibration factor for adjusting the measuring for compensating for the errors when measuring the at least one parameter of electrical energy.Type: ApplicationFiled: February 8, 2010Publication date: June 10, 2010Applicant: ELECTRO INDUSTRIES/GAUGE TECHInventors: Frederick Blair Slota, Andrew J. Werner
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Publication number: 20100145651Abstract: Various embodiments of self-calibration systems and methods are described. One method embodiment, among others, includes imposing an alternate test to components within the device, responsive to the imposition of the alternate test, providing test responses corresponding to the components, and substantially, simultaneously mapping each of the test responses to corresponding specification values of the components.Type: ApplicationFiled: June 27, 2006Publication date: June 10, 2010Inventors: Dong Hoon Han, Abhijit Chatterjee, Selim Sermet Akbay, Soumendu Bhattacharya, William R. Eisenstadt
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Patent number: 7734440Abstract: An improved method and apparatus for setting a trip-point temperature value for detection of an over-temperature condition in a chip when a reading from a main temperature sensor exceeds the trip-point temperature value. In one embodiment, the trip-point temperature value is set to a known temperature limit value offset by a temperature difference, ?T. ?T is calculated by taking the difference between a reading of the main temperature sensor and a reading of another temperature sensor, remote from the main temperature sensor, while a heat-generating circuit is enabled. The main temperature sensor is distal from heat-generating circuit on the chip and the remote temperature sensor is proximate the heat-generating circuit. For multiple heat-generating circuits on the chip, a ?T is determined for each of the heat-generating circuits, and the largest ?T is used to calculate the trip-point temperature value. Advantageously, the largest ?T determination may be done only once.Type: GrantFiled: October 31, 2007Date of Patent: June 8, 2010Assignee: Agere Systems Inc.Inventor: James Matthew Hattis
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Patent number: 7729874Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Corresponding method and system for calibrating the cable are also provided.Type: GrantFiled: July 18, 2007Date of Patent: June 1, 2010Assignee: Redmere Technology Ltd.Inventors: Aidan Gerard Keady, John Anthony Keane, Judith Ann Rea, Benjamin Griffin, John Martin Horan
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Patent number: 7725281Abstract: A method for automatic Pole-Zero adjustment in a radiation measurement system, the method including steps of: receiving a plurality of pulses from a radiation detector; for each of the plurality of pulses, synthesizing a multiple-peak pulse shape; and using the amplitude measurement of individual peaks in each of the multiple-peak pulse shapes to adjust the pole-zero of the radiation measurement system.Type: GrantFiled: December 20, 2007Date of Patent: May 25, 2010Assignee: Canberra Industries, Inc.Inventor: Valentin T. Jordanov
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Publication number: 20100121586Abstract: Method and practical use system for measuring the imbalance potential of an electrical installation or system comprising: i) acquiring instantaneous values of voltage (vA, vB, vC) and electrical intensity (iA, iB, iC) of each of the phases A, B, C of the installation, and breaking them down into their fundamental frequency components (vA1, vB1, vC1), (iA1, iB1, iC1); ii) obtaining effective voltage and intensity values and angles for initial phase difference between voltage and intensity, and, starting from these effective values obtaining active powers (PA, PB, PC) and reactive (QA, QB, QC) potentials for each of the phases; iii) from the active and reactive potentials, obtaining (4) a phasor imbalance potentials (?U) according to the following expression: ?U=?{square root over (2)}( p·|PA+a2PB+aPC|+ q·|QA+a2QB+aQC|) where a=1|120° and p and q are orthogonal unit phasors. The invention also relates to a device for calibrating (21) instruments for measurement instruments of this imbalance power.Type: ApplicationFiled: April 30, 2008Publication date: May 13, 2010Inventors: Antonio Cazorla Navarro, José Giner Garcia, Vicente Leon Martinez, Joaquin Montanana Romeu
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Patent number: 7716001Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.Type: GrantFiled: November 15, 2006Date of Patent: May 11, 2010Assignee: QUALCOMM IncorporatedInventors: Chong U. Lee, David Jonathan Julian, Amal Ekbal
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Method and system for performing optical proximity correction with process variations considerations
Patent number: 7711504Abstract: A method for performing optical proximity correction with process variations considerations is disclosed. The maximum aerial gradient direction for a control point associated with an edge is initially determined. Then, a variational edge placement error E?along the maximum aerial image intensity gradient direction of the control point is calculated. A determination is made whether or not |CE·n| is equal to or greater than a manufacturing grid, where n is the direction perpendicular to a segment pointing outward, and C is a constant. If |CE·n| is equal to or greater than a manufacturing grid, the edge is moved by ?CE·n.Type: GrantFiled: October 25, 2007Date of Patent: May 4, 2010Assignee: The Board of Regents, University of Texas SystemInventors: Zhigang Pan, Peng Yu -
Patent number: 7706998Abstract: Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.Type: GrantFiled: September 10, 2007Date of Patent: April 27, 2010Assignee: Rambus Inc.Inventors: Adrian E. Ong, Douglas W. Gorgen
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Patent number: 7698802Abstract: A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.Type: GrantFiled: February 8, 2008Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Steven M. Clements, William P. Cornwell, Carrie E. Cox, Hayden C. Cranford, Jr., Vernon R. Norman
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Patent number: 7693686Abstract: A sensor arrangement comprises a sensor responsive to a measurement parameter as a sensor signal and a signal processing means for the sensor signal, the signal processing means having a switching stage for comparison of the sensor signal with a comparison or switching value and for producing a switching signal in a manner dependent on the comparison. A functional stage is present, which constitutes one function of the sensor signal, is comprised in the signal processing means, such function including a time derivative of the sensor signal or a sensor signal value modified by an additive factor, and the output signal of the functional stage forming the comparison of switching value for the switching stage.Type: GrantFiled: April 12, 2007Date of Patent: April 6, 2010Assignee: Festo AG & Co. KGInventors: Dietmar Wagner, Armin Seitz
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Patent number: 7680618Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.Type: GrantFiled: September 28, 2007Date of Patent: March 16, 2010Assignee: Tektronix, Inc.Inventor: Kevin C. Spisak
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Publication number: 20100036634Abstract: A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.Type: ApplicationFiled: June 4, 2009Publication date: February 11, 2010Inventor: Sang Jin BYEON
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Patent number: 7660687Abstract: A method of increasing consistency between separate parametric measurement readings that are taken with an electron beam imaging tool at different times within a period of time, by correcting drift in the imaging tool at a time frequency that is less than a time period during which the drift is anticipated to be undesirably large.Type: GrantFiled: May 25, 2006Date of Patent: February 9, 2010Assignee: KLA-Tencor CorporationInventors: Indranil De, Mark A. McCord, David L. Adler
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Patent number: 7661051Abstract: An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.Type: GrantFiled: April 4, 2007Date of Patent: February 9, 2010Assignee: LSI CorporationInventors: Gurjinder Singh, Ara Bicakci
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Patent number: 7643956Abstract: A method and apparatus for monitoring and adjusting an analog signal of an operating circuit. The apparatus includes a control circuit, an analog-to-digital converter, and a comparator. The control circuit has an analog generator for generating the analog signal and an adjusting circuit for adjusting the strength of the analog signal. The analog-to-digital converter receives the analog signal and converts the analog signal to a digital signal. The comparator then compares the value of the digital signal to a predetermined value and generates a comparator signal. The adjusting circuit then receives the comparator signal and adjusts the strength of the analog signal based upon the value of the comparator signal. The method includes generating the analog signal, converting the analog signal to a digital signal, comparing the value of the digital signal to a predetermined value and adjusting the strength of the analog signal.Type: GrantFiled: January 3, 2007Date of Patent: January 5, 2010Assignee: Infineon Technologies AGInventor: David SuitWai Ma
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Publication number: 20090267582Abstract: A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator.Type: ApplicationFiled: April 14, 2009Publication date: October 29, 2009Applicant: EXAR CORPORATIONInventors: Aleksandar Prodic, Zdravko Lukic, Zhenyu Zhao, S. M. Ahsanuzzaman
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Patent number: 7610164Abstract: A system is provided to adjust a separation distance between a read/write sensing head and a data storage medium surface in a hard disk. The thermal expansion of the sensing head based on heat generated by power dissipated through the sensing head is precisely controlled. When electrical resistance is not accurately known, a calibration is performed in which a specific input value is matched to a predetermined reference electrical power. The matching is done through a reference voltage source, that remains at a fixed value, and a calibration factor is successively adjusted through a feedback loop until an optimum value of the calibration factor is obtained. At the conclusion of the calibration process, the feedback loop is disabled and the optimally attained value of the calibration constant is frozen. The electronic circuit to implement the proposed system is based on cost effective CMOS technology.Type: GrantFiled: October 19, 2007Date of Patent: October 27, 2009Assignee: Marvell International Ltd.Inventor: Kan Li
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Patent number: 7605728Abstract: In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as ? ? ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.Type: GrantFiled: September 13, 2004Date of Patent: October 20, 2009Assignee: NXP B.V.Inventors: Lucien Johannes Breems, Ovidiu Bajdechi
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Patent number: 7595645Abstract: Impedance adjusting transistors are once inactivated on every occasion of changing an impedance adjusting code. After restoring the potential to an initially set potential by once inactivating the impedance adjusting transistors, the state of the transistors is switched according to the impedance adjusting code. By starting the potential from the initially set potential at the time of switching the state of the transistors, no switching noise is generated. Since no switching noise is generated, a comparator always carries out stable comparison and judgment and thus there is obtained a calibration circuit that ensures stable outputs.Type: GrantFiled: October 16, 2006Date of Patent: September 29, 2009Assignee: Elpida Memory, Inc.Inventors: Hiroki Fujisawa, Hideyuki Yoko
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Publication number: 20090234612Abstract: In a parameter correction circuit in an LSI, a reference resistor element with high precision having a resistance value set to a target value is connected to an external terminal of the LSI. A constant current from a mirror circuit connected to a current supply flows through the reference resistor element. A voltage value generated in the reference resistor element is measured by a voltage measuring circuit. The constant current also flows through a variable resistor element. The resistance value of the variable resistor element is adjusted so that a voltage generated in the variable resistor element corresponds to the voltage generated by the reference resistor element.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: Panasonic CorporationInventors: Takahiro BOKUI, Kazuhiko NISHIKAWA
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Patent number: 7574317Abstract: An example embodiment provides a method for calibrating an active RC filter and RC time constant calibrator for an active RC filter. The RC time contact calibrator includes a RC timer and a calibration code generator. The RC timer outputs a holding signal based on a comparison of a first output signal and a second output signal. The holding signal output by the RC timer causes a digital count value to be compared to a digital target value. The calibration code generator generates a slope control code and a flag signal based on the comparison of the digital count value and the digital target value and outputs the slope control code as a calibration code based on the flag signal. The slope control code controls the slope of the first output signal and the slope of the second output signal.Type: GrantFiled: September 21, 2007Date of Patent: August 11, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Seung-Chan Heo
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Patent number: 7570071Abstract: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.Type: GrantFiled: February 8, 2008Date of Patent: August 4, 2009Assignee: International Business Machines CorporationInventors: Steven M. Clements, William P. Cornwell, Carrie E. Cox, Hayden C. Cranford, Jr., Vernon R. Norman
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Patent number: 7567881Abstract: A method of digitally correcting the raw output voltage from a Capacitive Voltage Transformer (CVT) with the intent to remove transient components impacting on transient accuracy of protection function. A typical CVT is represented using three parameters in the linear CVT model. A digital filter designed based on the three parameters and incorporating a dedicated mechanism to ensure numerical stability of the former. A method of self-adjusting the said filter based on system events and performed after the method has been deployed in the field and supplied from a specific CVT.Type: GrantFiled: March 30, 2007Date of Patent: July 28, 2009Assignee: General Electric CompanyInventors: Bogdan Z. Kasztenny, William James Premerlani, Iulian Raducanu
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Publication number: 20090184721Abstract: Embodiments describe methods of correcting S-parameter measurements for a DUT. The method includes coupling at least one tracking module associated with a set of electrical standards to a S-parameter measurement device to form a test system. An initial calibration for the test system is then determined. This may include measuring the S-parameters of the electrical standards, generating a calibration along a calibration plane, generating a calibration along a correction plane and determining at least one error adapter from the calibrations. The DUT is coupled to the test system and the S-parameters of the DUT are measured. Changes in the initial calibration are tracked using the tracking modules. Tracking may include measuring the S-parameters of the electrical standards, generating a correction plane calibration and generating a corrected calibration plane calibration from the correction plane calibration and the error adapter(s). The measured S-parameters are corrected using the tracked changes.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Inventors: Xavier M. H. Albert-Lebrun, Mario Lisi, Charles Van Lingen, Robert Christopher Peach
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Patent number: 7561979Abstract: A method for calibrating a data processing apparatus to set a target firmware trim value is disclosed. The data processing apparatus is for converting a non-test pattern to a non-test output according to the target firmware trim value under a normal mode. The method includes: driving the data processing apparatus to convert a test pattern into a test output according to a test firmware trim value received under a calibration mode; and analyzing the test output to tune the test firmware trim value outputted to the data processing apparatus, and controlling the data processing apparatus to store a specific test firmware trim value as the target firmware trim value when an analysis result of the test output generated in reference to the specific test firmware trim value indicates that a predetermined criterion is met.Type: GrantFiled: May 10, 2007Date of Patent: July 14, 2009Assignee: MediaTek Inc.Inventors: Hsiang-Sung Huang, Kuo-Pin Lan, Yuan-Chung Lee, Chien-Ming Chen, Pin-Huan Hsu
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Patent number: 7558692Abstract: A consumption current balance circuit reduces the layout area and suppresses the deterioration of accuracy of a delay time caused by a temperature variation due to a power variation of a delay circuit itself or caused by a load variation of a power supply. The consumption current balance circuit includes a delay circuit for giving a delay time to a timing pulse signal, a compensation circuit for interpolating the consumption current of the delay circuit, a ring oscillator provided in the same power supply area as the delay circuit; an output period counter for measuring the output period of the ring oscillator; and a heater circuit current amount adjusting circuit for adjusting the current amount of the heater circuit to minimize the difference in the output period between the stand-by state and the active state of the ring oscillator.Type: GrantFiled: September 14, 2005Date of Patent: July 7, 2009Assignee: Advantest Corp.Inventors: Masakatsu Suda, Satoshi Sudou
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Patent number: 7555397Abstract: A Coriolis mass flow meter and method for compensation of transmission errors of its input circuit, wherein a high accuracy of measurement is achievable by determining the transmission error of the input circuit of at least two input branches on the basis of at least one reference signal, which travels simultaneously through all input branches.Type: GrantFiled: May 31, 2006Date of Patent: June 30, 2009Assignee: Endress + Hauser Flowtec AGInventors: Matthias Roost, Robert Lalla
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Publication number: 20090164165Abstract: One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.Type: ApplicationFiled: December 19, 2007Publication date: June 25, 2009Inventors: Russell Homer, Luca Ravezzi, Hamid Partovi
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Patent number: 7552023Abstract: In a parameter correction circuit in an LSI, a reference resistor element with high precision having a resistance value set to a target value is connected to an external terminal of the LSI. A constant current from a mirror circuit connected to a current supply flows through the reference resistor element. A voltage value generated in the reference resistor element is measured by a voltage measuring circuit. The constant current also flows through a variable resistor element. The resistance value of the variable resistor element is adjusted so that a voltage generated in the variable resistor element corresponds to the voltage generated by the reference resistor element.Type: GrantFiled: December 4, 2006Date of Patent: June 23, 2009Assignee: Panasonic CorporationInventors: Takahiro Bokui, Kazuhiko Nishikawa
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Publication number: 20090157338Abstract: A method and device are disclosed for measuring potentiometric measuring probes. An exemplary method includes feeding two test voltages comprising a harmonic wave Ueg with a base frequency fg and the harmonic wave Uer with a base frequency fr into two cores of a connecting cable through voltage source impedances, respectively. The voltage between an indicating electrode and a reference electrode, and the AC responding signal resulting from the two test voltages are passed to an amplifier and further to a transfer function unit having transfer functions (Hg, Hr), an A/D converter, and a Fourier transformation unit, to calculate a potential Ux and the two test responses Ug and Ur, respectively. Two calibration responses Uehg and Uehr are determined, wherein Uehg includes a product of Ueg and Hg, and wherein Uehr includes a product of Uer and Hr.Type: ApplicationFiled: December 12, 2008Publication date: June 18, 2009Applicant: METTLER-TOLEDO AGInventor: Changlin WANG
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Patent number: 7548836Abstract: Apparatus for compensating for a coupling error in an input signal may include a blocking correction filter. The blocking correction filter is in operable connection with an AC coupling circuit. The blocking correction filter applies to the input signal a transfer function including a settling parameter and a time constant of the AC coupling circuit.Type: GrantFiled: October 27, 2005Date of Patent: June 16, 2009Assignee: Agilent Technologies, Inc.Inventor: Brian Michael Stewart
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Patent number: 7542866Abstract: Disclosed is a method and apparatus for setting threshold values for use by a radar level transmitter to detect reflected wave pulses corresponding to portions of a transmitted microwave pulse which reflect from interfaces contained in a container. The present invention estimates these threshold values based upon various parameters. Some of these parameters can relate to properties of the materials forming the interfaces while others relate to properties of the antenna and user-defined parameters.Type: GrantFiled: September 22, 2000Date of Patent: June 2, 2009Assignee: Rosemount Inc.Inventors: Eric R. Lovegren, Kurt C. Diede, Ryan R. Carlson
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Publication number: 20090138226Abstract: A method for measuring non-linear characteristics of a power amplifier is described. A calibration waveform is calculated during a testing procedure period. Amplitude characteristics of the calibration waveform at the output of the power amplifier are measured during the testing procedure period. Phase characteristics of the calibration waveform at the output of the power amplifier are measured during the testing procedure period. Pre-distortion techniques are configured based on the amplitude characteristics and the phase characteristics to be used during a normal operation period of a transmitter.Type: ApplicationFiled: April 23, 2008Publication date: May 28, 2009Applicant: QUALCOMM INCORPORATEDInventors: Revathi Sundara Raghavan, Puay Hoe See, Rema Vaidyanathan, Richard M. Schierbeck, II, Sudarsan Krishnan, Zae Yong Choi
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Patent number: 7538569Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.Type: GrantFiled: October 2, 2007Date of Patent: May 26, 2009Assignee: Analog Devices, Inc.Inventor: Andreas D. Olofsson
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Publication number: 20090125269Abstract: A test and measurement instrument and a method of calibrating the test and measurement instrument including a reference signal generator; multiple input channels; and multiple input circuits. Each input channel is coupled to a corresponding input circuit; and one of the input circuits is coupled to the reference signal generator.Type: ApplicationFiled: October 15, 2008Publication date: May 14, 2009Applicant: TEKTRONIX, INC.Inventors: Ronald Arthur ACUFF, Lester L. LARSON, Kevin E. GOSGROVE
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Patent number: 7532993Abstract: Devices including trimmable electric units and methods for providing trim values to electric units. A device includes a trimmable electric unit, at least one fuse to provide at least one first trim value, and a trim value provision unit to provide at least one second trim value, and a register. The register, which is connected to the electric unit, the at least one fuse, and the trim value provision unit, selectively stores the first and/or the second trim values and provides them to the electric unit.Type: GrantFiled: February 26, 2007Date of Patent: May 12, 2009Assignee: Infineon Technologies AGInventors: Remi Hardy, Vincent Rezard
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Patent number: 7523009Abstract: An instrument, in particular an electron microscope, has at least one user controllable operating parameter and at least one further operating parameter having a required value at least partially dependent on that of the user controllable parameter. A number of possible values of the further operating parameter are stored in a memory and each stored value corresponds to a respective possible value of the user controllable parameter. Selecting one of said stored possible values causes the instrument to be controlled accordingly. There is also provided a tuner for enabling the user to alter the selected value and updating apparatus for updating the memory accordingly, so that the adjusted value of the further operating parameter is subsequently selected from the memory if the same value of the user controllable parameter is then chosen again.Type: GrantFiled: August 12, 2003Date of Patent: April 21, 2009Assignee: Carl Zeiss NTS GmbHInventors: Dirk Preikszas, David Ralph Hubbard
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Publication number: 20090093987Abstract: A method for measuring accurate stray capacitance of automatic test equipment (ATE) and system thereof are disclosed. The method has several steps, comprising: First of all, an internal circuit is charged and discharged several times by a driver unit; Next, the internal circuit is self-discharged, and values of voltage from V1 to V2; Then, interval of self-discharge is measured; further, the interval of self-discharge is substituted into mathematical expression of R-C discharge, and a first R-C equation is obtained; Moreover, a measuring-assistant module is connected with the ATE; Then, the steps mentioned above are repeated, and a second R-C equation is obtained; Final, stray resistance and capacitance could be solved by the two simultaneous equations. Therefore, using this method to measure stray capacitance of ATE is effective and inexpensive.Type: ApplicationFiled: November 29, 2007Publication date: April 9, 2009Inventor: Cheng-Chin Ni
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Patent number: 7512506Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.Type: GrantFiled: May 31, 2007Date of Patent: March 31, 2009Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Oliver Aubel, Tom C. Lee, Deborah M. Massey, Travis S. Merrill, Stanley W. Polchlopek, Alvin W. Strong, Timothy D. Sullivan
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Patent number: 7509223Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being received by a data interface. Signal path delays are varied such that data and strobe signals received at a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration circuitry provides skew adjustment of each data signal path by determining one or more delays in each data signal path and strobe signal path based on relative timings of test signals. The rising or falling edges may be used for this alignment.Type: GrantFiled: April 13, 2007Date of Patent: March 24, 2009Assignee: Altera CorporationInventors: Yan Chong, Chiakang Sung, Joseph Huang, Michael H. M. Chu
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Patent number: 7509222Abstract: The invention is directed to various calibration techniques for calibrating an imagining device such as a display device, a printer, or a scanner. The techniques may involve characterizing the imaging device with a device model such that an average error between expected outputs determined from the device model and measured outputs of the imaging device is on the order of an expected error, and adjusting image rendering on the imaging device to achieve a target behavior. The invention can achieve a balance between analytical behavior of the imaging device and measured output. In this manner, adjustments to image rendering may be more likely to improve color accuracy and less likely to overcompensate for errors that are expected.Type: GrantFiled: May 26, 2004Date of Patent: March 24, 2009Assignee: Eastman Kodak CompanyInventor: Christopher J. Edge
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Publication number: 20090063081Abstract: An integrated circuit chip for calibrating a bridge sensor is described.Type: ApplicationFiled: August 22, 2008Publication date: March 5, 2009Applicant: ACCEL SEMICONDUCTOR (SHANGHAI) LIMITEDInventor: GANG XU
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Patent number: 7496480Abstract: System and method for specifying a signal analysis function. First user input is received, e.g., to a graphical user interface (GUI), indicating a parameter for a first operation implementing at least a portion of the function. The first operation is programmatically included in a sweep loop. Second user input is received specifying a sweep configuration for a sweep on the parameter. The signal includes signal data, e.g., signal plot data or tabular data. The sweep configuration includes: a range of values for the indicated parameter, a number of iterations for the sweep, an interpolation type, step size for the sweep on the indicated parameter, specific values in the range of values for the parameter, source for at least some of the sweep configuration, and/or resultant data. The sweep is performed on the parameter per the sweep configuration, generating resultant data which is stored, and optionally displayed, e.g., in the GUI.Type: GrantFiled: March 25, 2004Date of Patent: February 24, 2009Assignee: National Instruments CorporationInventors: Philippe G. Joffrain, Christopher G. Cifra, Alain G. Moriat, Christohpe A. Restat, John A. Pasquarette, J. Clinton Fletcher