Abstract: A testing unit is provided with a test data communication port adapted to output test data to a device being tested. The testing unit also has an expected test result data communication port adapted to output expected test result data to the device. The device being tested generates test result data in response to the test data, and compares the test result data with the expected test result data to generate test status data, such as a pass or fail indication.

Abstract: A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.

Abstract: A method and apparatus for testing the chip-to-package connectivity of a common I/O of a semiconductor chip is disclosed which uses reduced pin count testing methods. The method includes driving a test signal transition onto a control pad of a semiconductor chip with a weak driver and comparing the transition rise time with a threshold value. For an I/O with a faulty chip-to-package connection, the rise time is much faster than for an I/O with a completed chip-to-package connection. Additional impedances may also be added to the tester fixturing to increase the sensitivity of the test equipment to the capacitance of the I/O connections.

Abstract: A method and system for flexible, comprehensive, on-line, real-time dynamic lot dispatching in a semiconductor test foundry based on a two-phased, event-driven dispatching system structure. An adjustable priority formula and tuned algorithms integrated with PROMIS' constraint function give a nearly optimum dispatching list on any tester at any time with reduced mistake operations. Exception rules take care of special events to improve daily dispatching manual effort. This invention can automatically dispatch engineering lots according to engineering lots' capacity of Testing, solve conflict between wafer and package lots, efficiently reduce tester setup times, replace daily manual-dispatching sheet and keep a high CLIP rate while fully following MPS.

Abstract: Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated.

Abstract: Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.

Abstract: A printed board inspecting apparatus includes: an input unit for inputting a pulse from a first signal line; a receiving unit for receiving a voltage induced in a second signal line in response to the input pulse inputted; and a judging unit for judging whether or not a ratio between a voltage of the input pulse and the voltage induced in the second signal line is within a predetermined range. A check is made using a TDR method to determine whether or not the degree of coupling is within a range of specified values and a check is made to determine each of the voltage of the polarized RZ signal and the pulse width time is within a range of specified values to thereby inspect a printed board and a semiconductor chip constituting a bus using a directional coupler.

Abstract: An electric wiring simulation device 1 of the present invention includes an input device 2; a display 5; a characteristics information data base 4 storing parts information on parts and wirings, discharge characteristics of a power supply, current-prearcing time characteristics of protecting parts and current-smoke time characteristics of the wirings; an assigned path searching unit 11 searching an assigned path between a short-circuit point and the power supply on a test object circuit; a current value calculating unit 12 calculating a resistance value on the assigned path based on the parts information, and calculating a short-circuit value based on the resistance value and the discharge characteristics of the power supply; and a judging unit 13 judging whether or nor each protecting part is fused or etch wiring smokes based on the current-smoke time characteristics and the current-prearcing time characteristics, at unit time intervals.

Abstract: A method and apparatus for measuring a multiport device using a multiport test set connects one port of the multiport device to a stimulus signal and terminates all remaining ports in a respective load. A response to a stimulus signal is measured on all ports of the multiport device and the measured responses are corrected with calibration data to characterize the multiport device.

Abstract: Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files.

Abstract: In a semiconductor device testing apparatus for testing a plurality of semiconductor devices at one time, data peculiar to each semiconductor device can be written therein simultaneously with the avoidance of excessive enlargement in the scale of circuitry. A pair of an integer delay generation part and a fraction delay data generation part that are components of the semiconductor device testing apparatus is provided by the same number as that of pins of each semiconductor device under test, and a waveform control part is provided by the same number as that of the semiconductor devices under test for each of the pairs. In each waveform control part are generated a set pulse and a reset pulse for generating a test pattern signal to be applied to each of pins having the same attribute of the semiconductor devices under test, thereby to generate a test pattern signal.

Abstract: A semiconductor test data analysis system (1) automatically recording, during an analysis operation, operation information of the analysis operation, including analysis conditions or an analysis procedure for input test data, or analysis information obtained by the analysis operation. The analysis system includes a processing means (101), an analysis target data storage means (109), which stores the test data as analysis target data, a historical data storage means (107), which stores as historical data either operation information of the analysis operation or analysis information obtained by the analysis operation, and a display data storage means (112), which stores analysis information obtained by the analysis operation, which stores analysis display data generated by the processing means for the purpose of displaying the analysis information obtained by the analysis operation.

Abstract: A method for processing first data representing parameters relating to several components of an electrical circuit provides an associated first data record for each component. The components of the circuit are checked against specific parameters. The parameters relate to the connection of the components to networks, or to electrical/geometric characteristics of the components. The check of the “basic rules” results in the formation of binary values. The binary values are then logically linked to check an “overall rule”. One such overall rule is, for example, the rule for checking the circuit for adequate electrostatic discharge (ESD) protection. A computer readable storage medium and a data processing system, each containing computer-executable instructions for performing the method, are provided.

Abstract: A method and an apparatus for sorting between actual and perceived errors related to processing of semiconductor wafers. A plurality of semiconductor wafers are processed. Fault data relating to the processed semiconductor wafers is acquired. A trend associated with the fault data is determined. A determination is made whether the fault data relates to an actual fault associated with the semiconductor wafers or to a calibration error, based upon the trend. A component is notified of the calibration error in response to the determination that the fault data relates to the calibration error.

Abstract: An automatic tester for an analog micromirror device includes a computer having an ADC and DAC connected to its peripheral bus. A micromirror device under test is mounted on a black box containing a light source such as a laser and a position sensitive device. The light beam is reflected by the micromirror device onto the position sensitive device so that the deflection of the mirror in two axes can be measured. The output of the position sensitive device is amplified and coupled to the ADC via a tester board. The computer can test the micromirror device to detect mechanical failure and to measure the resonant frequency and Q of the driving coils, and SNR of the internal package feedback which measures the position of the mirror.

Abstract: A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.

Abstract: Building and testing complex electronic products especially large scale computer systems are handled with control remaining with the owner of the design while a contract manufacturer does the basic manufacturing processes and testing. Nearly all levels of testing are accomplished without sharing high level descriptions of the end product or its features by providing only low level files for test functions. Testing is accomplished without sharing the high level code descriptive of the system design so confidential information is retained. Testing using the low level data is made sufficient to identify what parts need repair despite the lack of high-level information transfer.

Abstract: Electrical and mechanical components and associated processes for enhancing automated test of a system by permitting automated generation and application (injection) of real-world stimuli applied to the system under test and sensing responses from the system under test without the need for manual intervention. Test components of the present invention may intercede in the exchange of signals and power over various signaling paths within a system under test. Under programmable control by methods of the invention, the electrical components of the present invention may simulate any desired real-world stimulus on any signal path associated with the system under test. Electromechanical manipulation test components and sensor components allow automation of testing of physical aspects of the system under test. Centralized test sequencing and logic enables simpler test components to permit improved scalability and flexibility of the automated test system and processes.

Abstract: A scheme for testing an electrical device to determine a range of combinations of values of N parametric variables, i.e., a SHMOO plot, for which the device functions properly. In one embodiment, the method comprises defining an N-dimensional plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N parametric variables. The plot region is successively subdivided into smaller sub-regions, based on determining whether the electrical device passes or fails upon testing at each operating point of a predetermined subset of operating points of the plot region or one of the smaller sub-regions, until a minimum resolution is achieved.

Abstract: A method and control system computing platform for a dialysis machine that uses Symmetric Multi-Processing (SMP) architecture. The SMP architecture tightly couples multiple (e.g., 2) independent processors by sharing memory between the processors. A single shared memory is used by both processors in order to facilitate communication between the processors and reduce cost by eliminating the expense of redundant memory. In this way, the two, or in general “N” processors, increase processor throughput by allowing the execution of N processes in parallel while without requiring extra memory and without having a single point of failure in the computer. In the event of a bus failure on the circuit card, the computer is reset using distributed hardware watchdogs. The watchdog reset signal is also sent to the hardware components of the dialysis machine in order to place the system in a safe.

Abstract: A method, system and software for automatically generating a test environment for testing a plurality of devices (DUTs) under test in a test system. The multiple devices are tested by mapping the plurality of DUTs into pins of the tester system to create pin data; inputting into a test program generator pattern data, generic test program rules and the pin data; generating a multi-DUT test program and multi-DUT pattern data; and controlling the test system through the test program. The resulting fail data is then logged to each DUT.

Abstract: The present disclosure relates to a method for testing a circuit having analog components. The method comprises performing a low-cost optimized test on the circuit by applying an optimized input stimulus to the circuit, capturing the circuit response to the input stimulus applied to the circuit, evaluating the circuit response to predict whether the performance parameters of the circuit satisfies predetermined specifications for the circuit, and making a pass/fail determination for the circuit based upon the evaluation of the circuit response.

Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Abstract: A control device test system including an electrical switch and a device controller, wherein the device controller has a processor, a memory coupled to the processor, and an auxiliary input coupled to the processor and adapted to receive a binary signal from the electrical switch. A routine is stored in the memory of the processor and is adapted to be executed on the processor to cause a control device test to be performed in response to the receipt of the binary signal at the input.

Abstract: A computer system linked by the internet to various remote waste water treatment facilities. The system receives real-time data from the facilities and analyzing the data to determine likely operational upsets and future effluent water quality. The computer system sends signals to a hierarchy of parties depending on the severity of predicted upsets problems and events. The computer also provides a probability distribution of such upsets and water quality and recommendations as how to adjust facility operating parameters to avoid or reduce the upsets to acceptable parameters and maintain effluent water quality parameters within preselected limits.

Abstract: The present invention provides systems and methods for margin testing of one or more components of an electronic system, such as a computer system (e.g., a server). A margin testing system of the invention can include a fault bypass module incorporated in the electronic system for masking signals indicative of faults associated with one or more components during margin testing of the system. The margin testing system can also include a controller, such as a Baseboard Management Controller (BMC), internal to the electronic system that is in communication with the fault bypass module. The controller can transmit a command to the fault bypass module to initiate masking of selected faults by that module.

Abstract: The present invention provides a margin testing system, incorporated in an electronic system (e.g., a computer system), that includes a controller, a frequency control module, and a voltage control module, and a fault bypass module. In response to commands from the controller, the frequency control module and/or the voltage control module can set a test clock frequency and/or a test voltage for application to one or more components of the electronic system to elicit system response to these test values. The response of the system at each test value can be monitored, e.g., by executing a diagnostics software, and analyzed. The fault bypass module can mask fault signals during margin testing to ensure that these signals will not disrupt margin testing of the system.

Abstract: Apparatus for electrical testing of electrical circuits includes an array of probes arranged for selective engagement with portions of electrical circuits to be tested, testing circuitry associated with the array of probes for sensing electrical characteristics of the electrical circuits engaged by the array of probes, and control circuitry associated with the array of probes for causing engagement between selected ones of the array of probes with selected ones of the portions of electrical circuits to be tested. The array of probes includes at least two static probe assemblies arranged in a fixed array, and the static probe assemblies include a selectively positionable probe element and a probe element positioner. The apparatus is employed to test electrical circuits during fabrication.

Abstract: A test tool enables the testing of multiple variable air volume (VAV) boxes from a single location in a building environmental system. The test tool includes a building level network interface and a test program for sending a test parameter to a plurality of VAV boxes so that measurements of air flow characteristics may be obtained at the plurality of VAV boxes.

Abstract: A system and method of testing a bank of modems. A test bed includes a RAS concentrator, wherein the RAS concentrator includes means for spoofing operation of a plurality of analog modems. The RAS concentrator is connected to a communication server having one or more concentrators or a bank of modems. Software is executed in the test bed to establish a plurality of simultaneously connections between the RAS concentrator and the bank of modems.

Abstract: According to one embodiment of the invention, there is provided a method of calibrating an N-port multiport test system for measurement of a DUT. The method consists of coupling each port of an N-port automatic calibration device to a respective port of the N-port multiport test system, and presenting three reflection standards with the automatic calibration device to each port of the N-port multiport test system. The method also consists of providing with the automatic calibration device, N−1 through conditions of a possible N(N−1)/2 possible through conditions, between corresponding ports of the N-port multiport test system, and making measurements with the N-port multiport test system of the three reflection standards at each port and the N−1 through conditions between the corresponding ports. The method further consists of determining all of systematic error coefficients for all of the ports of N-port multiport test system.

Abstract: A method of adaptively testing electronic circuits based on fabrication data includes steps for receiving as input fabrication data of the electronic circuits from at least one of electrical test and in-line inspection; calculating a process capability from the fabrication data; and selecting a test selection program based on the process capability to minimize testing cost and to verify performance specifications.

Abstract: The present invention to provide correctly ordered test code in order to effectively test software designs. There are software diagramming tools on the market today that capture software designs in a standard meta-language (UML). This software provides sequence diagrams that relate to the software component being analyzed. The UML sequence diagrams expose enough semantic content to allow the generation of test code correctly ordered. Since all of the objects are modeled consistently, the data requirements of the software component can also be determined. As a result, the generated test code is correctly ordered, thereby providing a more accurate, useful and real-world testing environment of the software component.

Abstract: A method of testing an electrical device to determine a range of combinations of values of N variable operating parameters for which the device functions properly is described. In one embodiment, The method comprises defining a plot region comprising a plurality of operating points each corresponding to a particular combination of values of the N variable operating parameters, selecting an operating point within the plot region, testing the device using the combination of values of the N variable operating parameters corresponding to the selected operating point, and if the device functions in a first manner at the selected operating point, adding all operating points of the plot region having a first relationship with respect to the selected operating point to a list of operating points to be tested.

Abstract: An apparatus for testing I/O ports of a computer motherboard. A non-volatile memory on a computer motherboard under test stores a test code instead of a normal BIOS code to initialize the computer motherboard under test and test its I/O ports. The computer motherboard under test is booted from the test code. For the I/O ports to be tested, a CPU on the computer motherboard under test executes test routines in the test code. The apparatus of the invention is connected to the computer motherboard under test so as to cooperate with the test routines in testing the I/O ports. Furthermore, the inventive apparatus includes connectors and test circuits for establishing electrical connections with corresponding pins of the I/O ports to be tested and checking each pin with the test routines.

Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.

Abstract: Systems for performing time domain measurements of a device under test (DUT) are provided. One such system includes a normalization system that receives information corresponding to a model of a test system used for providing differential input signals to a DUT, receives information corresponding to first and second differential input signals provided to the DUT, receives information corresponding to first and second reflected waveforms corresponding to the DUT response to the first and second differential input signals, and computes first and second normalized waveforms using at least a first inverse transfer function of the test system, the first and second normalized waveforms including fewer test system error components than the first and second reflected waveforms, respectively. Methods, computer-readable media and other systems also are provided.

Abstract: A plurality of lots of wafers, each lot of wafers having a lot number and each wafer of each lot having at least one test parameter generated by performing at least one wafer test item stored in a database, are divided into a high yield group and a low yield group. By analyzing the wafer test parameters of the wafers in the high yield group, a first standard value within a first range is obtained. A first comparison step is then performed to compare each wafer test parameter of each lot in the low yield group with the first standard value and delete lot numbers of lots with wafer test parameters within the first range. Finally, a first amount of residual lots in the low yield group is determined. In response to the first amount of residual lots in the low yield group not equaling to zero, a first searching step is performed to which item of sample test items, in-line QC items and process step items is related to the wafer test item of each residual lot in the low yield group in the database.

Abstract: A method and apparatus for measuring a multiport device using a multiport test set connects one port of the multiport device to a stimulus signal and terminates all remaining ports in a respective load. A response to a stimulus signal is measured on all ports of the multiport device and the measured responses are corrected with calibration data to characterize the multiport device.

Abstract: A method for testing I/O ports of a computer motherboard under test. A non-volatile memory on the computer motherboard under test is provided with a test code for initializing the computer motherboard and testing its I/O ports, in which the test code includes a plurality of test routines corresponding to the I/O ports to be tested. Upon power-up or reboot, the computer motherboard under test is booted from the test code in the non-volatile memory. One of the I/O ports is selected from an interactive display menu, and then a CPU on the computer motherboard under test executes the corresponding test routine for the selected I/O port to test it. If there is an abnormal signal pin in the selected I/O port, a failure message is displayed to indicate which signal pin of the selected I/O port is not operating correctly. Otherwise, a pass message is displayed.

Abstract: Disclosed are methods and apparatus for characterizing board test coverage. In one method, potentially defective properties are enumerated for a board, without regard for how the potentially defective properties might be tested. For each potentially defective property enumerated, a property score is generated. Each property score is indicative of whether a test suite tests for a potentially defective property. Property scores are then combined in accordance with a weighting structure to characterize board test coverage for the test suite.

Abstract: A method and apparatus for testing semiconductors according to various aspects of the present invention comprises a test system comprising an outlier identification element configured to identify significant data in a set of test results. The test system may be configured to provide the data in an output report. The outlier identification element suitably performs the analysis at run time. The outlier identification element may also operate in conjunction with a smoothing system to smooth the data and identify trends and departures from test result norms.

Abstract: A method and circuit for determining the accuracy of a measurement of a bit line voltage or a charge distribution for readout from FeRAM cells uses sense amplifiers to compare a bit line voltage to a series of reference voltages and then determines upper and lower limits of a range of range of reference voltages for which sensing operation provide inconsistent results. One embodiment uses an output signal of a sense amplifier to control a pull-down transistor of an I/O line and alternative precharging schemes for the I/O line allow determining both limits using the same compression circuitry to process a result value stream on the I/O line.

Abstract: A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.

Abstract: A system that includes a graphical user interface (GUI) connected to an input/output device of a computer system and one or more test instruments producing a set of electrical signals. The system also includes a probe card that has a multiple probe needles used for measuring electronic characteristics of each of the devices on a semiconductor wafer. Each device has cells. Each cell has a set of bond pads. The system also has a matrix switch and an interface conduit electrically connecting the one or more test instruments, the computer, the probe card, and the matrix switch together. The semiconductor wafer is moved so that the probe needles measure the electrical characteristics of each cell for each device selected for testing.

Abstract: A test circuit receives a plurality of internal test signals and delivers a group of the plurality of internal test signals onto a bus during an idle state of the bus. The bus is coupled to output pins so that the group of internal test signals can be used in debugging operations. The test circuit may include a multiplexing circuit that receives the plurality of internal test signals as inputs and that delivers a selected group of the internal test signals as outputs. The test circuit may also include a switch that couples the selected group of the internal test signals onto the bus during an idle state.

Abstract: Techniques to process semiconductor devices whose input-output (I/O) pins are only partially operative is able to accommodate substantially all possible combinations of operative I/O pin patterns. Semiconductor devices are tested to determine which I/O pins are operative. A code representing which I/O pins are operative is then associated with each tested device. The generated codes are used to selectively combine two or more semiconductor devices to form a component capable of providing the function of a single fully operational semiconductor device.

Abstract: An embodiment includes retrieving performance monitor data from an I/O processor. A performance monitoring driver coupled to a performance monitoring unit may be registered as a private driver with a real time operating system of the I/O processor. Events within the I/O processor may be selected on which to gather data. The selected events may be sent as a message request to the real time operating system. The message request may be translated into the appropriate parameters based on a set of private group parameters that may be accessible by the real time operating system. The message request may be sent as a translated request to the performance monitoring unit. The pieces of data requested by the translated request may be returned to the performance monitoring driver. The pieces of data then may be sent to a location specified in the message request.

Abstract: A method of connecting one or more testing devices to ports of a DUT through a switching network, to execute a testing procedure includes generating a switching network map defining connections within the switching network to implement electrical paths through the switching network. Each of the electrical paths is representative of a connection of one of the testing devices to one of the I/O ports of the DUT. The method further includes receiving commands that uniquely specify an electrical path connecting a particular testing device to a particular I/O port of the DUT. The method compares each command to the switching network map to identify a corresponding electrical path through the switching network, and implements that path associated the command through the network. The method further includes sequentially implementing the electrical paths corresponding to the one or more commands in a predetermined order.

Abstract: A virtual oven efficiently conducts stress testing of large numbers of modules. The virtual oven includes a logical grouping of modules, a controller, test instruments and a database which are all connected via a network. The logical groupings of modules of several virtual ovens may be physically accommodated within a single environmental stress screening room. Switching between modules in a logical group permits a single test piece of test equipment to be time-shared among the modules in the logical group. The method of bum-in testing a logical group of modules rotates a test sequence, including passive and active test cycles, between the modules. A test signal is split and supplied to multiple modules. Passive testing may be performed by monitoring parameters of the module while the test signal is supplied to the module. Active testing may be a functional test of the module in which the test signal is supplied to, processed by, and output from the module.