Timing Signal Patents (Class 702/125)
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Patent number: 8135557Abstract: An apparatus for testing a semiconductor integrated circuit includes an input part that inputs circuit description data that describes a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector to be used for testing a normal operation of the semiconductor integrated circuit, and a simulator that performs a simulation on the semiconductor integrated circuit with the use of a test vector.Type: GrantFiled: August 21, 2008Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yukio Kawasaki
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Patent number: 8108174Abstract: The present invention relates to process I/O controllers for semiconductor manufacturing to which a tool host can delegate data collection, monitoring and control tasks. In particular, it relates to process I/O controllers that can perform more than one of data collection, monitoring, control and response to commands from a tool host with statistically repeatable performance and precision. Embodiments described use prioritized real time operating systems to control of semiconductor manufacturing tools and data collection from tool associated with the sensors. Statistically repeatable responsiveness to selected commands and to sensor inputs during selected recipe steps effectively reduces jitter.Type: GrantFiled: November 16, 2009Date of Patent: January 31, 2012Assignee: MKS Instruments, Inc.Inventors: Leonid Rosenboim, David Michael Gosch
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Patent number: 8055969Abstract: A multi-strobe circuit that latches a signal to be tested, an evaluation target, at each edge timing of a multi-strobe signal having a plurality of edges. An oscillator oscillates at a predetermined frequency in synchronization with a reference strobe signal. A latch circuit latches the signal to be tested at an edge timing of an output signal of the oscillator. A gate circuit is provided between a clock terminal of the latch circuit and the oscillator, and makes the output signal of the oscillator pass therethrough for a predetermined period. A clock transfer circuit loads the output signal of the latch circuit at an edge timing of the output signal of the oscillator and performs retiming on the output signal of the latch circuit by using a reference clock.Type: GrantFiled: July 7, 2009Date of Patent: November 8, 2011Assignee: Advantest CorporationInventor: Noriaki Chiba
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Patent number: 8055801Abstract: A time synchronization apparatus, method and system are provided. In one aspect, the apparatus comprises at least a time of day clock, a first port operable to receive at least first time information using a first time protocol, a second port operable to receive at least second time information using a second time protocol, a third port operable to receive at least a timing signal, and a time stamp register operable to at least capture current value of the time of day clock upon receipt of the timing signal from the third port or the first time information from the first port or combination thereof.Type: GrantFiled: October 6, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Ronald M. Smith, Sr., Evangelyn Kay Gardner Smith, legal representative
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Patent number: 8041979Abstract: A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least one responding device receiving a trigger message from the initiating device. The trigger message includes a state transition time or a time from which a state transition time is obtainable. The method further includes the at least one responding device jointly making a respective state transition at the state transition time. A responding device, and a system including the initiating device and the responding device are also disclosed.Type: GrantFiled: October 29, 2007Date of Patent: October 18, 2011Assignee: Agilent Technologies, Inc.Inventors: James Adam Cataldo, Bruce Hamilton
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Patent number: 8027801Abstract: Embodiments of the invention provide a data storage device test method and data storage device manufacture method which allow a tester to perform an operation test of plural data storage devices connected thereto in a shorter period of time. In one embodiment, an operation test of each of plural HDDs 81-84 connected to a tester is performed by making plural HDDs 81-84 execute commands received from the tester, wherein, during a waiting period when exchange stops between the tester and, for example, HDD 81 of which operation test is being executed, the tester executes the operation test of another HDD. Such a waiting period occurs, for example, before HDD 81 becomes ready to receive a command, before a data transfer is completed and before HDD 81 becomes ready to receive the subsequent command. By using this waiting period, the tester issues a command to, for example, HDD 82 if the HDD is ready to receive a command or transfers data to the HDD if data transfer is possible.Type: GrantFiled: August 30, 2006Date of Patent: September 27, 2011Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Shigeto Nishiuchi, Satoshi Takahashi, Masashi Tsuyama, Takahiro Nakagawa
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Publication number: 20110231143Abstract: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: Micron Technology, Inc.Inventor: Paul A. LaBerge
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Patent number: 7996743Abstract: An integrated circuit may have a circuit under test. The integrated circuit may have a clock generation circuit that receives a reference clock from a tester and that generates a corresponding core clock. The integrated circuit may have a built in self test circuit and a clock synthesizer that receives the core clock. The built in self test circuit may provide clock synthesizer control signals that direct the clock synthesizer to produce test clock signals at various test clock frequencies. The test clock at the test clock frequencies may be applied to the circuit under test during circuit testing. The circuit under test may assert a pass signal when the circuit tests are completed successfully. The built in self test circuit may inform the tester of the maximum clock frequency at which the circuit under test successfully passes testing.Type: GrantFiled: April 1, 2008Date of Patent: August 9, 2011Assignee: Altera CorporationInventors: Tze Sin Tan, Jayabrata Ghosh Dastidar
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Patent number: 7979228Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA achieves nanosecond and sub-nanosecond time resolutions and is used in applications such as various time of flight systems.Type: GrantFiled: July 21, 2008Date of Patent: July 12, 2011Assignee: The Regents of the University of MichiganInventors: Thomas Zurbuchen, Steven Rogacki
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Patent number: 7945718Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.Type: GrantFiled: August 22, 2006Date of Patent: May 17, 2011Assignee: NXP B.V.Inventors: Ata Khan, Greg Goodhue, Pankaj Shrivastava
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Patent number: 7937232Abstract: Embodiments of the present invention relate to managing timestamps associated with received data. According to one embodiment, data is collected from a device that generates data at a specified rate, but which lacks a built-in clock. An accurate timestamp is assigned to the data by first taking an absolute timestamp from a reference clock, and then adding a calculated amount of time to each subsequent data point based on an estimate of the sampling frequency of the device. As the generated timestamp drifts from the actual reference clock time, the sampling frequency is re-estimated based on the amount of detected drift.Type: GrantFiled: June 25, 2007Date of Patent: May 3, 2011Assignee: Pivotal Systems CorporationInventors: Paxton Ming Kai Chow, Vera Alexandrova Snowball, Barton George Lane, III, Sophia Leonidovna Shtilman, Chalee Asavathiratham, Abhijit Majumdar, Sherk Chung, Yi Wang, Paul Tran
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Patent number: 7930121Abstract: Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally limited by clock speed. Here, an apparatus is provided that performs time stamp operations and is not generally limited by clock speed. This apparatus generally uses an interpolator, counter, lathing circuits, and a synchronizer. Typically, the interpolator provides a residue signal to the synchronizer, and the synchronizer can determines whether to add the interpolation signal to a counter state based at least in part on a comparison of an event signal and the residue signal.Type: GrantFiled: August 21, 2008Date of Patent: April 19, 2011Assignee: Texas Instrument IncorporatedInventors: Steven Graham Brantley, James Richard MacLean, Francesco Cavaliere
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Patent number: 7917319Abstract: Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.Type: GrantFiled: February 6, 2008Date of Patent: March 29, 2011Assignee: DFT Microsystems Inc.Inventor: Mohamed M. Hafed
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Patent number: 7917318Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.Type: GrantFiled: May 30, 2008Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: David W. Boerstler, Eskinder Hailu, Masaaki Kaneko, Jieming Qi, Bin Wan
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Patent number: 7912669Abstract: A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.Type: GrantFiled: March 27, 2007Date of Patent: March 22, 2011Assignee: Honeywell International Inc.Inventor: Sumit K. Basu
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Patent number: 7908110Abstract: Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal, based on an offset corresponding to the count value and on a reference clock; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that detects a phase difference between the first delay clock and a transition point of the output signal, and changes the count value in a direction that decreases the phase difference; a timing comparison section that acquires the output signal according to a transition timing of the sampling clock; and a judging section that judges acceptability of the acquired output signal by comparType: GrantFiled: July 22, 2008Date of Patent: March 15, 2011Assignee: Advantest CorporationInventor: Masakatsu Suda
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Publication number: 20110054827Abstract: A test apparatus tests a modulated signal under test received from a DUT. A cross timing data generating unit generates cross timing data which indicates a timing at which the level of the signal under test crosses each of multiple thresholds. An expected value data generating unit generates timing expected value data which indicates a timing at which an expected value waveform of the signal under test crosses each of the multiple thresholds when the expected value waveform is compared with each of the multiple thresholds. A timing comparison unit compares the cross timing data with the timing expected value data.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Applicant: Advantest Corporation, a Japanese CorporationInventors: Masahiro Ishida, Daisuke Watanabe, Toshiyuki Okayasu
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Publication number: 20110054828Abstract: Embodiments disclosed herein include a test control panel device, system, computer program product, and method for receiving a test input signal; reading a duration of the test input signal; verifying that the signal duration is a valid duration to initiate the test; initiating the test by sending a start test signal to a valve controller device; receiving signals from the valve controller device; indicating that the test control panel device has received a valve controller device signal from the valve controller device; wherein the valve controller device signal is a test acknowledgement signal.Type: ApplicationFiled: August 30, 2010Publication date: March 3, 2011Applicant: FISHER CONTROLS INTERNATIONAL LLCInventor: Kenneth W. Junk
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Patent number: 7895005Abstract: A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.Type: GrantFiled: November 20, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: David W. Boerstler, Eskinder Hailu, Masaaki Kaneko, Jieming Qi, Bin Wan
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Patent number: 7895478Abstract: A method for monitoring a process execution of a plurality of sequentially executed processes starts one of a plurality of timers in cyclic permutation when one of the processes is started, and outputs a first error signal when a period of time recorded by one of the timers exceeds a predefined maximum period of time.Type: GrantFiled: December 30, 2005Date of Patent: February 22, 2011Assignee: Robert Bosch GmbHInventors: Ruediger Karner, Alexander Jansen
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Patent number: 7873925Abstract: In one embodiment, the invention is a method and apparatus for computing margins for at-speed testing of integrated circuit chips. One embodiment of a method for computing a margin for at-speed testing of an integrated circuit chip design includes computing a statistical chip slack for the chip, computing a statistical test slack for the chip, and computing the margin from the chip slack and the test slack.Type: GrantFiled: January 14, 2008Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Chandramouli Visweswariah, Jinjun Xiong, Vladimir Zolotov
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Publication number: 20100321127Abstract: A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.Type: ApplicationFiled: February 20, 2009Publication date: December 23, 2010Applicant: ADVANTEST CORPORATIONInventors: Daisuke Watanabe, Toshiyuki Okayasu
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Patent number: 7809521Abstract: A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the “LUT delay chain”), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.Type: GrantFiled: February 29, 2008Date of Patent: October 5, 2010Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Gary R. Burke, Yuan Chen, Douglas J. Sheldon
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Patent number: 7810005Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.Type: GrantFiled: October 31, 2007Date of Patent: October 5, 2010Assignee: Credence Systems CorporationInventors: Jean-Yann Gazounaud, Howard Maassen
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Publication number: 20100235125Abstract: An electric device includes a plurality of circuits that operate in synchronization with a clock signal, a plurality of flip-flops each of which acquires a data value of a signal from a corresponding one of the plurality of circuits in synchronization with the clock signal and stores the acquired data value therein until receiving a next clock signal, where each flip-flop enters into a clock-disabled state, when receiving a signal at a disable terminal thereof, in which the acquired data value continues to be stored in the flip-flop, a timing controller that outputs a hold signal to the disable terminal of each flip-flop at a timing at which a corresponding circuit is desired to be diagnosed, and a plurality of diagnosis lines that are respectively provided in correspondence with the plurality of flip-flops, each diagnosis line outputting as diagnosis data a data value stored in a corresponding flip-flop.Type: ApplicationFiled: February 24, 2010Publication date: September 16, 2010Applicant: ADVANTEST CORPORATIONInventor: Masahiko HATA
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Patent number: 7783452Abstract: A signal measuring apparatus that measures a first input signal and a second input signal is provided, including a first measuring section that measures the first input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a second measuring section that measures the second input signal at a plurality of strobe timings arranged in each cycle of a measurement cycle, a phase difference calculating section that calculates phase differences between the first input signal and the second input signal in each measurement cycle based on measurement results from the first measuring section and the second measuring section, and a distribution generating section that generates distribution information of the phase differences calculated in each measurement cycle by the phase difference calculating section.Type: GrantFiled: November 16, 2007Date of Patent: August 24, 2010Assignee: Advantest CorporationInventors: Tadahiko Baba, Masatoshi Ohashi
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Patent number: 7778787Abstract: A time-of-flight PET nuclear imaging device (A) includes radiation detectors (20, 22, 24), electronic circuits (26, 28, 30, 32) for processing output signals from each of detectors (20), a coincidence detector (34), a time-of-flight calculator (38) and image processing circuitry (40). A calibration system (48) includes an energy source (50, 150) which generates an electrical or optical calibration pulse. The electrical calibration pulse is applied at an input to the electronics at an output of the detector and the optical calibration pulse is applied to a preselected point adjacent a face of each optical sensor (20) of the detectors. A calibration processor (52) measures the time differences between the generation of the calibration pulse and the receipt of a trigger signal from the electronic circuitry by the coincidence detector (34) and adjusts adjustable delay circuits (44, 46) to minimize these time differences.Type: GrantFiled: August 2, 2005Date of Patent: August 17, 2010Assignee: Koninklijke Philips Electronics N.V.Inventors: Klaus Fiedler, Michael Geagan, Gerd Muehllehner, Walter Ruetten, Andreas Thon
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Patent number: 7774669Abstract: The present invention provides systems, devices and methods for generating user-defined test patterns within serial controller to facilitate signal testing and verification. These user-defined test patterns may be generated to more accurately reflect the actual traffic of a device-under-test or system, as well as allow a test engineer to more accurately test the boundaries of the device or system. In various embodiments of the invention, a programmable patterns generator is provided for generating user-defined test patterns that may be used during a testing procedure. This programmable pattern generator allows a user to define a particular test pattern by providing bit-by-bit test values, by defining a combination of canned sequences, or by supplementing one or more canned sequences with additional test bits.Type: GrantFiled: June 11, 2007Date of Patent: August 10, 2010Assignee: LSI CorporationInventors: Gabriel L. Romero, Coralyn S. Gauvin
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Patent number: 7769559Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.Type: GrantFiled: November 20, 2007Date of Patent: August 3, 2010Assignee: Teradyne, Inc.Inventor: Peter A. Reichert
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Patent number: 7756659Abstract: In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.Type: GrantFiled: January 11, 2008Date of Patent: July 13, 2010Assignee: Fairchild Semiconductor CorporationInventor: David P. Morrill
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Patent number: 7742893Abstract: A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop.Type: GrantFiled: February 21, 2008Date of Patent: June 22, 2010Assignee: STMicroelectronics S.r.l.Inventors: Pierangelo Confalonieri, Riccardo Martignone, Marco Zamprogno
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Patent number: 7739098Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.Type: GrantFiled: February 4, 2004Date of Patent: June 15, 2010Assignee: Synopsys, Inc.Inventors: Kayhan Küçükçakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu, Subramanyam Sripada, Andrew J. Seigel
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Patent number: 7734433Abstract: A semiconductor integrated circuit includes a first power source having a power supply voltage that operates the semiconductor integrated circuit, a voltage comparator that compares the power supply voltage with a reference voltage, and a comparison result recording unit that records a comparison result of the voltage comparator, wherein the comparison result recording unit records a length of a period based on a clock signal for which the power supply voltage exceeds the reference voltage.Type: GrantFiled: January 17, 2008Date of Patent: June 8, 2010Assignee: Fujitsu LimitedInventor: Akihiko Konmoto
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Patent number: 7734848Abstract: Described is a system and method for frequency offset testing. The system comprises an electronic device, a first testing device providing a reference clock signal at a first frequency to the electronic device, and a second testing device receiving data from the electronic device at the first frequency and transmitting data to the electronic device at a second frequency. The second frequency is equal to a product of the first frequency and a frequency offset value.Type: GrantFiled: November 8, 2006Date of Patent: June 8, 2010Assignee: Verigy (Singapore) Pte. Ltd.Inventor: Jinlei Liu
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Patent number: 7698669Abstract: The present invention is directed to a method and a system to evaluate operational characteristics of an electronic circuit. The method includes generating a visual display, on a monitor, of an eye diagram viewer. The eye diagram viewer is used to establish a test parameter for the circuit. Accessed is data that includes a graphical file containing eye diagram information corresponding to the test parameter. A visually perceivable image of the eye diagram information is provided in response to the test parameter. Specifically, the eye diagram viewer is used to establish an eye diagram information identifier by displaying in a plurality of test condition selector screens one of a multiple condition values for the test condition parameters. The graphical file containing the eye diagram information corresponding to the eye diagram information identifier is obtained from the server and displayed.Type: GrantFiled: May 11, 2007Date of Patent: April 13, 2010Assignee: Altera CorporationInventor: Daniel Tun Lai Chow
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Patent number: 7680493Abstract: According to one embodiment, a low phase noise testing system includes a tester providing a high phase noise digital channel output. The low phase noise testing system further includes a crystal filter configured to receive the digital channel output and to pass a narrow frequency range from the digital channel output, whereby the high phase noise digital channel output is converted to a low phase noise clock for use by a device under test. The crystal filter can be, for example, a monolithic crystal filter or a discrete crystal filter.Type: GrantFiled: May 10, 2007Date of Patent: March 16, 2010Assignee: Broadcom CorporationInventor: Timothy F. Scranton
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Patent number: 7672805Abstract: A method and apparatus for synchronizing digital and analog/mixed signal modules in a test site of an open architecture test system is disclosed. Event triggers from digital modules are routed to an ASYNC module, which selectively distributes them to analog/mixed signal modules. When an event occurs, the trigger may activate an analog/mixed signal module to perform a certain operation. The ASYNC module may also receive triggers from the analog/mixed signal modules and selectively distribute them back to the digital modules or analog/mixed signal modules. The digital modules can be programmed to wait for an analog/mixed signal module to complete an operation, as indicated by a trigger received from that analog/mixed signal module, before continuing. Because embodiments of the present invention enable synchronization of digital and analog/mixed signal modules under pattern control, synchronization can be very precise and repeatable as compared to synchronization from a site controller.Type: GrantFiled: February 13, 2004Date of Patent: March 2, 2010Assignee: Advantest CorporationInventors: Eric Barr Kushnick, Kenji Inaba, Toshiyuki Miura
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Publication number: 20100030508Abstract: A main driver and a sub-driver control circuit are provided respectively to receive a test pattern signal for testing a device. The main driver drives the test pattern signal to output a first driven signal. The sub-driver control circuit modifies the test pattern signal to output a modified pattern signal. The modified pattern signal is provided to a sub-driver. The first sub-driver drives the modified pattern signal to output a second driven signal. The first and the second driven signals are combined. The combined signal is provided to a terminal of the device as a test signal.Type: ApplicationFiled: July 27, 2009Publication date: February 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tatsuhiro Gake
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Patent number: 7640463Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.Type: GrantFiled: June 30, 2006Date of Patent: December 29, 2009Assignee: LSI CorporationInventors: Peter Windler, Richard Lim
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Patent number: 7640127Abstract: There is provided a detection apparatus including a transition point detecting unit operable to receive the output signal to detect the point of transition, a timing comparing unit operable to detect the signal level of the output signal in front of or behind the point of transition in the output signal, and a correction unit operable to compensate the timing of the point of transition detected from the transition point detecting unit based on the signal level of the output signal detected from the timing comparing unit.Type: GrantFiled: July 28, 2005Date of Patent: December 29, 2009Assignee: Advantest CorporationInventor: Masaru Doi
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Patent number: 7624323Abstract: An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC device for a predetermined time period, and creating an array indicating an execution or a nonexecution of signal timing combinations of one of the test signals relative to at least one of the other test signals within the predetermined time period by the IC device. A determination as to whether the desired signal timing combinations of the test signals have been executed by the IC device is made by an operator.Type: GrantFiled: October 31, 2006Date of Patent: November 24, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Sergio Casillas, Jr., Bruce LaVigne
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Patent number: 7620516Abstract: The present invention relates to process I/O controllers for semiconductor manufacturing to which a tool host can delegate data collection, monitoring and control tasks. In particular, it relates to process I/O controllers that can perform more than one of data collection, monitoring, control and response to commands from a tool host with statistically repeatable performance and precision. Embodiments described use prioritized real time operating systems to control of semiconductor manufacturing tools and data collection from tool associated with the sensors. Statistically repeatable responsiveness to selected commands and to sensor inputs during selected recipe steps effectively reduces jitter.Type: GrantFiled: April 25, 2006Date of Patent: November 17, 2009Assignee: MKS Instruments, Inc.Inventors: Leonid Rozenboim, David Michael Gosch
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Patent number: 7574633Abstract: There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing comparaType: GrantFiled: December 20, 2006Date of Patent: August 11, 2009Assignee: Advantest CorporationInventors: Naoki Sato, Noriaki Chiba, Tomohiro Uematsu
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Patent number: 7574317Abstract: An example embodiment provides a method for calibrating an active RC filter and RC time constant calibrator for an active RC filter. The RC time contact calibrator includes a RC timer and a calibration code generator. The RC timer outputs a holding signal based on a comparison of a first output signal and a second output signal. The holding signal output by the RC timer causes a digital count value to be compared to a digital target value. The calibration code generator generates a slope control code and a flag signal based on the comparison of the digital count value and the digital target value and outputs the slope control code as a calibration code based on the flag signal. The slope control code controls the slope of the first output signal and the slope of the second output signal.Type: GrantFiled: September 21, 2007Date of Patent: August 11, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Seung-Chan Heo
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Patent number: 7539592Abstract: A test apparatus for testing a device under test is provided. The test apparatus includes: a timing data output section for outputting timing data to define at least one of a timing of modifying a test signal provided to the device under test and a timing of acquiring an output signal outputted by the device under test; a variable delay circuit for delaying a reference clock pulse of the test apparatus by a delay amount corresponding to designated delay data so as to generate a timing signal having a transition point corresponding to the at least one timing; and a range modification section for modifying the modification amount of the delay data when the timing data are changed by one unit in response to a change of a setting range within which the at least one timing is set.Type: GrantFiled: March 23, 2007Date of Patent: May 26, 2009Assignee: Advantest CorporationInventor: Masaru Goishi
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Patent number: 7532995Abstract: An interpolator testing system comprises an interpolator that generates M clock signals having phase shifts in increments of 360/M degrees relative to a reference clock signal and that outputs one of the M clock signals as a recovered clock signal. A recovered clock counter counts an attribute of the recovered clock signal, wherein the interpolator sequentially selects the M clock signals N times, wherein M and N are integers greater than one.Type: GrantFiled: May 8, 2007Date of Patent: May 12, 2009Assignee: Marvell International Ltd.Inventors: William Lo, Francis Campana
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Patent number: 7526399Abstract: In a method of delay calculation of relative timing paths of an integrated circuit, each of the paths contains at least one stage. The method is achieved by calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component; and by carrying out delay calculation of relative timing paths by using the on-chip variation depending on the systematic component and the on-chip variation depending on the random component.Type: GrantFiled: September 1, 2004Date of Patent: April 28, 2009Assignee: NEC CorporationInventors: Junko Matsumoto, Tetsuya Akimoto
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Patent number: 7505862Abstract: The technology and economics of system testing have evolved to the point where a radical change in methodology is needed for effective functional testing of systems at clock rates of 1 GHz and higher. Rather than providing a test fixture to interface between the system under test and an external tester, it is preferable to provide critical testing functions within each electronic system in the form of one or more special-purpose test chips. An architecture is proposed that supports full-speed testing with improved noise margins, and also efficient methods for learning correct system behavior and generating the test vectors. The test program is preferably written using the same programming language as used for the system application.Type: GrantFiled: May 29, 2003Date of Patent: March 17, 2009Assignee: Salmon Technologies, LLCInventor: Peter C. Salmon
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Patent number: 7506222Abstract: A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.Type: GrantFiled: March 6, 2006Date of Patent: March 17, 2009Assignee: Advanced Micro Devices, Inc.Inventor: Gerald R. Talbot
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Publication number: 20090043529Abstract: A method for testing an accuracy of a real time clock is provided. The method includes: applying parameters that comprise a predetermined repetition count on testing the RTC, a predetermined time period, and an acceptable error margin of the RTC; communicating with a local network time protocol (NTP) server for acquiring a system time of the local NTP server; applying a current time of the RTC according to the system time at the beginning of testing the accuracy of the RTC; acquiring the current system time of the local NTP server when the predetermined time period lapse; computing a time difference between the system time of the local NTP server and the current time of the RTC; and determining if the RTC is accurate or not by comparing the time difference and the acceptable error margin, and generating a testing result according to the determination.Type: ApplicationFiled: July 7, 2008Publication date: February 12, 2009Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Wei-Yuan CHEN, Chun-Te YEH