Timing (e.g., Delay, Synchronization) Patents (Class 702/89)
  • Patent number: 8219342
    Abstract: A self correcting device includes a first flip-flop to receive data and coupled to a clock input; one or more delayed flip-flops used to detect delay variations; a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops, a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: July 10, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventors: Simone Medardoni, Marcello Lajolo
  • Patent number: 8219346
    Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as a field programmable gate array (FPGA). The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA is able to achieve nanosecond and sub-nanosecond time resolutions.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 10, 2012
    Assignee: The Regents of the University of Michigan
    Inventors: Thomas Zurbuchen, Steven Rogacki
  • Patent number: 8219343
    Abstract: Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: July 10, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8219344
    Abstract: Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 10, 2012
    Assignee: Agere Systems Inc.
    Inventors: Mohammad S. Mobin, Gregory W. Sheets, Lane A. Smith, Paul H. Tracy
  • Patent number: 8218605
    Abstract: A method for generating a preamble signal for a wireless communication system including the step of combining a plurality of different short PN sequences into a long PN sequence, wherein one of the plurality of short PN sequences includes information that is configured for coarse timing synchronization, and the long PN sequence includes information that is configured for fine timing synchronization.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: July 10, 2012
    Assignee: Sony Deutschland GmbH
    Inventors: Zhaocheng Wang, Masahiro Uno
  • Patent number: 8219345
    Abstract: A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods may include generating incremented counter values at a counter responsive to edges of the second clock signal. For at least two of the plurality of calibration periods, an initial incremented counter value from the counter may be stored in memory at an initial edge of the first clock signal for the respective calibration period, a final incremented counter value may be stored in memory at a final edge of the clock signal for the respective calibration period, and the at least two of the plurality of calibration periods may be overlapping with different initial and final edges of the first clock signal. For each of the plurality of calibration periods, a number of edges of the second clock signal occurring during the respective calibration period may be determined using the initial and final incremented counter values stored in memory.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 10, 2012
    Assignee: Sony Ericsson Mobile Communications AB
    Inventors: Jacobus Cornelis Haartsen, Aalbert Stek
  • Patent number: 8212547
    Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: July 3, 2012
    Assignee: STMicroelectronics International N.V.
    Inventors: Anurag Ramesh Tiwari, Kallol Chatterjee
  • Publication number: 20120166123
    Abstract: An impulse response measurement with high precision is made possible with a simple device or signal processing, even if sampling clocks on the transmitting side and the receiving side are asynchronous at the time of measuring an impulse response of a measured system. An impulse response measuring method includes an input signal generating step of generating an input signal of an arbitrary waveform to be input to a measured system by using a synchronization signal having a first sampling clock frequency, a signal converting step of performing conversion on a measured signal output from the measured system into a discrete value system by using a synchronization signal having a second sampling clock frequency, and an inverse filter correcting step of correcting at least a phase of an inverse filter which is an inverse function of a function showing a frequency characteristic of the input signal according to a frequency ratio of the first sampling clock frequency and the second sampling clock frequency.
    Type: Application
    Filed: July 7, 2010
    Publication date: June 28, 2012
    Inventors: Shokichiro Hino, Hiroshi Koide, Akihiro Shoji, Koichi Tsuchiya, Tomohiko Endo, Qlusheng Xie
  • Publication number: 20120158339
    Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Nitin Chawla, Kallol Chatterjee, Chittoor Parthasarathy
  • Patent number: 8201952
    Abstract: A projection apparatus and a projection system comprising the same are provided. The projection apparatus is adapted to connect to a server for transmitting a time signal via a network. The projection apparatus comprises a schedule module, a timing module, and a network process module. The schedule module is configured to store schedule information. The timing module is configured to generate time information. The network process module is coupled to the schedule module and the timing module, and configured to connect to the server to get time signal via the network according to the schedule information and timing information in a specific time.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: June 19, 2012
    Assignee: Delta Electronics, Inc.
    Inventors: Jimmy Su, Yu-Shan Lai
  • Patent number: 8191033
    Abstract: Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive the data at a capture element using the synchronous data path, wherein the launch element and the capture element are disposed on the same integrated circuit chip upon which the timing signal is generated and/or used, and gather statistics about whether a timing violation has occurred by comparing the sent data with the received data over the course of multiple launch/capture events as the timing is adjusted. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Marvell International Ltd.
    Inventor: Thomas Page Bruch
  • Patent number: 8190722
    Abstract: Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment, it can be determined how long it takes to propagate a signal to each box in the chain. These values are then recorded in each box in a delay register so that each box has a recorded delay value corresponding to the time required to propagate a signal to or receive a signal from every other box. Each box applies a control signal, such as a run signal or a trigger signal, to the ports in the box only after the expiration of the delay value indicated in the delay register. The box initiating the signal has the largest delay since the other boxes need to get the signal before the boxes can begin to operate with a common counter, with successive boxes having smaller delays.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: May 29, 2012
    Inventors: Randy Oyadomari, Arthur Michael Lawson
  • Patent number: 8175834
    Abstract: In a method for monitoring a measurement system having a transmitter which determines the position of a moveable element and has a transmitter clock, and an electrical energy store which, in the event of a failure of an external electrical supply voltage for the transmitter, continues to supply electrical power to at least a part of the transmitter, including the transmitter clock. After the external electrical supply voltage has been restored, the clock time of the transmitter clock is compared with a clock time of an external clock, and an incorrectly determined position is identified on the basis of the comparison of the clock times.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: May 8, 2012
    Assignee: Siemens Aktiengesellschaft
    Inventor: Roland Finkler
  • Publication number: 20120109563
    Abstract: The best match of two time-uncertain series is quantified with a degree of confidence by selecting one of the time series and repeatedly computing a maximum covariance between the selected time series and a series of random records with the same distribution and expected autocorrelation as the non-selected time series. The resulting distribution of maximum covariances can be used to determine a degree of confidence by determining the percentage of those computed maxima which lie below the maximum covariance associated with the best match.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 3, 2012
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Kwang-Chung Eddie HAAM, Peter HUYBERS
  • Patent number: 8135553
    Abstract: A method for clock calibration is provided. The method comprises receiving discontinuous reception period (DRX period) information from a base station, computing a calibration duration according to the discontinuous reception period and a clock error tolerance of a first clock, and when receiving paging information that informs of possible sent transmissions, calibrating the first clock with a second clock for a period of the calibration duration.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: March 13, 2012
    Assignee: Mediatek Inc.
    Inventors: Ganning Yang, Ming-Chi Chen
  • Patent number: 8107579
    Abstract: Clock compensation for GPS receivers. A receiver in accordance with the present invention comprises a Radio Frequency (RF) portion, and a baseband portion, coupled to the RF portion, wherein the baseband portion comprises a crystal, an oscillator, coupled to the crystal, wherein the oscillator generates a clock signal based on a signal received from the crystal, a counter, coupled to the oscillator via the clock signal, a comparator, coupled to the counter, a controller, at least one logic gate, coupled to the comparator and the controller, and a combiner, coupled to the at least one logic gate, the controller, and the counter and producing an accurate clock signal therefrom.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: January 31, 2012
    Assignee: Qualcomm Atheros Technology Ltd.
    Inventor: Richard Obermeyer
  • Publication number: 20120010838
    Abstract: Calibration of a device using electromagnetic waves to determine a distance to a surface, which device comprises a pulse generator, a real time sampler and a calibration unit having a signal generator for generating a calibration signal with a predefined frequency. In a calibration mode, the real time sampler receives the calibration signal, and an average sample time delay of the sampler is determined based on the sampled calibration signal and the known calibration frequency. In a measurement mode, the real time sampler receives a reflection signal and the distance is determined based on a sampled reflection signal and the average sample time delay. Knowledge of the average delay of the sampler makes it possible to exactly determine the distance (in time and thus space) between two points in the sampled signal.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Inventors: Fabian Wenger, Valter Nilsson
  • Patent number: 8065102
    Abstract: A pulse width measurement circuit generates a time difference signal that corresponds to the pulse width of the input pulse signal PULSE. A delay circuit delays the input pulse signal PULSE by a predetermined amount, and outputs a start signal. An inverter inverts the input pulse signal PULSE, and outputs a stop signal. A time measurement circuit measures the time difference between a positive edge in the start signal and a positive edge in the stop signal, and outputs a time difference signal that corresponds to the time difference.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: November 22, 2011
    Assignee: Advantest Corporation
    Inventor: Shoji Kojima
  • Patent number: 8060326
    Abstract: Provided is a measurement apparatus including a first timing detecting section that detects first change timings of a signal under measurement, a second timing detecting section that detects second change timings of the signal under measurement, a buffer section that buffers data indicating the first change timings detected by the first timing detecting section and data indicating the second change timings detected by the second timing detecting section, and a calculating section that acquires, from the buffer section, the data indicating the first change timings and the data indicating the second change timings, calculates a temporal relationship between the first change timings and the second change timings, and outputs the temporal relationship.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: November 15, 2011
    Assignee: Advantest Corporation
    Inventors: Masashi Miyazaki, Hiroshi Ito
  • Patent number: 8058918
    Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: November 15, 2011
    Assignee: Redmere Technology Ltd.
    Inventors: Aidan Gerard Keady, John Anthony Keane, Judith Ann Rea, Benjamin Griffin, John Martin Horan
  • Patent number: 8055801
    Abstract: A time synchronization apparatus, method and system are provided. In one aspect, the apparatus comprises at least a time of day clock, a first port operable to receive at least first time information using a first time protocol, a second port operable to receive at least second time information using a second time protocol, a third port operable to receive at least a timing signal, and a time stamp register operable to at least capture current value of the time of day clock upon receipt of the timing signal from the third port or the first time information from the first port or combination thereof.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ronald M. Smith, Sr., Evangelyn Kay Gardner Smith, legal representative
  • Patent number: 8050881
    Abstract: A system for synchronizing data after they are collected and stored locally in sensor units in a distributed sensor system, so that wired or wireless communication is not required during a data-collection session. Each sensor unit has a local clock providing local-clock times before and after a data-collection session, and a data processor uses its local clock or a sensor unit's local clock as the reference to compute each sensor unit's time-scaling factor, which is the ratio of the elapsed reference local-clock time and the elapsed local-clock time. The data processor uses the time-scaling factor to convert each sensor unit's local-clock data-sampling times to the reference local-clock data-sampling times, and the data processor subsequently interpolates sensor data to approximate simultaneous sensor-data values at desired reference local-clock times. A physical-activity monitoring system can use this synchronization method to reduce the size, power consumption, and cost of the sensor units.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: November 1, 2011
    Assignee: Enbiomedic
    Inventors: King-Wah Walter Yeung, Wei-Wei Vivian Yeung
  • Patent number: 8046185
    Abstract: Systems, methods, and apparatuses including computer program products for oscillator calibration include, in at least one implementation, a storage device including: a system including a first clock source, a second clock source, and a motor controller, the motor controller including calibration circuitry configured to calibrate the second clock source according to the first clock source in response to the first clock source operating as expected, and configured to provide to the system the calibrated second clock source as a timing reference instead of the first clock source as the timing reference in response to the first clock source not operating as expected, a head actuator configured to communicate with the motor controller, and a spindle disposed within the system.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: October 25, 2011
    Assignee: Marvell International Ltd.
    Inventor: Siew Yong Chui
  • Publication number: 20110254760
    Abstract: The present invention relates to a combination of a 6-axis motion sensor having a 3-axis gyroscope and a 3-axis linear accelerometer, a motion processor and a radio integrated circuit chip (IC), wherein the intelligence in the motion processor enables the communication between the motion sensor, the radio IC and the external network. The motion processor also enables power savings by adaptively controlling the data rate of the motion sensor, depending on the amount or speed of the motion activity.
    Type: Application
    Filed: August 27, 2010
    Publication date: October 20, 2011
    Applicant: InvenSense, Inc.
    Inventors: Stephen Lloyd, David Sachs, David Devries, Doug Vargha, Derek Shaeffer, Erik Anderson, Kerry Keal, Nathan Royer
  • Patent number: 8041979
    Abstract: A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least one responding device receiving a trigger message from the initiating device. The trigger message includes a state transition time or a time from which a state transition time is obtainable. The method further includes the at least one responding device jointly making a respective state transition at the state transition time. A responding device, and a system including the initiating device and the responding device are also disclosed.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 18, 2011
    Assignee: Agilent Technologies, Inc.
    Inventors: James Adam Cataldo, Bruce Hamilton
  • Publication number: 20110251813
    Abstract: A system for synchronizing components of a downhole system includes: a source assembly including a source clock; an electromagnetic source associated with the source assembly and configured to emit an electromagnetic signal into an earth formation at a transmission time; a receiver assembly including a receiver clock; an electromagnetic receiver associated with the receiver clock and configured to detect the electromagnetic signal; and a processor configured to identify a receipt time of the electromagnetic signal based on the receiver clock and adjust the receiver clock by comparing the transmission time to the receipt time.
    Type: Application
    Filed: March 25, 2011
    Publication date: October 13, 2011
    Applicant: BAKER HUGHES INCORPORATED
    Inventors: Radu Coman, Michael Neubert
  • Patent number: 8036844
    Abstract: A system and method of phase compensating transient performance data are provided. Transient performance data are collected for a plurality of parameters, and two of the parameters are selected. A transfer function is applied to the transient performance data for at least one of the selected parameters to thereby generate phase compensated performance data that is representative of a steady state relationship between the selected parameters.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: October 11, 2011
    Assignee: Honeywell International Inc.
    Inventors: Richard Ling, Oswald Harris, Alan Hemmingson
  • Patent number: 8024147
    Abstract: An offset compensation circuit for a yaw rate sensor, having a subtracter, which is provided for subtracting a correction value from an input signal, the correction value being obtainable by dividing each of n measurements of the input signal by the constant n and subsequently integrating a number of n quotients into an integrator. Furthermore, a yaw rate sensor having such an offset compensation circuit.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: September 20, 2011
    Assignee: Robert Bosch GmbH
    Inventor: Michael Baus
  • Patent number: 8020130
    Abstract: In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: September 13, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventor: Makoto Nagata
  • Patent number: 8019957
    Abstract: A calibration module for a data storage control system. The calibration system includes a programmable delay module configured to i) receive a data strobe signal, ii) receive a delay value, and iii) output a delayed data strobe signal to a buffer based on the delay value, wherein data is read from the buffer based on the delayed data strobe signal. The calibration module further includes a delay calculation module configured to calculate the delay value based on a comparison between the data strobe signal and the delayed data strobe signal.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: September 13, 2011
    Assignee: Marvell International Ltd.
    Inventors: Theodore C. White, Thanh H. Le
  • Patent number: 8010317
    Abstract: A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of threshold voltage VT logic libraries. Each hardware performance monitor is associated with one of the plurality of threshold voltage VT logic libraries and provides a signal that measures a performance of its respective threshold voltage VT logic library die temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and provided to an advanced power controller for use in providing adaptive voltage scaling for the integrated circuit system.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: August 30, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Juna Pennanen, Pasi Salmi
  • Patent number: 7991573
    Abstract: One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 2, 2011
    Assignee: Qimonda AG
    Inventors: Russell Homer, Luca Ravezzi, Hamid Partovi
  • Patent number: 7987062
    Abstract: A delay circuit includes a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value. The initializing section includes a first loop path that inputs an output signal of the first delay element into the first delay element and a second loop path that inputs an output signal of the second delay element into the second delay element. The initialization section includes a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element, a second measuring section that measures a delay amount in the second delay element, and a delay amount computing section that corrects a delay amount measured by the first measuring section.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: July 26, 2011
    Assignee: Advantest Corporation
    Inventors: Kazuhiro Fujita, Masakatsu Suda, Takuya Hasumi
  • Patent number: 7987061
    Abstract: The present invention relates to a method and apparatus for measuring a frequency or a phase of a measuring signal, wherein the frequency (fg) or the phase (?g) are estimated by approximating the relationship between a collecting clock (c) and a gating clock (g) based on a non-linear step-shaped function. Thereby, the estimation error can be improved with almost negligible complexity increase in signal processing.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: July 26, 2011
    Assignee: ST-Ericsson SA
    Inventor: Alexander Lampe
  • Publication number: 20110170534
    Abstract: Apparatus includes at least two devices that communicate with each other, wherein a first one of the at least two devices having an IEEE 1588 precision time protocol interface, the interface including one or more components configured for communications in both a wired manner and a wireless manner with a second one of the at least two devices. The second one of the at least two devices having an IEEE 1588 precision time protocol interface, the interface including one or more components configured for communications in both a wired manner and a wireless manner with the first one of the at least two devices.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 14, 2011
    Applicant: FARO TECHNOLOGIES, INC.
    Inventor: Frederick John York
  • Patent number: 7979228
    Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA achieves nanosecond and sub-nanosecond time resolutions and is used in applications such as various time of flight systems.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: July 12, 2011
    Assignee: The Regents of the University of Michigan
    Inventors: Thomas Zurbuchen, Steven Rogacki
  • Patent number: 7974807
    Abstract: Techniques for adaptively calibrating a TDC output signal in a digital phase-locked loop (DPLL). In an exemplary embodiment, a calibration factor multiplied to the TDC output signal is adaptively adjusted to minimize a magnitude function of a phase comparator output signal of the DPLL. In an exemplary embodiment, the calibration factor may be adjusted using an exemplary embodiment of the least-mean squares (LMS) algorithm. Further techniques for simplifying the adaptive algorithm for hardware implementation are described.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: July 5, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Jifeng Geng, Daniel F. Filipovic, Christos Komninakis
  • Publication number: 20110161031
    Abstract: A time differential is estimated between a plurality of signals by determining a filter response of a first electrical signal with a first filter array, determining a filter response of a second electrical signal with a second filter array, and determining, based at least on the filter response of the first electrical signal and the filter response of the second electrical signal, a time differential between the first electrical signal and the second electrical signal. A first optical signal is converted into the first electrical signal and a second optical signal is converted into the second electrical signal. The filter response of the first electrical signal and the filter response of the second electrical signal are sampled and the time differential between the first electrical signal and the second electrical signal is determined based at least on the sampled filter response of the first electrical signal and the sampled filter response of the second electrical signal.
    Type: Application
    Filed: January 31, 2011
    Publication date: June 30, 2011
    Applicant: VOXIS, INC.
    Inventors: Jerry Samuel Dimsdale, Joseph Newhall West, Andrew Philip Lewis, Thomas Rahjit Singh Gill
  • Patent number: 7970566
    Abstract: Two or more sets of measurement data can be independently collected from causally related characteristics or elements. Such measurements can be synchronized with one another through the identification of a correct offset between their measurement data. An identification of the nature of the causal relationship between the measured characteristics can identify relevant ranges within which the aggregate values of one of the measurements can be obtained. As the offset between the measurements is adjusted, the aggregate values can change and a derivative, or other meaningful function based on the aggregate values can be calculated. The meaningful function, or subsequent functional result of it, can inform a range of offsets within which a local extreme value can be identified. The offset corresponding to such a local extreme value can be the correct offset.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Microsoft Corporation
    Inventors: Lloyd Alfred Moore, John R Eldridge
  • Patent number: 7945341
    Abstract: A graphical user interface for use in phacoemulsification surgical systems that allows a user to select different pulse modes by touching portions of the display screen. The user interface includes first and second display elements. One display element includes a representation of the on-time of the pulses, and the other display element includes a representation of the off-time. The representations show how the on-time and off-time change relative to a position of a controller, such as a foot pedal. The representation show a constant time, or that a time increases or decreases as the foot pedal is pressed. To select a pulse mode, a user can scroll through different pulse representations by touching the screen at the display elements. The selected pulse mode can be continuous, pulse, burst and other modes.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 17, 2011
    Assignee: Alcon, Inc.
    Inventors: Mikhail Boukhny, David Thoe
  • Patent number: 7936197
    Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: May 3, 2011
    Assignee: Redmere Technology Ltd.
    Inventors: Aidan Gerard Keady, John Anthony Keane, Judith Ann Rea, Benjamin Griffin, John Martin Horan
  • Patent number: 7937232
    Abstract: Embodiments of the present invention relate to managing timestamps associated with received data. According to one embodiment, data is collected from a device that generates data at a specified rate, but which lacks a built-in clock. An accurate timestamp is assigned to the data by first taking an absolute timestamp from a reference clock, and then adding a calculated amount of time to each subsequent data point based on an estimate of the sampling frequency of the device. As the generated timestamp drifts from the actual reference clock time, the sampling frequency is re-estimated based on the amount of detected drift.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: May 3, 2011
    Assignee: Pivotal Systems Corporation
    Inventors: Paxton Ming Kai Chow, Vera Alexandrova Snowball, Barton George Lane, III, Sophia Leonidovna Shtilman, Chalee Asavathiratham, Abhijit Majumdar, Sherk Chung, Yi Wang, Paul Tran
  • Publication number: 20110087449
    Abstract: A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods may include generating incremented counter values at a counter responsive to edges of the second clock signal. For at least two of the plurality of calibration periods, an initial incremented counter value from the counter may be stored in memory at an initial edge of the first clock signal for the respective calibration period, a final incremented counter value may be stored in memory at a final edge of the clock signal for the respective calibration period, and the at least two of the plurality of calibration periods may be overlapping with different initial and final edges of the first clock signal. For each of the plurality of calibration periods, a number of edges of the second clock signal occurring during the respective calibration period may be determined using the initial and final incremented counter values stored in memory.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 14, 2011
    Inventors: Jacobus Cornelis Haartsen, Aalbert Stek
  • Patent number: 7925456
    Abstract: A method and apparatus is disclosed that guides a user through a sequence of steps that will allow the user to complete a predefined task using the flow meter. The steps include: selecting a predefined task, displaying a sequence of steps that directs the user through a process for using the Coriolis flow meter to complete the predefined task, and operating the Coriolis flow meter in response to the sequence of steps to complete the predefined task.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: April 12, 2011
    Assignee: Micro Motion, Inc.
    Inventors: Craig B. McAnally, Andrew T. Patten, Charles P. Stack, Jeffrey S. Walker, Neal B. Gronlie
  • Patent number: 7917318
    Abstract: A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 29, 2011
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Masaaki Kaneko, Jieming Qi, Bin Wan
  • Patent number: 7904266
    Abstract: A method and an apparatus for calculating the separation time of the arcing contacts of a high-voltage switchgear which is operatively coupled to a synchronous switching device and to an auxiliary switch having auxiliary contacts operatively connected to the arcing contacts. During execution of a predefined test condition the separation time of the arcing contacts and of the auxiliary contacts is measured. The time delay between the measured separation time of the arcing contacts and of the auxiliary contacts is calculated. Upon separation of the arcing contacts under an operating condition other than the predefined test condition, the separation time of the auxiliary contacts is measured. Then, the separation time of the arcing contacts is calculated as the difference between the separation time of the auxiliary contacts measured during the operating condition other than the predefined test condition and the calculated time delay.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: March 8, 2011
    Assignee: ABB Technology AG
    Inventors: Michael Mendik, Anton Poeltl
  • Patent number: 7904264
    Abstract: A mechanism for measuring the absolute duty cycle of a signal is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Masaaki Kaneko, Jieming Qi, Bin Wan
  • Patent number: 7899633
    Abstract: An object of the present invention is to provide a sensing instrument capable to detect a substance existing in a very small quantity, such as environmental pollutants, instantly with a high degree of precision. As a specific means for solving the problem, a frequency signal from a crystal oscillator is sampled using a frequency signal from a reference clock generating part, the sampling value is outputted in a digital signal, quadrature detection is conducted with the digital signal for a frequency signal corresponding to the output signal, the rotational vector rotating at a frequency corresponding to the difference between the frequency of the frequency signal and the frequency of a sinusoidal wave used for the quadrature detection is taken out, and the variation of the frequency is detected by detecting the velocity of the rotational vector based on the respective sampling values.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 1, 2011
    Assignees: Nihon Dempa Kogyo Co., Ltd., DSP Technology Associates, Inc.
    Inventors: Nobuo Tsukamoto, Kazuo Akaike, Tsukasa Kobata
  • Patent number: 7895005
    Abstract: A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: David W. Boerstler, Eskinder Hailu, Masaaki Kaneko, Jieming Qi, Bin Wan
  • Patent number: 7890787
    Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: February 15, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Shaun Bradley, Kieran Heffernan, Tomas Tansley, Yang Ling