Abstract: The present invention provides a system and method for time-series with compression accuracy as a function of time. Briefly described, in architecture, one embodiment of the system, among others, can be implemented as follows. The system includes a computer with a processor. The system performs a method receiving a data set on the computer, utilizing a plurality of filter banks to transform the data set into a plurality coefficients, wherein each coefficient is associated with a basis function, and quantizing the plurality of coefficients, wherein the quantization maps the plurality of coefficients into certain value ranges. Then, system further performs determining a threshold based upon each coefficient effect on a time domain, disregarding the coefficient that fall below the threshold, and storing any remaining coefficients as compressed data for the data set.

Abstract: A method and system for compressing coefficients of a digital filter is provided. In one approach, the method comprises providing a digital filter having a plurality of consecutive filter coefficients including a first filter coefficient, determining consecutive difference values between each of the consecutive filter coefficients, and storing the first filter coefficient and the consecutive difference values in a memory. The consecutive filter coefficients are generated by retrieving the first filter coefficient, and adding a first difference value to the first filter coefficient to generate a consecutive second filter coefficient. The first difference value corresponds to a difference between the first filter coefficient and the second filter coefficient. A consecutive next difference value is then added to the second filter coefficient to generate a consecutive next filter coefficient.

Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

Abstract: A method, system, and processor-readable storage medium are directed towards calculating approximate order statistics on a collection of real numbers. In one embodiment, the collection of real numbers is processed to create a digest comprising hierarchy of buckets. Each bucket is assigned a real number N having P digits of precision and ordinality O. The hierarchy is defined by grouping buckets into levels, where each level contains all buckets of a given ordinality. Each individual bucket in the hierarchy defines a range of numbers—all numbers that, after being truncated to that bucket's P digits of precision, are equal to that bucket's N. Each bucket additionally maintains a count of how many numbers have fallen within that bucket's range. Approximate order statistics may then be calculated by traversing the hierarchy and performing an operation on some or all of the ranges and counts associated with each bucket.

Abstract: The image data processor generates storage layout information and output joint information, and then generates a page raster for storage based on the storage layout information and a page raster for output based on the output joint information. The storage layout information is based on layout information describing object layouts and includes a page formed by the same objects and reusable objects of the same arrangements and a page formed by each variable object. The output joint information combines a page for reusable objects and a page for the variable object.

Abstract: Various methods and devices are provided to address the need for reduced compression complexity in the area of compressive sensing. In one method, a vector x is compressed to obtain a vector y according to y=?RDx, where ?RD=U?RM·?RM is a compressive sensing matrix constructed using a second-order Reed-Muller code or a subcode of a second-order Reed-Muller code and U is a unitary matrix from the real or complex Clifford group G. In another method, vector y is decompressed to obtain vector x also according to y=?RDx. In some embodiments, decompression may involve computing y?=U?1y and then determining the vector x using the computed y?.

Abstract: Aspects of the subject matter described herein relate to image restoration for compressed images. In aspects, image restoration is accomplished by recovering spectral information from data corresponding to a compressed image. The spectral information is recovered using an algorithm to search through a solution space of possible solutions while constraints are imposed on the solution space to trim undesirable solutions from the space. An algorithm described herein may be iteratively applied to improve the quality of the recovered image.

Abstract: A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first four-to-two compressor, performing a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second four-to-two compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.

Abstract: A data accessing and reproducing apparatus and method that permits a user to selected desired video clips and perform editing on the clips such that the time needed to display a thumbnail representation is minimized. In an edit mode, thumbnail pictures are arranged and displayed in the order of which edit results are reproduced. These thumbnails may be, for example, a lower resolution, proxy representation of the audio or video data. When data of thumbnail pictures are read from a disc, the data are read in the order of which they have been recorded. The order of which thumbnail pictures are displayed on the screen is different from the order of which they are arranged on the screen, and thus, the seek time for the disc becomes the shortest. Thus, the thumbnail pictures can be displayed at high speed.

Abstract: Method for fully adaptive calibration of a prediction error coder, comprising a first step of initialization; a second step of reception and accumulation of block-size data samples wherein for each received value, it is added one to the histogram bin associated to that value; a third step of analysis of the histogram and determination of the coding option; a fourth step of analysis of the histogram and determination of a coding table; a fifth step of output a header with the prediction error coder coding table determined; and wherein previous steps are repeated if more samples need to be compressed. It is useful as a data compression technique, with the advantage of being faster and more robust than the current CCSDS lossless compression standard.

Abstract: A low-complexity inverse transform computation method, comprising following steps: firstly, analyzing an end-of-block (EOB) point in a matrix of a block; next, determining whether a bottom-left corner coefficient or a top-right coefficient before said EOB point is zero, and if it is zero, reducing further size of said matrix; then, determining an adequate operation mode to reduce computational complexity; and finally, realizing 2-D inverse transform through simplified 1-D inverse transforms. An inverse transform process of said method mentioned above is capable of lowering computation amount, reducing burden and computational complexity of a decompression system, and shortening effectively computation time of said 2-D inverse transform, such that it is applicable to inverse transforms of various video and still image codecs.

Abstract: A method and system for compressing a tree with a plurality of nodes that each may be associated with a node identifier and a parent node identifier. The method may comprise for each node in the tree determining whether the current node is to be deleted, if the current node is to be deleted updating a list of deleted nodes such that the node identifier of the current node may be stored; a parameter representing a number of nodes currently having been deleted from the tree may be stored, such that the parameter is associated with the node identifier of the current node, and updating the node identifier and the parent node identifier of the current node as a function of the list of deleted nodes. Each node in the tree is visited only once.

Abstract: According to one embodiment, a decompressing apparatus includes an input unit, a calculating unit, a first selecting unit, and a decompressing unit. The input unit inputs additional data, which is obtained based on trace expression data in which an element in a subgroup of a multiplicative group of a finite field is trace-expressed and affine expression data in which the trace expression data is affine-expressed, and the trace expression data. The calculating unit calculates a plurality of solutions of simultaneous equations derived by the trace expression data. The first selecting unit selects any of a plurality of items of affine expression data in which the element is affine-expressed based on the additional data, the affine expression data being found from the solutions. The decompressing unit decompresses the selected affine expression data to the element.

Abstract: A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows.

Abstract: According to one embodiment, a representation converting unit converts a set of n elements (h0, h1, . . . , hn?1) (hi: a member of a finite field Fp?m, 0?i?n?1) that is a projective representation of a member g of an n-th degree algebraic torus Tn(Fp?m) (n: positive integer, p: prime number, m: positive integer) into a limited projected representation expressed by a set of n elements (h?0, h?1, . . . , h?n?1) (h?i: a member of the finite field Fp?m, 0?i?n?1) in which at least one element out of the n elements is a zero element 0 or an identity element 1. An arithmetic unit omits part of Fp?m operation that is arithmetic operation in the finite field Fp?m based on a fact that an element in the set of n elements (h?0, h?1, . . . , h?n?1) represented by the limited projective representation is a zero element “0” or an identity element “1” when performing Fp?mn operation that is arithmetic operation of a finite field Fp?mn in combination with the Fp?m operation.

Abstract: Methods and apparatus for lossless LiDAR LAS file compression and decompression are provided that include predictive coding, variable-length coding, and arithmetic coding. The predictive coding uses four different predictors including three predictors for x, y, and z coordinates and a constant predictor for scalar values, associated with each LiDAR data point.

Abstract: A method for processing a digital signal comprises receiving an output encoded signal (Sd,sc) obtained from an original digital signal (Si) having an initial spatial resolution and an initial bit rate, the output encoded signal having a bitrate lower than the initial bitrate, processing the output encoded signal to obtain a source signal (Sv) having the initial spatial resolution, and dividing (E303) samples of the source signal into at least two subsets of samples, the subsets corresponding respectively to different spatial grids that are arranged so that at least some samples of one subset are interleaved spatially with at least some samples of another said subset.

Abstract: An integrated memory controller (IMC) preferably sits on the main CPU bus or a high speed system peripheral bus and couples to system memory. The IMC may use a lossless data compression and decompression scheme for improved performance. The IMC may also include microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data may be decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Internal memory mapping may allow for formal definition spaces which may define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level.

Abstract: An apparatus for evaluating a mathematical function at an input value is provided. The apparatus includes a device for selecting a mathematical function, a device for inputting a value at which to evaluate the function, a device for identifying an interval containing the input value, the interval being described by at least one polynomial function, a device for retrieving at least one control point representing the polynomial function from at least one look up table, a device for deriving the polynomial function from the control points, a device for evaluating the function for the input value and a device for providing data representing the evaluated function at an output.

Abstract: A method to perform a least recently used (LRU) algorithm for a co-processor is described, which co-processor in order to directly use instructions of a core processor and to directly access a main storage by virtual addresses of said core processor comprises a TLB for virtual to absolute address translations plus a dedicated memory storage also including said TLB, wherein said TLB consists of at least two zones which can be assigned in a flexible manner more than one at a time. Said method to perform a LRU algorithm is characterized in that one or more zones are replaced dependent on an actual compression service call (CMPSC) instruction.

Abstract: Methods and systems for decompressing data are described. The relative magnitudes of a first value and a second value are compared. The first value and the second value represent respective endpoints of a range of values. The first value and the second value each have N bits of precision. Either the first or second value is selected, based on the result of the comparison. The selected value is scaled to produce a third value having N+1 bits of precision. A specified bit value is appended as the least significant bit of the other (non-selected) value to produce a fourth value having N+1 bits of precision.

Abstract: An image capturing apparatus determines an image frame to extract as a reference image frame from a plurality of image frames constituting a moving image, using a histogram, for example, and generates a reference image data file. An encoder unit encodes the plurality of image frames after reducing the resolution thereof, and generates an encoded moving image data file. A list associating the reference image frame with information specifying the corresponding reference image data file is generated with a content information list generating unit. The reference image data file, the encoded moving image data file and the list are then recorded.

Abstract: A system comprises a receiver and a transmitter in wireless communication with the receiver. The receiver receives from the transmitter multiple bursts of data on a paging channel. First and second bursts of data comprise channel protocol information and paging mode data. The second burst comprises an encoding dependency that groups paging mode data independently of channel protocol information.

Abstract: A computerized data storage system includes at least one storage device including a nonvolatile writable medium; a cache memory operatively coupled to the storage port and including a data storing area and a data management controller and a storage port. The storage port is operable to connect to a host computer, receive and send I/O information required by the host computer. The storage port is also operable to receive a request to read data, and, in response to the request to read data, the storage port is operable to send the data stored in the data storing area of the cache memory. The storage port is further operable to receive a request to write data, and, in response to the request to write data, the storage port is operable to send the write data to the data storing area of the cache memory.

Abstract: A computing method and circuit for computing a modular operation with at least one operand having a binary representation. Iteratively for each bit of this operand, doubling the value of an intermediate result stored in a first memory element by shifting the bits of the intermediate result towards the most significant bit and, while the most significant bit of the intermediate result is one, updating this intermediate result by subtracting a modulus stored in a second memory element.

Abstract: A system and method for compressing and/or decompressing data uses a field programmable gate array (FPGA). In an embodiment, the method includes receiving data at the FPGA device, filtering the received data in a first dimension using a first logic structure of the FPGA device, storing the first filtered data in a memory of the FPGA device, filtering the received data in a second dimension using a second logic structure of the FPGA device, storing the second filtered data in the memory, quantizing the filtered data using a third logic structure of the FPGA device, encoding the quantized data using a fourth logic structure of the FPGA device to compress the data, and storing the encoded compressed data in a memory of the FPGA device.

Abstract: Provided is a method of compressing information.

Abstract: A system and method for compressing trace data from an emulation system. Scan chains may receive trace data from configurable logic blocks inside one or more emulation chips, and the data received from the scan chains may be compressed. Where delta compression is used, the scan chains may also perform a delta detection function. Alternatively, delta detection may be performed using the outputs of the scan chains. In addition, event detectors may be implemented within or outside of the scan chains. Compression of the trace data may include receiving a plurality of data sets and performing compression along cross-sections of the combined data sets.

Abstract: A multi-resolution segmentation and fill technique is disclosed. In one embodiment, the method comprises generating a plurality of layers using image data from multiple resolutions, generating a mask describing compositing of the plurality of layers to obtain the image, and filling pixels in each of the plurality of layers where the pixels being filled are those that do not contribute to the image when the plurality of layers are composited.

Abstract: Encoding data includes: computing a first set of coefficients based on a plurality of transforms each computed over a different portion of an array of data, a second set of coefficients based on a plurality of transforms each computed over a different portion of the array of data, and a third set of coefficients based on a transform computed over the array of data; choosing a set of coefficients to represent the array of data from a group of multiple sets of coefficients, the group including the first set of coefficients, the second set of coefficients, and the third set of coefficients; and encoding the chosen coefficients and one or more parameters related to the chosen coefficients.

Abstract: Systems and methods compress and decompress 16 bit data. The 16 bit data may be signed or unsigned and represented in a fixed point or floating point format. A fixed block size of data is compressed into a fixed length format. Data compressed using a medium quality compression scheme may be efficiently decompressed in hardware. Data may be efficiently compressed and decompressed in hardware using a high quality compression scheme. The high quality compression scheme has a lower compression ratio compared with the medium quality compression scheme, but is near lossless in terms of quality.

Abstract: A method for determining a representation (y) of a signal (s) comprise selecting a predetermined number (m) of row vectors (v1, . . . , vm) from a predetermined measurement matrix (M). The predetermined measurement matrix (M) is predetermined dependent on a product of a predetermined Hadamard matrix or generalized Hadamard matrix (H) and a predetermined representation matrix(B). The predetermined representation matrix (B) represents a predetermined basis for the signal(s). The method further comprises determining a respective inner product of the signal (s) and each of the predetermined number (m) of selected row vectors (v1, . . . , vm) resulting in a predetermined number (m) of measurements (y1, . . . , ym) forming the representation (y) of the signal (s).

Abstract: Novel, computationally efficient schemes for deterministic wavelet thresholding with the objective of optimizing maximum-error metrics are provided. An optimal low polynomial-time algorithm for one-dimensional wavelet thresholding based on a new dynamic-programming (DP) formulation is provided that can be employed to minimize the maximum relative or absolute error in the data reconstruction. Directly extending a one-dimensional DP algorithm to multi-dimensional wavelets results in a super-exponential increase in time complexity with the data dimensionality. Thus, novel, polynomial-time approximation schemes (with tunable approximation guarantees for the target maximum-error metric) for deterministic wavelet thresholding in multiple dimensions are also provided.

Abstract: The invention provides an image encoding/decoding device and method. An encoding/decoding architecture of the invention includes: encoders for encoding image data into data blocks; a reordering multiplexer for receiving the data blocks and determining an order by which the data blocks are written into a memory according to an order of an achieved percentage of an encoding progress for each encoder; a memory writing unit, a memory dispatcher, a memory controller, and a memory reading unit, for writing the data blocks into the memory and reading the data blocks from the memory; a request demultiplexer for receiving the read data blocks from the memory reading unit and outputting the received data blocks according to data request signals; and decoders for generating the data request signals, receiving the output data blocks from the request demultiplexer, decoding the received data blocks, and then outputting the decoded data blocks.

Abstract: A method is disclosed for encoding and decoding integer values ranging over a known gamut of values used by a data system. By noting that a data system may store and/or transmit integer values over a predefined gamut having a minimum and a maximum limit, integer values at or near the maximum may be compressed to a greater degree than in conventional systems without any loss of data resolution.

Abstract: Systems and methods for representing low dynamic range data in compressed formats with a fixed size block allow low dynamic range data to be stored in less memory. The compressed formats use 8 bits per pixel to represent 24 bits of low dynamic range data for each pixel. The compressed format includes four or six endpoint values, a partition index that specifies a mask for each pair of the endpoint values, and an index for each pixel in the block. The indices are compressed to allow more bits for the endpoint values. Mode bits are included to distinguish between the different encodings and various blocks within a single compressed image may be encoded differently. Compressed low dynamic range values may be efficiently decompressed in hardware.

Abstract: An image processing system includes a decoder configured to decode an encoded image and an encoder configured to encode the image decoded by the decoder. The decoder includes a decoder adapted to decode the encoded image, and a detector adapted to detect, on the basis of the image, a fade period included in the image and supply a fade information signal indicating a detection result to the encoder. The encoder includes an acquisition unit adapted to acquire the fade information signal, and a changing unit adapted to change a process performed in the encoding of the image in accordance with the fade information signal.

Abstract: An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider re-usage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two N-bit operands as an input, adding the (N?M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.

Abstract: A method and apparatus for compressing signal samples uses block floating point representations where the number of bits per mantissa is determined by the maximum magnitude sample in the group. The compressor defines groups of signal samples having a fixed number of samples per group. The maximum magnitude sample in the group determines an exponent value corresponding to the number of bits for representing the maximum sample value. The exponent values are encoded to form exponent tokens. Exponent differences between consecutive exponent values may be encoded individually or jointly. The samples in the group are mapped to corresponding mantissas, each mantissa having a number of bits based on the exponent value. Removing LSBs depending on the exponent value produces mantissas having fewer bits. Feedback control monitors the compressed bit rate and/or a quality metric. This abstract does not limit the scope of the invention as described in the claims.

Abstract: Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data.

Abstract: A method for transmitting the value of a parameter in a compressed form, the method comprising the steps of: accepting successive numbers representing the value of a parameter; manipulating each number, the manipulation comprising placing the number in a form comprising a mantissa and an exponent, and defining a transmission mantissa to be transmitted; transmitting to a receiver, in turn, the transmission mantissas only of the successive numbers; and receiving the transmission mantissas of the successive numbers at the receiver, characterised by the steps of maintaining a record, at the receiver, of a receiver variable, the receiver variable initially corresponding to the exponent of an initial number; formulating at the receiver, for each received transmission mantissa, a reconstructed number comprising at least the transmission mantissa and an exponent corresponding to the receiver variable; and altering the receiver variable in a first manner if the transmission mantissa of the current number fulfils a fir

Abstract: Associative matrix compression methods, systems, computer program products and data structures compress an association matrix that contains counts that indicate associations among pairs of attributes. Selective bit plane representations of those selected segments of the association matrix that have at least one count is performed, to allow compression. More specifically, a set of segments is generated, a respective one of which defines a subset, greater than one, of the pairs of attributes. Selective identifications of those segments that have at least one count are stored. The at least one count that is associated with a respective identified segment is also stored as at least one bit plane representation. The at least one bit plane representation identifies a value of the at least one associated count for a bit position of the count that corresponds to the associated bit plane.

Abstract: An ability to compress packets is announced from a customer edge router (CE) to other CEs through a routing protocol packet. An announcement of that ability is received from another CE through a routing protocol packet. A compression technique is then matched. The CE receives compression information from the other CE in a routing protocol packet, and determines that a compression technique identified therein matches any compression technique the CE is programmed to use. The CE then flags packets transmitted from/received by the CE to be compressed/decompressed according to the matched compression technique. Alternatively, the CE may match by transmitting compression information identifying a compression technique to the another CE in a routing protocol packet; the another CE receives the routing protocol packet and determines that a compression technique identified in the compression information of the routing protocol packet matches any compression technique the another CE is programmed to use.

Abstract: Sensor data is received from one or more sensors. The sensor data is organized within a hierarchy. The sensor data is organized within a hierarchy that is non-dyadic. A processor of a computing device generates a discrete wavelet transform, based on the sensor data and based on the hierarchy of the sensor data, to compress the sensor data. The sensor data, as has been compressed via generation of the discrete wavelet transform, is processed.

Abstract: An image processing apparatus includes a decision unit configured to determine whether or not print image data includes copy-forgery-inhibited-pattern image data. Based on a decision result of the decision unit regarding whether or not the print image data includes the copy-forgery-inhibited-pattern image data, a processing unit of the image processing apparatus is configured to determine whether first compression processing is to be performed or second compression processing is to be performed and apply the decided compression processing to the print image data.

Abstract: Embodiments of the present invention are directed to a microcontroller which includes a Register Load Assist engine. The microcontroller can include no or minimal non-volatile memory which stores boot data. Thus, most of the boot data can be stored at a non-volatile memory external to the microcontroller. An external circuit can read the externally positioned non-volatile memory and send compressed boot data to the microcontroller. The boot data can be originally stored in compressed form in the external non-volatile memory or it can be compressed by the external circuit. The boot data can be received by the microcontroller and saved in an intermediate location in the microcontroller's internal volatile memory. The RLA engine can then uncompress the boot data and store various portions of it in their final destinations (such as, for example, in respective registers).

Abstract: A data transformation method capable of saving numeral operations, the data transformation method includes encoding a plurality of digital data to generate a plurality of sets of byte data according to an encoding mode, determining a plurality of repetition patterns of the plurality of sets of byte data, processing shift operations on the plurality of sets of byte data to generate a plurality of sets of shifted byte data according to positions of the plurality of repetition patterns located in the plurality of sets of byte data, processing addition operations on the plurality of sets of shifted byte data.

Abstract: An image processing method for decoding input encoded image data, which has undergone encoding processing by a predetermined format, image processing the decoded image data, and encoding the image-processed data to create output encoded data includes repeating the process of decoding, image processing and encoding processing and outputting the image data in image processing units subject to the image processing; and sorting the encoded data obtained from the repeated processing step and creating the output encoded data in an order defined by the format of the output encoded data for performing encoding processing on one picture plane. In this case, the repeated processing step includes decoding the input encoded data in the image processing units and outputting image data, image processing the decoded image data in the image processing units, and encoding processing the image-processed data in encoding processing units.

Abstract: The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves.

Abstract: The invention provides an image processing apparatus and method, for processing a captured or recorded image with a dimension of M×N temporarily stored in an external memory; M and N are both integers larger than 1. The image processing apparatus includes a reading module, a buffer, a first processing module, a second processing module, and a writing module. Particularly, the image processing apparatus and method of the invention is a tile-based apparatus and method, which can decrease the width of the buffer and further reduce the hardware cost.