Abstract: Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the first input set has exactly a predetermined number of high input signals. Each control output signal corresponds to a different predetermined number of high input signals. A second subcircuit has a second input set, a set of control inputs for receiving control output signals from the first subcircuit, and logic including a plurality of switches including one or more pass gates. Each switching component switches to connect or isolate one of the second input set to a common output. The control inputs control the switches. The first and second subcircuits are configured such that only one switch can be switched to connect at a time.

Abstract: A method and a bit counting device (100) count bits set to one in a data word of arbitrary size. The bit counting device (100) includes a first data register (110) for storing a data word, an offset register (112) for storing an offset value, a second data register (120), and a one-cycle shifter (114), electrically connected to the first data register (110), to the second data register (120), and to the offset register (112), for shifting the data word by a value stored in the offset register (112) and storing the shifted data word in the second data register (120).

Abstract: Methods and apparatuses for run length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor in response to the microprocessor receiving a single instruction includes: receiving a first list of a plurality of elements from a first vector register; generating a plurality of run values respectively for the first list of elements, at least one of the plurality of run values indicating the number of consecutive elements of a first value immediately preceding the corresponding element in the first list; and outputting the plurality of run values into a second vector register; where the above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of the population count and bit shift circuits so that the execution of operations is more balanced, which, in effect, increases computational speed and efficiency. An apparatus that integrates population count circuitry and bit shift circuitry has also been developed. The apparatus comprises a plurality of dynamic stages followed by static stages. The dynamic stages involve the use of dynamic nodes which represent values dependent upon values of individual bits in the pointer and the sparse vector. The apparatus further allows for an expansion through circuit repetition so that the topology of the apparatus can change according to the size of the pointer and sparse vector.

Abstract: There is disclosed a circuit for determining if an N-bit number is equal to a power of two. The circuit comprises: 1) a first stage of detection gates, each of the first stage detection gates capable of receiving a first data bit and a second data bit from the N-bit number and generating a first output bit and a second output bit, wherein the first and second output bits are 01 if the first and second data bits are different and are one of 00 and 11 if the first and second data bits are the same; and 2) a second stage of detection gates coupled to the outputs of the first stage of detection gates, each of the second stage detection gates receiving three of the first stage output bits and generating a first output bit and a second output bit, wherein the first and second output bits of the second stage detection gates are 01 if only one of the three first stage output bits is equal to Logic 1 and are one of 00 and 11 otherwise.

Abstract: Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes am−1:0 and bm−1:0, respectively. In one embodiment, the circuit asynchronously generates a binary code cm−1:0 representing an average of the binary codes am−1:0 and bm−1:0 generated by the first and second circuits, respectively.

Abstract: In order to provide an inexpensive binary data counting device of which the processing is done at high speed and which can be implemented with a small circuit scale, a shifter array 10 is provided for outputting binary data of N bits, which comprises N×(N+1)/2 shifters of which the control inputs are the data expressed in a binary manner comprising N bits so that binary data wherein is are filled in from the right in the same number as 1s in the data expressed in a binary manner comprising N bits are outputted by controlling the operation of each shifter in the shifter array 10 with each bit value of the data expressed in a binary manner comprising N bits. An encoder is also provided for converting said binary data into a multi-valued number in accordance with the position of 1 in said binary data on the MSB side.

Abstract: One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits. Next, the system converts the thermometer code into a one-hot code in which only one bit has a logical one value. Finally, the system converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.

Abstract: Counting the number of set bits in an n-bit data word in a data processing system. The process involves generating at least p1 intermediate n-bit words, where 1<p1<n, by masking and shifting the data word such that each intermediate word has n/p1p1-bit fields and n of the fields of the intermediate words represent the values of respective bits of the data word. The intermediate words are then summed to generate an n-bit derivative word having n/p1p1-bit fields whereby each field of the derivative word represents the sum of a respective group of bits of the data word. The fields of the derivative word can then be summed in various ways by performing shift, add and mask operations on the derivative word. The resulting sum value represents the number of set bits in the data word.

Abstract: An apparatus and method is provided for determining locations of a predetermined value in a sequence of data bits. Each location is determined independently of the others thereby allowing them to be found more quickly. This has particular application to block memory loads and block stores to memory, wherein ones in the register list in the instruction word indicate the registers to be loaded or stored. Thus, in these applications the present invention enables the positions of these ones to be determined quickly.

Abstract: There is disclosed a circuit for determining if an N-bit number is equal to a power of two. The circuit comprises: 1) a first stage of detection gates, each of the first stage detection gates capable of receiving a first data bit and a second data bit from the N-bit number and generating a first output bit and a second output bit, wherein the first and second output bits are 01 if the first and second data bits are different and are one of 00 and 11 if the first and second data bits are the same; and 2) a second stage of detection gates coupled to the outputs of the first stage of detection gates, each of the second stage detection gates receiving three of the first stage output bits and generating a first output bit and a second output bit, wherein the first and second output bits of the second stage detection gates are 01 if only one of the three first stage output bits is equal to Logic 1 and are one of 00 and 11 otherwise.

Abstract: A method for generating data characterizing an item described by an ordered string of characters, comprises the steps of: (i) for a set of separation metrics each representing a unique number of positions of separation between arbitrary characters in a character group in the ordered string of characters, associating first with each separation metric; generating a set of character groups, wherein each character group comprises at least two characters contained within the ordered string of characters; and (ii) for at least one given character group in the set of character groups, for each given separation metric in the set of separation metrics, generating second data representing number of occurrences that the given character group satisfies the given separation metric; generating third data associated with the given character group, wherein the third data is based upon the second data and the first data; and storing the third data in memory for subsequent use.

Abstract: An electronic device that counts the number of set bits in an input vector and asserts an output vector representative of the number of set bits. The electronic device uses a combination of dynamic logic components and static logic components to minimize gate delay. The electronic device may be configured so that dynamic logic components are used to count set bits in the least significant portion of an input vector while static logic components count set bits in the most significant portion of an input vector. The electronic device may include circuitry for preventing a false assertion of an output due to leakage current.

Abstract: A method and a bit counting device (100) count bits set to one in a data word of arbitrary size. The bit counting device (100) includes a first data register (110) for storing a data word, an offset register (112) for storing an offset value, a second data register (120), and a one-cycle shifter (114), electrically connected to the first data register (110), to the second data register (120), and to the offset register (112), for shifting the data word by a value stored in the offset register (112) and storing the shifted data word in the second data register (120).

Abstract: A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of the population count and bit shift circuits so that the execution of operations is more balanced, which, in effect, increases computational speed and efficiency. An apparatus that integrates population count circuitry and bit shift circuitry has also been developed. The apparatus comprises a plurality of dynamic stages followed by static stages. The dynamic stages involve the use of dynamic nodes which represent values dependent upon values of individual bits in the pointer and the sparse vector. The apparatus further allows for an expansion through circuit repetition so that the topology of the apparatus can change according to the size of the pointer and sparse vector.

Abstract: A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: There is disclosed a circuit for determining the number of Logic 1 bits in a group of N data bits.

Abstract: An input bit string is latched sequentially by a D latch initialized to the logical level “1” and a plurality of D latches initialized to logical level “0”. If the data bit released from the last D latch, of the plurality of D latches, has a logical level “1”, a detection enabling circuit continuously keeps outputting a signal having a logical level “1”. This detection enabling circuit comprises an OR gate and another D latch. If the signal output by the detection enabling circuit has a logical level “1” and the bit pattern held in all of the D latches is “11111”, then an AND gate outputs a bit string detection signal having a logical level “1”.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: A novel architecture is described for applying a sum and threshold function to a weightless input string and a weightless threshold string. The sum and threshold function is carried out by distributing the input bits in random manner (12) between a number of sum and threshold devices (14), whose outputs are supplied to a second layer of one or more sum and threshold devices (16).

Abstract: A parallel bit counter for counting the number of bits having a particular level in parallel input data. The counter includes a 2-bit sorter adapted to sort "high" and "low" bit fields of parallel input data in accordance with a bit sort method, and a caster adapted to detect a boundary between the sorted "high" and "low" bit fields and to code the resultant signal obtained after the detection, indicative of the number of "high" bits included in the input data, into its equivalent binary form. Accordingly, the counter can prevent a degradation in the counting speed resulting from a multiple adder operation and a carry set-up time.

Abstract: In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number detectors set for respective places, the number of the high signals in the input values is output in the binary notation, and outputs from a plurality of NDs are added by full adders to execute a high speed operation without carries. In addition, values with no common places are integrated into single data before being added.

Abstract: First and second binary words representing a third binary word having a predetermined number of bits are determined in a data processing system by storing a first word the same as the third binary word and storing a second word having the predetermined number of zero bits in the data processing system. A pair of consecutive order bits having a binary "1" value is searched for in the third binary word, starting at the least significant bit of the third binary word. Each of the first and second words is incremented by 2 raised to a lowest order of the pair of consecutive order bits, for a pair of consecutive order bits having a binary "1" value found in the binary word. Preferably, the steps of searching and incrementing are repeatedly performed for pairs of consecutive order bits in the third binary word having binary "1" value distinct from previously found pairs of lesser order consecutive order bits in the third binary word.