Abstract: A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.

Abstract: The disclosed embodiments relate to a system that generates a pseudorandom number. During operation, the system maintains a current dot-product for a thread, wherein the current dot-product is a dot-product between a pedigree for the thread and an array of coefficients, wherein the pedigree for the thread comprises an array of elements that specify a path to the thread from a root in a dynamic multi-threading hierarchy, and wherein the array of coefficients includes a coefficient for each level in the dynamic multi-threaded hierarchy. To generate the pseudorandom number, the system incrementally computes a new dot-product from the current dot-product without performing a multiplication operation by adding a coefficient associated with the thread's level in the dynamic multi-threading hierarchy to the current dot-product. Next, the system performs a mixing operation on the new dot-product to produce the pseudorandom number. Finally, the system updates the current dot-product to the new dot-product.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for producing programmable probability distribution function of pseudo-random numbers that can be utilized for filtering (dropping and passing) neuron spikes. The present disclosure provides a simpler, smaller, and lower-power circuit than that typically used. It can be programmed to produce any of a variety of non-uniformly distributed sequences of numbers. These sequences can approximate true probabilistic distributions, but maintain sufficient pseudo-randomness to still be considered random in a probabilistic sense. This circuit can be an integral part of a filter block within an ASIC chip emulating an artificial nervous system.

Abstract: A random number generation method and apparatus are disclosed. In the random number generation method, a random number is generated using a plurality of digital signals existing in various storage devices, and thus the speed at which a random number is generated may be significantly increased.

Abstract: A Self-Timed Logic Entropy Bit Stream Generator (STLEBSG) outputs a bit stream having non-deterministic entropy. The bit stream is supplied onto an input of a signal storage ring so that entropy of the bit stream is then stored in the ring as the bit stream circulates in the ring. Depending on the configuration of the ring, the bit stream as it circulates undergoes permutations, but the signal storage ring nonetheless stores the entropy of the injected bit stream. In one example, the STLEBSG is disabled and the bit stream is no longer supplied to the ring, but the ring continues to circulate and stores entropy of the original bit stream. With the STLEBSG disabled, a signal output from the ring is used to generate one or more random numbers.

Abstract: A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.

Abstract: The invention relates to a circuit for generating a true, circuit-specific and time-invariant random binary number, having: a matrix of K?L delay elements that can be connected to each other by means of L?1 single or double commutation circuits into chains of delay elements of length L, a single or double demultiplexer connected before the matrix, a single or double multiplexer connection after the matrix, and a run time or number comparator, wherein the setting of the commutation circuits, the demultiplexer, and the multiplexer can be prescribed by a control signal, wherein the circuit comprises a channel code encoder whereby code words of a channel code can be generated and a transcriber, whereby code words of the channel code can be transcribed into the control signal of the L?1 single or double commutation circuits, and a method for generating a true, circuit-specific and time-invariant random number by means of a matrix of L?K delay elements, L?1 single or double commutation circuits, a single or double

Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.

Abstract: A method of generating a random number using nonvolatile memory and an apparatus for the same are provided. The method of generating a random number includes reading random number state information from nonvolatile memory when power is supplied; updating the random number state of a random number generator using the random number state information and a saving entropy source, thereby producing updated random number state information; storing the updated random number state information in the nonvolatile memory; updating a random number state of the random number generator using the updated random number state information and a generating entropy source, thereby producing a generating random number state information; and producing a random number to be used in an application program using the generating random number state information and the generating entropy source.

Abstract: A random number quality control circuit capable of fast control of the level of random number quality is present. When a “0” output section and a “1” output section generate random numbers by individually receiving a random number signal, a random number quality monitor monitors an unbalance between the numbers of “0”s and “1”s. If a deviation from a desired ratio is found, a drive controller controls the reception characteristics of the “0” output section and “1” output section individually so that the deviation will be compensated for. The amount of information intercepted between a sender and a receiver can be reduced by maintaining the mark ratio of shared random numbers at 50%.

Abstract: Generating a number based on mask and range constraints. For example, a method of generating a pseudo random number satisfying a range constraint and a mask constraint may include determining a number of possible solutions satisfying the range constraint and the mask constraint; selecting an index representing a solution of the possible solutions; and generating the pseudo random number based on the index. Other embodiments are described and claimed.

Abstract: A method for assessing an output of a random number generator which is provided by two phase-locked loops of the random number generator includes: receiving, by a checking system, the output of the random number generator for at least two sampling cycle, wherein for each sampling cycle (i) the output of the random generator includes a sequence of sample values between a starting value and an end value, and (ii) all sample values between the starting value and the end value in the respective cycle are entered into a signature; and comparing, by the checking system, the signatures from the at least two sampling cycles to one another.

Abstract: A signal is generated by obtaining an unconstrained random bit sequence. The unconstrained random bit sequence is modified to satisfy a constraint and the modified random bit sequence is output.

Abstract: An invention is presented with new and simple ways of spectral tests applicable to the multiplicative congruential generator (d,z) with any odd modulus d and any multiplier z coprime to d. The invention realizes powerful ways to select multipliers of excellence with greatly improved statistical performances in their generation of uniform and independent random numbers. Related two inventions for new designs of the generator (d,z) are presented at the same time, as strongly facilitative for the application of advocated extended spectral tests, by exploiting specific structures of moduluses formed by two odd-prime-powers so as to realize improved periodic structures that are set conveniently out of tune avoiding harmful resonances.

Abstract: A data processing apparatus is provided for producing a randomized value. A cell in the data processing apparatus comprises a dielectric oxide layer and stress voltage circuitry is configured to apply a stress voltage across the dielectric oxide layer of the cell to cause an oxide breakdown process to occur. Oxide breakdown detection circuitry is configured to determine a current extent of the oxide breakdown process by measuring a response of the dielectric oxide layer to the stress voltage and randomized value determination circuitry is configured to determine a randomized value in dependence on the current extent of the oxide breakdown process.

Abstract: Among other things, systems and techniques are described for authenticating one or more client devices. A system includes one or more client devices and a server to communicate with the one or more client devices over a network. The server receives a request for network connection from at least one of the client devices. In response to the received request, the server performs authentication of the requesting client device based on at least two factors. The at least two factors includes a transmission control protocol (TCP) header verification to identify a media access control (MAC) address of the requesting client device as an authorized or unauthorized MAC address; and a challenge-reply verification performed based on the TCP header verification. The challenge-reply verification includes sending a challenge message sent to the requesting client device; receiving a reply message from the requesting client device; and identifying the received reply message as a correct or incorrect reply.

Abstract: Techniques are described for generating high quality entropy in a software only or a hardware assisted software environment, such as a virtualized environment. Embodiments of the invention describe creating an entropy pool within the virtualized environment using multiple sources of entropy. The entropy pool may be used in creating dynamically customizable and high entropy RNG and PUF. The sources of entropy may include trusted sources, untrusted sources and entropy sources with a varied scale of trust and entropy quality associated with them.

Abstract: An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information.

Abstract: A wireless communications method is provided. The method includes employing a processor executing computer executable instructions stored on a computer readable storage medium to implement various acts. The method also includes generating cyclic shifts for a sequence generator by masking shift register output values with one or more vectors. The method includes forwarding the sequence generator to a future state based in part on the output values and the vectors.

Abstract: A random number generator of a processor comprises a whitener for reducing the bias in random numbers generated by the random number generator. The whitener receives a random number of a first length read by an array of latches with inputs from an array of oscillators. The whitener dynamically creates a mask of the first length based on a parity of at least one previous random number read from the array of latches during at least one cycle prior to reading the random number. The whitener applies a compare operation between the random number and the mask to generate a whitened random number of the first length, with reduced bias, without reducing randomness.

Abstract: A random number generator of a processor comprises a whitener for reducing the bias in random numbers generated by the random number generator. The whitener receives a random number of a first length read by an array of latches with inputs from an array of oscillators. The whitener dynamically creates a mask of the first length based on a parity of at least one previous random number read from the array of latches during at least one cycle prior to reading the random number. The whitener applies a compare operation between the random number and the mask to generate a whitened random number of the first length, with reduced bias, without reducing randomness.

Abstract: The present invention relates to an apparatus and method for acquiring noise source entropy for a random number generator, which use contention for access to memory between Graphical Processing Unit (GPU) cores. For this, an apparatus for acquiring noise source entropy for a random number generator includes a core calling unit for simultaneously calling a plurality of cores to a critical area, and a noise source entropy generation unit for generating noise source entropy based on a sequence of entry of the plurality of cores into the critical area.

Abstract: A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequence of values from the first circuit and producing an output indicative of the degree of entropy of the random sequence of values, and a third circuit that adjusts the adjustable input of the first circuit in response to the output of the second circuit.

Abstract: A method of generating non-deterministic and non-periodic random bits including the steps of providing a plurality of noise generators; providing a trigger based upon an outside world input; sampling the output signal of one of the noise generators upon the provision of the trigger; generating a first random number based upon the value of the sampled signal; and wherein the identity of the noise generator to be sampled is determined based upon a previous random number generated.

Abstract: An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.

Abstract: A random number generation apparatus includes: a random noise generation element comprising a source region and a drain region, a tunnel insulation film, a gate electrode, and a charge trap portion provided between the tunnel insulation film and the gate electrode and being capable of trapping charges, random noise being generated in a drain current flowing between the source region and the drain region on the basis of charges trapped in the charge trap portion; a random number conversion circuit for converting random noise generated from the random noise generation element to a random number; a first test circuit for performing a random number test to test quality of the random number output from the random number conversion circuit; and an initialization circuit for pulling out charges in the charge trap portion of the random noise generation element to the semiconductor substrate through the tunnel insulation film and thereby initializing the charge trap portion.

Abstract: Systems and methods for using carry-less multiplication (CLMUL) to implement erasure code are provided. An embodiment method of using CLMUL to implement erasure code includes initiating, with a processor, a first CLMUL call to calculate a first product of a data bit word and a constant, partitioning, with the processor, the first product into a high portion and a low portion, and initiating, with the processor, a second CLMUL call to calculate a second product of the high portion and a hexadecimal number portion, a bit size of the second product less than a bit size of the first product. The second product, or a third product generated by a third CLMUL call, is used to calculate a parity bit. Because the second product or the third product has a number of bits equivalent to the number of bits used by the processor, the erasure codes are more efficiently implemented.

Abstract: A method of assessing parallel random number streams includes mixing two or more parallel random number streams. Mixing the parallel random number streams may include pairing at least one of the random number streams with other random number streams. For each mixed random number stream, an inter-stream correlation value may be computed based on a correlation among the random number steams used. A quality metric for the parallel random number streams may be determined from inter-stream correlation values for the two or more mixed streams created from the parallel random number streams. A quality metric for a single random number stream may be computed by segmenting the single random number stream into multiple substreams and applying the methods of mixing streams and computing quality metric in the case of parallel streams.

Abstract: A true random number generator (TRNG) uses sources of uncertainty found within graphics processing units (GPUs) together with signal processing techniques, for example histogram equalization, to obtain maximum entropy.

Abstract: A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.

Abstract: Embodiments of methods and systems for producing random values include a first module that provides a random data request (e.g., a request for an unspecified length of random data) to a random number generator. The random number generator generates random data in response to the random data request, and multiple random values derived from the random data are stored in a buffer. In response to receiving a request for a random value (e.g., an initialization vector), the first module produces the random value based on the multiple random values stored in the buffer. The system also may be configured to receive requests for other types of random values, and to fulfill those requests using random data that is not buffered (e.g., random data that is received directly from the random number generator in response to a request for a specified length of random data).

Abstract: The present invention relates to a method and system for providing an analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. A band-limited digital noise signal indicative of a Gaussian noise signal having a predetermined Gaussian probability distribution function is ?? modulated generating a pulse-density modulated 1-bit sequence representing a Gaussian noise signal having a predetermined probability distribution function, bandwidth and center frequency. Using an analog low-pass filter the pulse-density modulated 1-bit sequence is then converted into a respective analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. The method and system are successfully employed in numerous applications such as in histogram testing and probabilistic digitization.

Abstract: A method and a device for generating a random output bit sequence are put forth. In the case of these, an input is inputted into a set-up of finite state machines. The set-up ascertains an output on the basis of the input; the input being inputted into the set-up, linked to a one-way function.

Abstract: The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder 121 performs the coding in such a way that 1<w0 and w1<w0 are satisfied when the maximum column weight of the cyclic matrices in the check matrix of a certain code whose code rate is not the minimum value among the LDPC codes is defined as w0 and the maximum column weight of the cyclic matrices in the check matrix of a code having a code rate lower than that of the certain code is defined as w1.

Abstract: A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator.

Abstract: A method, an apparatus, and a computer program product for generating and processing random numbers are provided. An apparatus comprises a processing system that includes a processor, a random number generator and a pair of buffers. A first buffer receives low-entropy random numbers generated by the random number generator and a second buffer provides high-entropy random numbers directly to a processing system. The processing system may directly access the second buffer in response to an instruction executed by the processing system. The processing system responds to an interrupt based on occupancy levels of the buffers by conditioning low-entropy random numbers read from the first buffer to obtain high-entropy random numbers that are then stored in the second.

Abstract: A system, method, and computer program product are provided for determining a random value. In use, a width value is identified. Additionally, a random value is determined, utilizing the width value, wherein determining the random value is capable of being synthesized as a hardware design. Further, the random value is returned.

Abstract: One feature pertains to a method that reduces the computational delay associated with generating prime numbers. The method includes generating a first random number having a plurality of bits. A first primality test is then executed on the first random number. Then, it is determined whether the first random number generated fails or passes the first primality test. If the first random number fails the primality test then a portion but not all of the plurality of bits of the first random number are replaced with an equal number of randomly generated bits to generate a second random number. Next, a primality test is again executed on the second random number. This process is repeated until a prime number is detected.

Abstract: Confidential information is provided to a proxy computer in communication between an unsecured computer and a computer having information desired by a user. The proxy computer receives the confidential information in either an encrypted form or having arbitrary information combined therewith. The proxy computer ascertains the confidential information and forwards it to the computer having the information desired by the user.

Abstract: An apparatus includes multiple oscillators, where each oscillator includes an inverter chain. The apparatus also includes combinatorial logic configured to generate a random number having one or more bits. The combinatorial logic is configured to generate each bit by combining two or more signals from at least two oscillators that have inverter chains with different prime numbers of inverters. The combinatorial logic may be configured to generate each bit using signals from a unique combination of oscillators. The combinatorial logic may also be configured to combine the signals asynchronously and sample the combined signal synchronously using a synchronous sampling clock, where at least one of the signals is not harmonically related to the sampling clock. Each of at least one of the oscillators may include multiple taps configured to provide multiple signals, and the multiple signals from one oscillator could have different asynchronous phases relative to the sampling clock.

Abstract: In one embodiment, a mechanism for string hashing using a random number generator is disclosed. In one embodiment, a method includes dividing an input stream provided to a hashing module into a plurality of subsets of ‘n’ bits, entangling, by a mixer of the hashing module, one of the subsets of ‘n’ bits by a next sequential output of a pseudo-random number generator (PRNG), adding a product of the entangling to an accumulator of the hashing module, repeating the entangling and adding until all subsets of the plurality of subsets have been processed, and returning a value in the accumulator as a hash result value.

Abstract: An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure. A method for testing randomness performed by the apparatus is also included.

Abstract: It is made possible to provide a random number generation device which generates a physical random number with as little power dissipation as possible. A random number generation device includes: a ring oscillator having at least one set, each set comprising a current noise source and a Schmitt inverter configured to receive an output of the current noise source; and a conversion circuit configured to convert output frequency fluctuation of the ring oscillator to a random number and output the random number.

Abstract: A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data.

Abstract: A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a pseudo-random sequence generator circuit, a decoder circuit, and a pseudo-random sequence reconstitution circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a detected output. The pseudo-random sequence generator circuit is operable to generate an interim data sequence and to generate a second data set based upon a combination of the detected output and the interim data sequence. The decoder circuit is operable to apply a data decode algorithm to a derivative of the second data set to yield a third data set.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate pseudo-random sequences in response to a first m-sequence and a second m-sequence, where the first m-sequence is initialized with a pre-calculated constant and the second m-sequence is initialized based on a pre-defined initial sequence and a table of pre-calculated values indicating which components of the initial sequence participate in initializing the second m-sequence. The second circuit may be configured to store the table of pre-calculated values.

Abstract: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

Abstract: A delay device for generating a signal for a random component in a random number generator is disclosed. The delay device includes a delay module, for generating a plurality of delayed signals, wherein each delayed signal has a delay time and the delay time is different from each other; a first multiplexer, coupled to the delay module, for outputting a delayed signal among the plurality of delayed signals as a delayed trigger signal to control the random component to generate a random bit; and a delay selector, coupled to the first multiplexer, for generating a selecting signal to control the first multiplexer to select to output the delayed signal as the delayed trigger signal.

Abstract: A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.