Abstract: Techniques are described for sampling rate conversion in the digital domain by up-sampling and down-sampling a digital signal according to a selected intermediate sampling frequency. A prototype anti-aliasing filter that has a bandwidth with multiple factors is stored in memory. The techniques include selecting an intermediate sampling frequency to be an integer multiple of a desired output sampling frequency of a digital signal based on the factors of the prototype filter, and selecting a down-sampling factor to be the same integer associated with the selected intermediate sampling frequency. A filter generator generates an anti-aliasing filter for the selected down-sampling factor based on the prototype filter.

Abstract: Systems and methods are provided for detecting abnormal conditions and preventing abnormal situations from occurring in controlled processes. Statistical signatures of a monitored variable are modeled as a function of the statistical signatures of a load variable. The statistical signatures of the monitored variable may be modeled according to an extensible regression model or a simplified load following algorithm. The systems and methods may be advantageously applied to detect plugged impulse lines in a differential pressure flow measuring device.

Abstract: A system, method, and apparatus for calculating non-linear functions with finite order polynomials are presented herein. Use of finite order polynomials allow calculation of the non-linear functions using fixed point arithmetic operations resulting in significant cost savings.

Abstract: An elliptic curve processing apparatus that performs operations on elliptic curves specified over binary polynomial fields includes a functional unit that has a digit serial multiplier with a digit size of at least two bits. The elliptic curve processing apparatus performs reduction for respective generic curves using arbitrary irreducible polynomials, which correspond to respective ones of the generic curves. The elliptic curve processing apparatus may include hardwired reduction circuits in the functional unit for use with respective named curves. A storage location in the elliptic curve processing apparatus may be used to specify whether an operation is for one of the named curves or for one of the generic curves.

Abstract: Time delay and frequency offset calculation systems and related methods. System implementations include modules coupled together configured to calculate a time delay and a corresponding frequency offset of a second signal delayed in time relative to a first signal with the maximum value of a magnitude of a delay optimization function. Implementations of a method for calculating a time delay and frequency offset calculate the maximum value of the delay optimization function by generating the cross-correlation of one or more adjacent discrete Fourier transformed blocks corresponding to the first signal and second signal, respectively, of two or more discrete Fourier transformed blocks. The maximum value of the delay optimization function is then identified. Implementations of the method may compare the identified maximum value of the magnitude of the delay optimization function with a threshold to determine whether to continue processing for additional adjacent discrete Fourier transformed blocks.

Abstract: The present invention provides a technology which can perform a precise restoration to a distribution of original information by carrying out an iterative calculation using only a distribution of degraded information. The method according to the present invention performs the restoration to original information based only on degraded information. The method according to the present invention considers the distribution of the degraded information and the distribution of the original information as distributions of probability density functions, and considers a transfer function of a transfer system as a probability density function of a conditional probability.

Abstract: A look-up table outputs an initial value, an inclination of a straight line and a correction value in response to an entry-of a high-order bit string of an operand. An offset circuit calculates an offset of the low-order bit string. A correction circuit outputs the initial value obtained by adding the correction value to at least one of the initial value and the inclination when the correction is necessary. A multiplier calculates a product of the inclination and the offset. An adder calculates the sum of the initial value and the product.

Abstract: Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from instruction memory during a runtime phase.

Abstract: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

Abstract: An equivalent material constant calculation system that calculates an equivalent material constant of a structure constituted by a plurality of materials includes a shape data input portion that inputs shape data, a material data input portion that inputs material constant data, a dividing portion that divides the structure into a plurality of small regions, and a small region interior calculation portion that calculates equivalent material constants in the small regions, in which the small region interior calculation portion, based on the shape data and material constant data, with a function that includes a value in a variable that expresses a position in at least one direction in the small region, expresses an equivalent material constant for a region that is a portion of a small region, and using the function, calculates an equivalent material constant for the small region with respect to the at least one direction.

Abstract: A divide-by-N clock frequency divider producing N non-overlapping clocks each with precise 1/N duty ratio is implemented by a counter, a token generator and N-bit shift register. Every N clock cycles, a pulse is generated as a token from a logical combination of signals from the counter. The pulse is passed along a shift register having balanced load capacitances under control of the clock edge, ensuring a precise 1/N duty ratio that is unaffected by load capacitances from the fault state detection and/or reset circuitry. In this manner, a higher operating frequency may be achieved with low power consumption.

Abstract: Using different number of data bits to represent points in corresponding different sections of a high order monotonic curve in a floating point format. More number of data bits are used to represent one section of the curve, while correspondingly fewer data bits are used to represent another section of the curve. In one embodiment, the differences of mantissa values of successive points are stored in a memory to obtain compression, but with different number of bits for different sections of the curve. The absolute values of the exponents for each section are also stored. The high order monotonic curve may represent a de-gamma curve and used in processing video signals which are to be de-gamma corrected.

Abstract: A system and method for automatically generating a computation mesh for use with an analytical tool, the computation mesh having a plurality of ?-grid lines and ?-grid lines intersecting at grid points positioned with respect to an inner boundary and an outer boundary. The system and method include one or more mesh equations having one or more source terms that include: a grid clustering component based on a Jacobian scaling parameter, a source decay parameter, and one or more first point distance parameters, and a cell shape modifying source component based on one or more source parameters selected from the group consisting of a smoothing source parameter, an area source parameter, an orthagonality source parameter, and any combinations thereof.

Abstract: A comprehensive method for generating mathematical equations and symbolic scientific expressions using pure HTML and CSS is disclosed. This method renders the equations portable and editable and contrasts with previous procedures that represent equations using a whole built-up graphic objects. An application of the method using HTML and JavaScript is also disclosed. Finally, a procedure for documenting the equations within the HTML document is included such that the equations are interpretable and can be converted to and from other formats such as LaTex, MATHML, or linear representation.

Abstract: Methods and apparatuses are presented for determining coefficients for a polynomial-based approximation of a function, by iteratively estimating a first coefficient, reducing the first coefficient to a lower precision to obtain a first limited-precision coefficient, analytically calculating a second coefficient by taking into account the first limited-precision coefficient, reducing the second coefficient to a lower precision to obtain a second limited-precision coefficient, iteratively estimating a third coefficient by taking into account at least one of the first limited-precision coefficient and the second limited-precision coefficient, and reducing the third coefficient to a lower precision to obtain a third limited-precision coefficient.

Abstract: The circuit of this invention performs clock division with dynamic divide-by value change capability. This circuit provides low area and low latency. The clock divider is conventional except for the logic that handles the dynamic divide-by value change. When the divide-by value is changed by the user, such as through software, the changed value is recorded in a register but does not affect the divider immediately. Once the changed divide-by value is recorded, the divider clock output is allowed to continue till it reaches ‘low’ and is shut off. Then the recorded value is sent to the divider. The divider then generates a clock signal corresponding to the new divide-by value. The clock gating is then disabled and the clock propagates. This implements glitch free clock switching. This implementation of clock selection or switching provides low area and low latency for switching.

Abstract: Methods and apparatus for determining approximating polynomials using instruction-embedded coefficients are disclosed. In particular, the methods and apparatus use a plurality of coefficient values stored in a plurality of instructions. The coefficient values are associated with a runtime approximating polynomial of a K-th root family function. The coefficient values and the instructions stored in an instruction memory enable the processor system to determine a K-th root family function approximation value based on the runtime approximating polynomial.

Abstract: A method for reducing jitter in an output signal from a frequency synthesizer using a control word having a fractional bit includes dividing the output signal by a predetermined divisor to present a modified output signal substantially free of jitter.

Abstract: An approximation method and system for series expansion of functions include the steps and functions, respectively, of: expanding an input function in Taylor series up to an (N?1)-th term; expanding the input function in Taylor series up to the N-th term; multiplying the expanded result up to the (N?1)-th term by a predetermined weight ?; combining the expanded result up to the (N?1)-th term, multiplied by ?, and the expanded result up to the N-th term; and dividing the combined result by (?+1).

Abstract: Electronic device (10) to calculate linear functions and to calculate and generate non-linear functions, intended to process signals. The electronic device (10) is provided with a calculator unit (11) to calculate linear functions, a device (12) to generate arbitrary functions, including nonlinear functions, and a selector device (13) to selectively put the electronic device (10) in a first mode to calculate linear functions and a second mode to generate non-linear functions.

Abstract: The present invention teaches a method for generating an output value corresponding to an input value via a first function comprising a first section and a second section with the use of a lookup table, comprising: prestoring a plurality of first sampling points corresponding only to a third section of a second function, wherein the second function further includes a fourth section and there is a first mathematical transformation between the first function and the second function; receiving the input value corresponding to the first section; generating the output value based on at least one of the first sampling points through performing the first mathematical transformation on the first sampling point; and outputting the output value.

Abstract: Techniques are described for sampling rate conversion in the digital domain by up-sampling and down-sampling a digital signal according to a selected intermediate sampling frequency. A prototype anti-aliasing filter that has a bandwidth with multiple factors is stored in memory. The techniques include selecting an intermediate sampling frequency to be an integer multiple of a desired output sampling frequency of a digital signal based on the factors of the prototype filter, and selecting a down-sampling factor to be the same integer associated with the selected intermediate sampling frequency. A filter generator generates an anti-aliasing filter for the selected down-sampling factor based on the prototype filter.

Abstract: The secure integrated circuit (1) further includes storage means (2) in which confidential data is stored, such as an encryption programme and at least an encryption key, and a microprocessor unit (3) for executing the encryption programme. Said circuit further includes an oscillator stage (4, 5) supplying clock signals (CLK) in particular for clocking the sequence of operations in the microprocessor unit (3), and a random number generator (6) connected to the microprocessor unit. A random number (RNGosc) generated by the random number generator is supplied to the input of the oscillator stage to configure it such that the frequency of the clock signals supplied by the oscillator stage depends on said random number. The oscillator stage includes an RC type oscillator, in which a certain number of resistors and/or capacitors can be selected by the random number introduced at the input of the oscillator stage.

Abstract: A digital synthesizer includes a digital radio frequency memory (DRFM) for storing phase values and corresponding digital signals. The digital synthesizer includes a digital processing circuit receiving input from the DRFM, the circuit including tapped delay lines and a summer summing the output of the tapped delay lines. The digital synthesizer includes a signal modulator independently synthesizing within each tapped delay line a frequency modulated and gain scaled signal, wherein input to the tapped delay lines are phase values from the DRFM.

Abstract: A sequence generator for generating a pseudo random sequence for random number generation or a stream cipher engine includes a plurality of linear feedback shift registers operable to generate a plurality of binary sequences. A plurality of nonlinear functions having the binary sequences as their input and operable to generate a second plurality of binary sequences. There are at least two switches and a controller including a shift register operable to control said first and second switches. The first switch is operative to select one of the second plurality of binary sequences to the first bit of the shift register, and the second switch is operative to select one of said second plurality of binary sequences to the output of the sequence generator.

Abstract: A waveform generator for use in IQ modulation in a wireless cellular device having an FM waveform generator (104) that is programmable to generate a desired FM frequency deviation; a digital accumulator (108, 110, 112) to provide phase generation. First and second look-up tables 114 and 116 use the 6 MSBs and the 6 LSBs of 12-bit digital accumulator values to look up phase-space values that are combined in complex multipliers (130, 140), which are re-used from other parts of the circuit. This provides the following advantage(s): Support of both FM and I/Q modulation techniques for constant envelope modulation; low cost implementation; and flexibility to address multimode systems.

Abstract: The present invention provides a method to improve the frequency resolution and phase noise of a synthesized RF signal. It also results in the superior characteristics of instantaneous frequency changeability, wide frequency setting ability, and fully digital ASIC implementation ability. The synthesized RF signal is generated from a higher reference frequency using a variable pulse stretching technique. The amount of the pulse stretch in each cycle is controlled by a phase increment value and is implemented using programmable delay lines. Pulse stretching is extended beyond one cycle by pulse swallowing, allowing the generation of an RF signal from DC up to the input reference clock signal frequency.

Abstract: In order to generate a multiple of a unit U, N times U, by a digital circuit is provided, where U is a rational number and N is a natural number, the method comprises the following steps (1) to (5). (1) Where A, B and C are natural numbers, A>1, B>C and U=A+C/B, the values A, B and C are stored. (2) A multiple of A, N times A, and a multiple of C, N times C are generated. (3) The multiple of C is compared with the denominator B. (4) The multiple of A is modified according to the result of the comparing step (3). (5) The modified multiple of A is output as the multiple of U.

Abstract: An exemplary radar system includes a waveform generator that generates a control waveform. An in-phase and quadrature modulator receives the control waveform from the waveform generator and in turn generates a waveform output that is amplified by a power amplifier before being transmitted from an antenna.

Abstract: The synthesizer and method provide a relatively wideband swept frequency signal and include generating a first swept frequency signal with a first generator, and successively switching between different frequency signals with a second generator. Such switching creates undesired phase discontinuities in the output swept frequency signal. The first swept frequency signal is combined with the successively switched different frequency signals to produce the relatively wideband swept frequency signal, and the second generator is calibrated to reduce the undesired phase discontinuities during switching based upon the output swept frequency signal.

Abstract: Systems and methods for determining coefficients a filter are disclosed. The filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distnbuted values for the sine and cosine functions in the range of 0 to ?. The inverse of the input value is computed using an inverse memory lockup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal. Thus, the coefficient is computable in real-time without the use of previously computed and stored coefficients.

Abstract: A first value of a sinusoidal-shaped electronic signal is computed based on a Lagrange interpolation using an update phase-angle associated with the electronic signal, a first set of equally-spaced data-values that generally describe the sinusoidal function and a second set of pre-calculated-values, which are based on spacing differences between the data-values. The first value can then be used to update the electronic signal or used to update another signal, such as a communication signal.

Abstract: An apparatus and method are disclosed for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials. Unlike prior art methods that individually round each polynomial coefficient of a function, the method of the present invention use a “ripple carry” rounding method to round each coefficient using information from the previously rounded coefficient. The “ripple carry” method generates rounded coefficients that significantly improve the total rounding error for the function.

Abstract: A hardware context vector codec/generator which can be used in the block coder of a discrete wavelet transform (DWT) codec. The context vector codec/generator consists mostly of three columns of context vector registers where the context vectors move in parallel from column to column while the bits in the context vectors are modified by digital logic gates placed before each column. The digital logic gates are controlled by the results of the block coder scanning quantized wavelet coefficients. The preferred embodiment is used in a JPEG2000 codec.

Abstract: A sigma delta interpolator for use in a fractional N synthesizer having a multi-modulus divider for controlling the output frequency of the synthesizer. The sigma delta interpolator includes an accumulator operative for receiving an input signal representing the desired frequency output of the fractional N synthesizer and for generating a digital output signal having M bits, which include N most significant bits and n least significant bits. The N most significant bits output by the accumulator are coupled to the multi-modulus divider and are operative for controlling the operation of the multi-modulus divider. The sigma delta interpolator further includes a delay circuit coupled to the accumulator, which functions to receive the n least significant bits and implement a delay function defined by equation: 1?(1?Z?1)N, where N corresponds to the order of the sigma delta interpolator.

Abstract: A method and an apparatus are disclosed for digital synthesis of signals having a frequency which is a rational factor n/m times an existing reference or clock frequency, wherein n and m may be large relatively prime integers. The invention provides for the use of a periodic sequence generator having up to N taps which are connected to a cascade of digital commutating multiplexers. The periodic sequence generator and the commutating multiplexers have periodicities fi that are determined by programmable address counters and the choice of N. The resultant signal at the output of the last commutator stage has a spectral frequency component at a desired frequency which is an algebraic sum of the frequencies fi (each taken with either positive or negative signs). One aspect of the invention provides for the use of weighted linear combination of commutator output lines, thereby further aiding in improving its spectral purity performance.

Abstract: In an inverse calculation, x is road out of a storage means, [x/2] is calculated and stored therein as b, a lent significant bit of b is stored as a, [(ax+b)/2] is calculated and stored as updated b, and low-order two bits of x are stored as y. Then, for i=1, 2, . . . , n?1, by is calculated, a is updated with ?by, [(b+ax)/(2^(2i))] is calculated and stored as updated b, and y+a2^(2i) is calculated and stored as updated y, where y is road out as the result of inverse calculation.

Abstract: A system, method and computer program product are provided for branching during programmable processing in a computer graphics pipeline. Initially, data is received. Programmable operations are then performed on the data in order to generate output. Such operations are programmable by a user utilizing instructions from a predetermined instruction set. When performing the programmable operations in the foregoing manner, programmable branching may take place between the programmable operations. Subsequently, the output is stored in memory. Also included is a system, method and computer program product for directly executing a function in the computer graphics pipeline. Initially, input data is received in the computer graphics pipeline. A mathematical function is directly performed on the input data in order to generate output data. It should be noted that the mathematical function is directly performed in the computer graphics pipeline without a texture look-up or aid from a central processing unit.

Abstract: The circuit of this invention performs clock division with dynamic divide-by value change capability. This circuit provides low area and low latency. The clock divider is conventional except for the logic that handles the dynamic divide-by value change. When the divide-by value is changed by the user, such as through software, the changed value is recorded in a register but does not affect the divider immediately. Once the changed divide-by value is recorded, the divider clock output is allowed to continue till it reaches ‘low’ and is shut off. Then the recorded value is sent to the divider. The divider then generates a clock signal corresponding to the new divide-by value. The clock gating is then disabled and the clock propagates. This implements glitch free clock switching. This implementation of clock selection or switching provides low area and low latency for switching.

Abstract: A method, system and computer program product for digitally generating a function, including a phase accumulator configured to receive a phase value and integrate the phase value to generate an accumulation result; an address generator configured to generate consecutive addresses based on the accumulation result; a storage device configured to initiative initial digital function values based on the consecutive addresses; a coefficient calculator configured to generate coefficients for a polynomial interpolation based on the initial digital function values; and an interpolator configured to generate a final digital function value corresponding to the phase value based on the accumulation result and the coeffcients.

Abstract: A power of a square matrix is determined in a time approximately proportional to the upper integer of the base—2 logarithm of the order of the matrix. A preferred embodiment uses two types of look-up tables and two multipliers for a matrix of 15×15, and is applied to a pseudorandom noise (PN) sequence phase correlation or state jumping circuit. An exact state of a PN code can be determined or calculated from applying an appropriate offset value into a control circuit. The control circuit can produce a PN sequence state from the offset value and typically does so within one system clock period regardless of the amount of the offset. Once the exact state is determined, it is loaded into a state generator or linear sequence shift register (LSSR) for generating a subsequent stream of bits or symbols of the PN code. The PN generator system may include state computing logic, a maximum length PN generator, a zero insertion circuit and a zero insertion skipping circuit.

Abstract: A direct digital synthesizer that suppresses phase jumps which would invite the generation of spurious signals. Out of phase data supplied by a phase accumulator, the value of any rounding error arising at the time of phase computation is entered into a variable delay circuit, and the phase of a signal obtained by phase-amplitude conversion is controlled to compensate for any phase jump in the output signal.

Abstract: A low speed clock divider that behaves like a high speed clock divider is provided. The clock divider includes a software-configurable low-speed component for waveform generation and a high-speed component linked to the low-speed component, the high-speed component providing an output signal by serializing a waveform received from the low-speed component.

Abstract: An apparatus (20) and method (22) for transparently accessing and interpolating data are provided. Consecutive data values (24) of a function are generated and indexed. Even-indexed data values (24) are stored in an even-indexed table (30) and odd-indexed data values (24) are stored in an odd-indexed table (32). Adjacent-indexed data values (24) are acquired substantially simultaneously from even- and odd-indexed tables (30,32) with the first-indexed value (Gn) extracted from the even-indexed table (30) when an integral portion (A[N]) of a memory address (A[N+F]) is even and from the odd-indexed table (32) when the integral portion (A[N]) is odd. A fractional portion (A[F]) of the memory address (A[N+F]) is converted into an incremental value (&Dgr;).

Abstract: A DDS (Direct Digital Synthesis) frequency synthesizer can be adapted to operate as a pseudo random noise generator by including a swept address ingredient that distributes (but does not eliminate) repetitive frequency components that would otherwise appear in the output of the basic DDS technique, (which fetches fixed but randomized values from a waveform memory). These residual distributed long period frequency components in the output of a swept DDS pseudo random noise generator are suppressed by making the sweep itself irregular. The noise generator includes an Address Increment Register (AIR) whose content: (1) alters the address used to fetch fixed randomized values from the waveform memory; and (2) is incremented to produce the swept address (different sequences of addresses). At some point the AIR value has been incremented as high as it will go (i.e., the end of the sweep has been reached), and the process must start over.

Abstract: An on-board self test system for an electrical power monitoring device includes a test signal circuit in an electronic circuit of the monitoring device, and responsive to a programmable test input signal for producing an analog signal simulating an electrical power waveform, and a programmable memory in an electronic circuit of the monitoring device and operatively coupled with the test signal circuit for storing and reproducing upon command, one or more of the programmable test input signals.

Abstract: A polynomial coefficient generator for performing a polynomial multiplication. All the sub-coefficients necessary for performing the polynomial multiplication can be sequentially input into the generator. After n clock cycles, all n polynomial coefficients are computed and stored inside the generator ready for use.

Abstract: A computerized apparatus and associated method and program code on a storage medium, for producing a flattening map of a digitized image. This image may be initially synthetically produced as discrete data or as quasi-discrete image data of a real object—and the original image data may be stored as two-, three-, or four-dimensional dynamic coordinate data. Once produced, the flattening map can be conformally mapped onto the computer generated surface (whether 2-D, 3-D, or any of the dynamically-varying family of surfaces) for display on a computer-assisted display apparatus in communication with a processor. The apparatus and associated method and program code include constructing a first set of data comprising a plurality of discrete surface-elements to represent at least a portion of a surface of the digitized image, and performing a flattening function on the first set of data to produce the flattening map.

Abstract: The invention relates, in general, to circuits and techniques for generating numbers and, in particular, to digital semiconductor circuit for generating large numbers. For generating such large numbers a large number generator circuit is used, comprising first means having an output for providing a first operand to a first input of a processing unit, second means having an output for providing a second operand to a second input of said processing unit, an output of said processing unit being operatively connected to an input of an arithmetic unit for generating a large number, wherein said second operand is generated by said second means using a parameter having far fewer number of p bits than the number of bits of the first operand.

Abstract: A frequency synthesizer that improves a unique DDS characteristic, while maintaining a circuit scale (ROM size) of a direct digital synthesizer (DDS). A first digital signal generator generates a quantized frequency signal, and a second digital signal generator generates a frequency signal having a fine frequency resolution and many spurious signals as compared with the first digital signal generator. A filter performs band rejection on an output of the second digital signal generator, and a mixer mixes an output of the first digital signal generator with an output of the filter.