Function Generation Patents (Class 708/270)
  • Patent number: 6665693
    Abstract: A digital signal system (10, 100) for determining an approximate reciprocal of a value of x. The system includes an input (12) for receiving a signal, and circuitry (18) for measuring an attribute of the signal. The measured attribute relates at least in part to the value of x. The system further includes circuitry (104) for identifying a bounded region within which x falls. The bounded region is one of a plurality of bounded regions, and each bounded region has a corresponding slope value and first and second endpoints. The system further includes circuitry (106, 108, 110) for determining the approximate reciprocal by adjusting a reciprocal value at one of the first and second endpoints by a measure equal to a distance of the value of x from the one of the first and second endpoints times the slope value corresponding to the bounded region within which x is identified as falling.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: December 16, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Rustin W. Allred
  • Patent number: 6611854
    Abstract: The present invention employs a mapping function in order to apply a known distortion to an input signal. The mapping function of the present invention is defined by: y=A1*sin(arcsin(x))+A2*cos(2*arcsin(x))+A3*sin(3*arcsin(x))+A4*cos(4*arcsin(x))+ . . . An*sin(n*arcsin(x))+A(n+1)*cos((n+1)*arcsin(x)), where x is the input signal, y is the output signal, A is the amplitude of the harmonic level for a given harmonic, 1 being the fundamental, n is an odd number and (n+1) represents the highest harmonic of interest.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: August 26, 2003
    Inventor: David Amels
  • Publication number: 20030154224
    Abstract: Systems and methods for determining coefficients of an FIR filter are disclosed. The FIR filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of FIR filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distributed values for the sine and cosine functions in the range of 0 to &pgr;. The inverse of the input value is computed using an inverse memory lookup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal.
    Type: Application
    Filed: October 30, 2001
    Publication date: August 14, 2003
    Inventors: Zhongnong Jiang, Rustin W. Allred
  • Patent number: 6587863
    Abstract: Direct digital synthesis (DDS) methods and structures are provided that increase DDS output frequencies fout without requiring a corresponding increase in the rate fclk at which DDS structures must operate. An exemplary method generates a periodic stream of digital words at a clock frequency fclk wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step &phgr;s.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: July 1, 2003
    Assignee: Analog Devices, Inc.
    Inventors: Ken Gentile, John Kornblum
  • Patent number: 6581079
    Abstract: The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.
    Type: Grant
    Filed: November 12, 2001
    Date of Patent: June 17, 2003
    Assignee: STMicroelectronics, Inc.
    Inventor: Leonard Rarick
  • Patent number: 6578057
    Abstract: On the basis of a high degree of theory, prime numbers are derived through effective processing and steps so as to achieve a remarkable reduction in the processing time taken for the derivation. With respect to an arbitrary prime number rank entered, (1) numerical values are added in sequence to a prime number of the anterior rank to calculate prime number candidates of the next rank; (2) the thus calculated prime number candidate is divided by known prime numbers to verify whether it is a prime number or not; and (3) processing for reducing the verification time is iterated when the thus calculated prime number candidate is larger than a certain value, to thereby derive prime numbers until the entered rank is reached.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: June 10, 2003
    Inventor: Hironobu Hori
  • Patent number: 6549924
    Abstract: An input number is applied to a look-up table that supplies three coefficients based upon certain bits of the input that define a series of bins. The first coefficient is fed directly to an adder that produces the output. The second coefficient is multiplied by a number corresponding to how far the input is from the edge of a bin. This number is then input to the adder that produces the output. The third coefficient is multiplied by a number that is the result of a curve-fit function of a number corresponding to how far the input is from the middle of a bin. This result is then input to the adder that produces the output. These three addends are aligned and summed to produce an output that corresponds within a certain precision of a chosen mathematical function of the input such as the mathematical inverse (1/x) or the mathematical inverse of the square root of the input.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: April 15, 2003
    Assignee: Hewlett-Packard Company
    Inventor: Robert H Miller, Jr.
  • Publication number: 20030055853
    Abstract: An apparatus (20) and method (22) for transparently accessing and interpolating data are provided. Consecutive data values (24) of a function are generated and indexed. Even-indexed data values (24) are stored in an even-indexed table (30) and odd-indexed data values (24) are stored in an odd-indexed table (32). Adjacent-indexed data values (24) are acquired substantially simultaneously from even- and odd-indexed tables (30,32) with the first-indexed value (Gn) extracted from the even-indexed table (30) when an integral portion (A[N]) of a memory address (A[N+F]) is even and from the odd-indexed table (32) when the integral portion (A[N]) is odd. A fractional portion (A[F]) of the memory address (A[N+F]) is converted into an incremental value (&Dgr;).
    Type: Application
    Filed: June 2, 2001
    Publication date: March 20, 2003
    Inventor: Thomas L. Fowler
  • Publication number: 20030037080
    Abstract: A technique for approximating output values of a function based on LaGrange polynomials is provided. Factorization of a LaGrange polynomial results in a simplified representation of the LaGrange polynomial. With this simplified representation, an output value of a function may be determined based on an input value comprising an input mantissa and an input exponent. Based on a first portion of the input mantissa, a point value and at least one slope value are provided. Each of the at least one slope value is based on a LaGrange polynomial approximation of the function. Thereafter, the point value and the at least one slope value are combined with a second portion of the input mantissa to provide an output mantissa. Based on this technique, a single set of relatively simple hardware elements may be used to implement a variety of functions with high precision.
    Type: Application
    Filed: July 30, 2001
    Publication date: February 20, 2003
    Inventor: Daniel B. Clifton
  • Publication number: 20030037081
    Abstract: A method, system and computer program product for digitally generating a function, including a phase accumulator configured to receive a phase value and integrate the phase value to generate an accumulation result; an address generator configured to generate consecutive addresses based on the accumulation result; a storage device configured to initiative initial digital function values based on the consecutive addresses; a coefficient calculator configured to generate coefficients for a polynomial interpolation based on the initial digital function values; and an interpolator configured to generate a final digital function value corresponding to the phase value based on the accumulation result and the coeffcients.
    Type: Application
    Filed: November 8, 2001
    Publication date: February 20, 2003
    Inventor: Julio Alberto Vergel
  • Publication number: 20020198912
    Abstract: A fractional sequence generator for use in a F-N synthesizer includes a multi-accumulator structure providing a plurality of carry-out signals for application to an adder through a recombination network to generate an output fractional sequence, S, having an average value given by avg(S)=C/D, where C/D is the desired fractional part of the divisor, and denominator, D, is programmable. Illustratively, contents of a n-bit accumulator in each accumulator is augmented by a function of the programmable denominator value upon a carry-out of the associated n-bit adder in that accumulator.
    Type: Application
    Filed: June 12, 2001
    Publication date: December 26, 2002
    Inventors: Scott Robert Humphreys, Alex Wayne Hietala
  • Patent number: 6424185
    Abstract: An improved synchronization circuit has a numerically controlled oscillator (NCO) having an accumulator, a number line, and feedback line fed back from the accumulator output. The accumulator repeatedly adds the number represented on the number line and the number represented on the feedback line and feedbacks the result to the accumulator. The result rolls over to zero as would an odometer when it reaches a maximum value. When the number represented on number input is properly selected by, for example, a microprocessor, a data stream representing the most significant bit of the result has jitter. The synchronization circuit also has a phase-locked loop (PLL) configured to receive the data stream of the most significant bit. The frequency of the most significant bit stream and the frequency of the jitter on that bit stream are controlled by the number at the number input. The number is chosen to maximize the jitter frequency and thus maximize jitter attenuation through the PLL.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: July 23, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Christopher K. Wolf
  • Publication number: 20020078111
    Abstract: In order to generate a multiple of a unit U, N times U, by a digital circuit is provided, where U is a rational number and N is a natural number, the method comprises the following steps (1) to (5). (1) Where A, B and C are natural numbers, A>1, B>C and U=A+C/B, the values A, B and C are stored. (2) A multiple of A, N times A and a multiple of C, N times C are generated. (3) The multiple of C is compared with the denominator B. (4) The multiple of A is modified according to the result of the comparing step (3). (5) The modified multiple of A is output as the multiple of U.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 20, 2002
    Inventor: Kozo Mugishima
  • Publication number: 20020065861
    Abstract: Disclosed is a table lookup based phase calculator for a high-speed communication using normalization of input operands which can reduce the size of a phase table by converting respective input data into a sign and a magnitude, respectively, normalizing the magnitude of converted signals within a predetermined range, and reading the phase table using only upper L bits of the normalized input data.
    Type: Application
    Filed: January 24, 2001
    Publication date: May 30, 2002
    Inventors: Ki Seon Kim, Seung Geun Kim
  • Patent number: 6393449
    Abstract: An arbitrary function generator produces one or more waveforms for arbitrary applications wherein a general-purpose waveform production capability is customized to meet the demands of specific applications. The arbitrary waveform generator supports arbitrary scaling of waveforms in amplitude and in time. The arbitrary function generator is a standalone system that may be integrated into a MRI control system. In a preferred embodiment of the present invention, a software system comprising a delivery component, a configuration component, a scaling component, and a triggering component provide the features and functions of the present invention. The various software components communicate in accordance with a shared memory database in which data structures comprising waveform descriptions and tuning parameters are made available to the various software components.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: May 21, 2002
    Assignee: The Ohio State University Research Foundation
    Inventors: Samuel S. Bair, Jogikal M. Jagadeesh, Amir M. Abduljalil
  • Patent number: 6385632
    Abstract: A system and method for evaluating one or more functions using a succession of CORDIC stages/iterations followed by a residual rotation. The succession of CORDIC stages are preferably partitioned into (a) a Z path which operates on an input angle and generates an output angle, and (b) an X/Y path which operates on an input point and generates an output point. The residual rotation rotates the output point by the output angle to generate a resultant point using a small angle approximation for sine and an accurate evaluation for sine of the output angle. The number of CORDIC stages in the succession is chosen so that the error in the coordinates of the resultant point induced by the approximation of sine is smaller than a desired amount. In particular, the number of CORDIC stages in the succession is chosen to be greater than or equal to (N+1)/3 in order to guarantee N bits of precision in coordinates of the resultant point. The Z path has a propagation time which is smaller than the X/Y path.
    Type: Grant
    Filed: June 18, 1999
    Date of Patent: May 7, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gwangwoo Choe, James R. MacDonald
  • Patent number: 6363405
    Abstract: A method optimizes function evaluations performed by of a VLIW processor through enhanced parallelism by evaluating the function by table approximation using decomposition into a Taylor series.
    Type: Grant
    Filed: December 24, 1998
    Date of Patent: March 26, 2002
    Assignee: Elbrus International Limited
    Inventor: Vadim E. Loginov
  • Publication number: 20010051966
    Abstract: The present invention provides apparatus, methods, and computer program products for providing coefficients of a function representative of a signal. In one embodiment, the apparatus, methods, and computer program products of the present invention, taking advantage of the independence of samples, provide complete sets of coefficients of the function as each sample is received and corrects the updated coefficients for accuracy by applying a rotating reference system. As such, the apparatus, methods, and computer program products of the present invention are capable of providing accurate coefficients with decreased latency. In another, embodiment, the apparatus, methods, and computer program products of the present invention use learning models to derive complete sets of coefficients of functions as each sample is received.
    Type: Application
    Filed: February 26, 2001
    Publication date: December 13, 2001
    Inventors: Walter E. Pelton, Adrian Stoica
  • Patent number: 6330578
    Abstract: A method and apparatus for digitally representing a waveform segment defined by discrete ordered pairs of abscissae and ordinates, the ordered pairs being divided into an odd set and an even set. The method includes the steps of: for each even abscissa, generating a difference code representing a difference between an even ordinate paired with the even abscissa and the even abscissa, whereby the even ordinate paired with the even abscissa is represented as the sum of the even abscissa and the corresponding difference code; and for each odd abscissa, generating a differential code representing a differential between an odd ordinate paired with the odd abscissa and an even ordinate corresponding to the odd abscissa, whereby the odd ordinate paired with the odd abscissa is represented as the sum of the corresponding even ordinate and the corresponding differential code.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: December 11, 2001
    Assignee: Nortel Networks Limited
    Inventors: Cristian Emanuel Savin, Bradley John Morris
  • Patent number: 6320431
    Abstract: An apparatus according to a preferred embodiment of the present invention includes two memories each storing different octants of a sine (or cosine) waveform. The sine and cosine waveforms may be concurrently generated by alternately accessing each memory in succession. It is unnecessary to access one memory concurrently, so that both waveforms may be concurrently generated without requiring either two accesses to the same memory or a doubled memory size.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: November 20, 2001
    Assignee: National Semiconductor Corporation
    Inventors: David Potson, Mark F. Rives
  • Patent number: 6317764
    Abstract: The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: November 13, 2001
    Assignee: STMicroelectronics, Inc.
    Inventor: Leonard D. Rarick
  • Publication number: 20010007990
    Abstract: A polynomial coefficient generator for performing a polynomial multiplication. All the sub-coefficients necessary for performing the polynomial multiplication can be sequentially input into the generator. After n clock cycles, all n polynomial coefficients are computed and stored inside the generator ready for use.
    Type: Application
    Filed: December 19, 2000
    Publication date: July 12, 2001
    Inventor: Shih-Yung Chen
  • Patent number: 6240433
    Abstract: An improved method of estimating the square root, reciprocal square root, and reciprocal of an input value in a computer system. The input value, after being normalized, is used to select a pair of constants from a table. The constants are based on a linear approximation of the function for each interval of the input value, offset to reduce a maximum error value for a given interval. The estimated function is calculated by adding or subtracting the product of a part of the normalized input value and the first constant from the second constant. In one implementation, the input value is normalized within the range 1≦×<2, and one lookup table is used, having an interval size of {fraction (1/32)}. In a further preferred embodiment, only a lower order part of the mantissa is used in the multiply-add operation, to reduce the number of bits required (the high order part of the mantissa is used to select the constants from the table).
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: May 29, 2001
    Assignee: International Business Machines Corporation
    Inventors: Martin Stanley Schmookler, Donald Norman Senzig
  • Patent number: 6223192
    Abstract: A method for generating entries for a bipartite look-up table having base and difference table portions. In one embodiment, these entries are usable to form output values for a mathematical function, f(x), in response to receiving corresponding input values within a predetermined input range. The method first comprises partitioning the input range into I intervals, J subintervals/interval, and K sub-subintervals/subinterval. For a given interval M, the method includes generating K difference table entries and J base table entries. Each of the K difference table entries corresponds to a particular group of sub-subintervals within interval M, each of which has the same relative position within their respective subintervals. Each difference table entry is computed by averaging difference values for the sub-subintervals included in a corresponding group N.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: April 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stuart F. Oberman, Norbert Juffa
  • Patent number: 6185594
    Abstract: A versatile signal generator for generating digitally modulated test signals computed in real-time is provided. Each of the blocks ol the versatile signal generator, including the MUX, coder, map, filter, re-sampler, and modulator, are implemented in a sufficiently flexible manner so as to allow ready configuration to produce any of a variety of digitally modulated signals as well as high quality analog modulated signals. Each of the blocks may be implemented using ASICs and RAM that allow to obtain high symbol rates while being capable of being reconfigured for different test signals as needed. The versatile signal generator has a real time input for receiving input data to modulate the test signal in real time.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: February 6, 2001
    Assignee: Agilent Technologies Inc.
    Inventors: Howard E Hilton, John H. Guilford
  • Patent number: 6154101
    Abstract: A novel and improved method and apparatus for a fast-slewing pseudorandom noise sequence generator is described. One or more loadable PN generators are controlled by a DSP or microprocessor in conjunction with a free-running counter which maintains a reference offset count. The PN generator will typically be part of a finger or searcher. The DSP or microprocessor may assist in other finger or searcher functions as well as the slew function, and can control one or more fingers and/or searchers. Each PN generator is comprised of a loadable linear feedback shift register (LFSR) or its equivalent, a loadable counter for maintaining an index of the state of that particular PN generator, and a slew control device capable of receiving a slew command and controlling the LFSR and index counter to enact an advance or a retard of a certain offset distance.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: November 28, 2000
    Assignee: Qualcomm Incorporated
    Inventors: Qiuzhen Zou, Gilbert C. Sih, Avneesh Agrawal
  • Patent number: 6038578
    Abstract: An initial waveform is defined as a set of amplitude values corresponding to a set of base positions. A series of waveform definitions is generated by incrementing or decrementing at least one amplitude value in the set of amplitude values according to a predetermined counting sequence and in dependence upon the current amplitude values. Waveform definitions are generated until an end condition is reached, such as a predetermined number of waveform definitions having been generated or a predetermined waveform definition having been generated. Waveform definitions can be stored in memory. A single waveform definition or the series of waveform definitions can be stored in memory. A single waveform or the series of waveforms can be plotted or displayed.
    Type: Grant
    Filed: November 21, 1990
    Date of Patent: March 14, 2000
    Inventor: Harold T. Fogg