Abstract: A filtering method approximates a target Finite Impulse Response (FIR) (or transversal) filter and reduces computational requirements by eliminating high pass filtering required by known multi-rate filters. An input signal is copied into two identical signals and processed in parallel by a full-rate path, and by a reduced-rate path. Parallel filters are computed and applied in each path, the reduced-rate signal is up-sampled, and the two signals summed. The high pass filter required by known multi-rate filters is eliminated and the low pass filter in the prior art is implicit in a down sampling. Linear phase FIR filters are used for down and up sampling, resulting in constant group delay. Added benefits include the option of zero added latency through the filtering and the constant group delay added to the target FIR. The user may choose criteria such as minimum resolution in each band.

Abstract: An apparatus for generating random data includes a raw random sequence source adapted to generate a raw random sequence and a digital post processor adapted to process the raw random sequence to generate the random data, wherein the digital post-processor includes a synchronous finite state machine having at least one input adapted to repeatedly receive a current value of the raw random sequence and at least one output to provide a current output value depending on previous values of the raw random sequence.

Abstract: A method for deformable registration of 2 digital images includes providing a pair of digital images, including a fixed image and a moving image, extracting a set of edge images from each image of the pair of images, each edge set being extracted at a different resolution, selecting a pair of edge images with a lowest resolution, determining a mapping from edge points of the fixed image to edge points of moving image using a geodesic thin plate spline interpolation, applying the mapping to a next higher resolution edge point image of the moving image, selecting a pair of edge images at a next higher resolution, where a moving edge image is the moving edge image to which the mapping has been applied, repeating the steps at a next higher resolution for all edge images in the set of edge images, and applying the mapping to an entire moving image.

Abstract: A direct digital radio having a high speed RF front end in communication with an antenna, and a radio subsystem that can be configured to form a multi-channel, full duplex transceiver system. The high speed RF front end provides a digital signal to the radio subsystem. Each transceiver includes a waveform processing subsystem that makes use of a linear, phase-B cubic spline interpolating finite impulse response (IFIR) filter for filtering the received RF signal substantially entirely in the digital domain. The linear phase-B, cubic spline IFIR filter requires significantly fewer hardware components than traditional FIR filters and is ideally suited for implementation using Very Large Scale Integration (VLSI) technology.

Abstract: An interpolator for a system, such as a motion control system, where a stream of values of at least a first command signal is communicated across a communications medium according to a predefined update rate. The integrator is configured to calculate at a higher rate relative to the update rate to generate at least one interpolated prediction of the first command signal.

Abstract: A modulator can be configured to sense a change in current flow in a circuit and to generate an oversampled, noise-shaped signal. A first decimation filter is coupled to the modulator and is configured to generate instantaneous current data at a first data rate. The instantaneous current data can be input into a multiplier circuit. The output of the multiplier circuit (the instantaneous current data squared) can be input to a second decimation filter. The second decimation filter can be configured to generate a sum of the squared current data at a second data rate. The sum of the squared current data can be used by an application (e.g., battery power management) to compute power measurements or for other purposes.

Abstract: A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.

Abstract: A method for processing a digital signal comprises receiving an output encoded signal (Sd,sc) obtained from an original digital signal (Si) having an initial spatial resolution and an initial bit rate, the output encoded signal having a bitrate lower than the initial bitrate, processing the output encoded signal to obtain a source signal (Sv) having the initial spatial resolution, and dividing (E303) samples of the source signal into at least two subsets of samples, the subsets corresponding respectively to different spatial grids that are arranged so that at least some samples of one subset are interleaved spatially with at least some samples of another said subset.

Abstract: A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M-1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

Abstract: A discrete time signal resampling circuit (200). A data sample processing module (260) removes selected samples from a sequential plurality of discrete time signal samples to implement fractional resampling where the data sample processing module stores fewer samples than the number of samples between samples to be removed. A coefficient generator (240) in the resampling circuit generates a sequence of finite impulse response filter coefficients, with each coefficient in the sequence being associated with a respective distinct portion of a plurality of discrete time signal samples. A coefficient multiplier (264) multiplies each of the sequential plurality of finite impulse response filter coefficients by its associated respective distinct portion of the plurality of discrete time signal samples. An adder (236) produces a resampled output sample that consists of a sum of elements of the product vector produced by the coefficient multiplier.

Abstract: A coefficient compensating unit 33 calculates based on a loop point and a cross-fade point of impulse response coefficient data renewed compensation impulse response coefficients specified for a cross-fade period defined between the cross-fade point and an end point of the impulse response coefficient data, and stores the calculated impulse response coefficients in a compensation coefficient memory 34, wherein the cross-fade point corresponds to a beginning point of the cross-fade period in which a cross-fading is performed to smoothly connect the end point with the loop point.

Abstract: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.

Abstract: A decimation filter has: a plurality of calculating devices each having a multiplier and an accumulator; a plurality of coefficient memories (a ring memory and shift registers) which store filter coefficients, and which correspond to the calculating devices, respectively; and a selector which sequentially selectively outputs the outputs of the plurality of calculating devices in synchronization with a clock signal. When a decimation ratio is n, filter coefficients which are sequentially shifted by an n number of filter coefficients are read out from the plurality of coefficient memories, and multiplied with a signal in the multipliers of the calculating devices, and results of the multiplications are accumulated in the accumulators to be output.

Abstract: The present invention relates to a rate change filter having multiple branches. The multi-branch rate change filter of the present invention achieves higher effective output rates by processing the input sample stream in two or more parallel filter branches with offset states.

Abstract: A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and maintains gains (Ki, Kp) of two branches of the control apparatus at a fixed value, which enables searching of a desired value by the DPLL to determine a neighborhood of the desired value, and reduces the gains when the number of samples reaches a predetermined number. Processing units in the DPLL generate and process first and second input signals based on an input clock, an output clock, and a system clock. The second input signal is processed using two branches. Signals resulting from the two branches are re-aligned according to a changed status of the first processed input signal such that the signals resulting from the two branches are sampled in the same input clock interval.

Abstract: A digital signal processing system comprising: an input terminal to receive an input signal that includes a distorted component and an undistorted component, the input signal having a sampling rate of R; and an adaptive self-linearization module coupled to the input terminal, to perform self-linearization based at least in part on the input signal to obtain an output signal that is substantially undistorted, wherein: the adaptive self-linearization module is to generate a replica distortion signal that is substantially similar to the distorted component, the generation being based at least in part on a target component having a sampling rate of R/L, L being an integer greater than 1; the adaptive self-linearization module includes a first digital signal processor (DSP) that is adapted to obtain a filter transfer function that approximates a system distortion transfer function, and a second DSP that is configured using configuration parameters of the first DSP.

Abstract: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.

Abstract: An OFDM (Orthogonal Frequency Division Multiplexing) demodulator includes: an FFT (Fast Fourier Transform) circuit for performing a fast Fourier transform on an OFDM signal; a circuit for extracting an SP (Scattered Pilot) signal from the fast Fourier transformed signal; a circuit for adding a positive or negative sign to the extracted SP signal; a memory for temporarily storing the signed SP signal and an information transmission signal; a carrier interpolation circuit for performing time axis interpolation and frequency axis interpolation on the signed SP signal by a plurality of methods; a complex division circuit for performing a complex division of the information transmission signal by interpolated data; and a memory interface for detecting a timing a prescribed number of signed SP signals have been obtained and an output timing of the interpolated data according to the interpolation method.

Abstract: A signal processing apparatus includes a decoding unit, an analyzing unit, a synthesizing unit, and a selecting unit. The decoding unit decodes an input encoded audio signal and outputs a playback audio signal. When loss of the encoded audio signal occurs, the analyzing unit analyzes the playback audio signal output before the loss occurs and generates a linear predictive residual signal. The synthesizing unit synthesizes a synthesized audio signal on the basis of the linear predictive residual signal. The selecting unit selects one of the synthesized audio signal and the playback audio signal and outputs the selected audio signal as a continuous output audio signal.

Abstract: The present invention relates to an interpolation FIR (finite impulse response) filter having multiple data rates in a mobile communication system, and a method of filtering data using the same. In the method of filtering data using the interpolation FIR filter, a first filter uses an FIR low pass filter that restricts a band to satisfy a bandwidth corresponding to a data spectrum mask required in the mobile communication system. The other filters use interpolation FIR halfband filters that are implemented by a small number of taps. Accordingly, the interpolation FIR filter having multiple data rates can be easily implemented, and can be easily applied to the mobile communication system that transmits and receives data having various data rates.

Abstract: A technique for interpolating a series of samples includes constructing a mathematical model of the series that describes its large signal behavior. The model is subtracted from the original series to yield a residue. A discrete Fourier transform (DFT) is taken of the residue, and the DFT is zero-padded. An inverse DFT of the padded result yields an interpolated residue, which is then added back to the mathematical model to construct an interpolated version of the series of samples. Using this technique, accurate interpolation can generally be attained even when the series of samples is not coherently sampled.

Abstract: A method of signal processing comprises receiving an unknown input signal that includes a distorted component and an undistorted component, the unknown input signal having a sampling rate of R; and performing self-linearization based at least in part on the unknown signal to obtain an output signal that is substantially undistorted, including by generating a replica distortion signal that is substantially similar to the distorted component, the generation being based at least in part on a target component having a sampling rate of R/L, L being an integer greater than 1.

Abstract: A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.

Abstract: A digital signal processing apparatus including: an arithmetic circuit that performs first digital signal processing on an input signal SA sampled at a first sampling frequency f1 and second digital signal processing on a result of the first digital signal processing; a timing control circuit that controls and causes the arithmetic circuit to perform the first and second digital signal processing; and a control circuit that monitors in real-time at least one of an amount of data subjected to the second digital signal processing and an amount of data to be transmitted by the input signal SA, and which controls the timing control circuit when the monitored data amount reaches a predetermined value.

Abstract: An architecture for use in wireless receiver applications, particularly for ADC conversion of received in-phase I and quadrature Q signals. A single ADC is shared to convert both signals, and the ADC input is alternately switched between the i and q signals. In an embodiment, the ADC is clocked at an increased sample rate, and the digital output signals are aligned to compensate for the phase difference resulting from the implementation of the single ADC.

Abstract: A computer program product and method for sales forecasting and adjusting a sales forecast for an enterprise in a configurable region having one or more clusters of stores. The method includes periodically receiving a sales forecast for an enterprise over a configurable period of time, periodically receiving actual sales information, sales anomalies and anticipated events within the at least one of the clusters of stores over a computer network, determining positive and negative deviations from the anticipated sales of the sales forecast based on the sales information, determining whether one or more trends are occurring or have occurred using a pre-defined mathematical expression based on the sales information, the positive and negative deviations, and the sales anomalies, adjusting the anticipated sales of the sales forecast based on the sales anomalies, the trends and the anticipated events, and outputting the adjusted sales forecast to a user.

Abstract: A time-division (TD) decimation filter bank includes two decimation filter units. The first decimation filter unit operates at a system clock and receives a first-stage input data string. Each data in the first-stage input data string has a first part data and second part data. During the odd clock periods, the first part data are filtered and decimated in frequency. During the even clock periods, the second part data are filtered and decimated in frequency. The second decimation filter unit operates at the system clock and 2N clock periods are set as an operation-period unit, N?2. The second decimation filter unit receives the outputs from the first decimation filter unit and receives several feedback data of the second decimation filter unit by TD, so that the received data are distributed into the 2N clock periods for filtering and decimation and outputting by TD.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell.

Abstract: Data rate conversion devices and methods are provided. A method for converting a first digital signal having a first sampling rate into a second digital signal having a sampling rate close to a predetermined second sampling rate comprises the following operations: when the ratio of the first sampling rate to the second sampling rate is a repeating infinite decimal, calculate at least two calibrating coefficient values and output the calibrating coefficient values according to a predetermined rule; conduct overflow operation on the output calibrating coefficient; and interpolate the first digital signal using the output calibrating coefficient and the result of the overflow operation to obtain the second digital signal such that during any period of a certain length along time axis, sampling times of the second digital signal equals to sampling times of the second sampling rate.

Abstract: Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Abstract: A digital pulse generator including a fractional delay filter is provided as having a plurality of step response functions that can be selected on a sample by sample basis by selection of filter coefficients. The step response functions are all identical but each have different group delay. Responsive to an input waveform having leading and trailing edges aligned with a system clock, the fractional delay filter can output the impulse responses as a pulse waveform having respective leading and trailing edges delayed by different respective fractions of a signal clock cycle from the respective leading and trailing edges of the input waveform. The pulse waveform as output can thus have desired pulse width and desired period of repetition with finer edge placement resolution of improved accuracy.

Abstract: A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit.

Abstract: A method for updating the processing capacity of an encoder or decoder to use a modulated transform having a size greater than a predetermined initial size is provided, particularly, where the encoders or decoders are for storing an initial prototype filter defined by an ordered set of initial size coefficients. A step is provided for constructing a prototype filter of a size greater than the initial size to implement the modulated transform of the greater size by inserting at least one coefficient between two consecutive coefficients of the initial prototype filter.

Abstract: A discrete sampling control signal, which influences the sampling time, from a sampling phase selection element is calibrated by definition of quantization intervals for a sampling time error signal. For this purpose, a received signal is shifted through a series of time shifts ?i in the signal path upstream of the sampling phase selection element. The sampling time errors ei associated with the respective time shifts ?i are measured. The quantization steps of the sampling control signal that are suitable for the sampling phase selection element are then determined from the relationship obtained between ?i and ei.

Abstract: The present invention is to provide a parallel filtering method, which is implemented to an interpolation filter and comprises the steps of separating coefficients of the interpolation filter into two sets comprising the positive and negative coefficients respectively for parallelly filtering a plurality of input data pixels packed into data words inputted to the interpolation filter concurrently to obtain a first result data word, and clipping and shifting the first result data word to obtain a final output data word containing packed half-pel pixels for parallelly and efficiently filtering data stream of video without increasing the complexity, cost, size and power consumption of circuitry of an electronic video apparatus.

Abstract: Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value ST or to apply IIR filtering for the vertical filtering where the determined scale factor satisfies a second condition relative to the threshold value ST. The first and second conditions are different and exclusive, such that only one type of filtering is applied. This hybrid filtering approach uses each type of filtering to avoid defects of the other.

Abstract: A filter for high speed digital signal processing. In one embodiment the filter includes a linear, phase-B, interpolating cubic spline filter having a pre-filter section and an interpolating post-filter section. The pre-filter section may be formed to implement any one of a 1-4-1 cubic spline function, a 2-5-2 cubic spline function or a 1-2-1 cubic spline function. The post-filter may be formed using a plurality of running average filters arranged in a cascade (i.e., serial) fashion. The filter can be constructed using significantly fewer independent component parts for a given level of pass band and stop band performance criteria, as compared with a conventional finite impulse response (FIR) filter. The filter is thus ideally suited for implementation with very large scale integration (VLSI) technology, and in a wide variety of electronic devices where high speed digital filtering is required.

Abstract: A sample rate converter circuit receives a first signal at a first sampling frequency and for outputs a second signal, representative of the first signal, having a second sampling frequency.

Abstract: A programmable integrated circuit device such as a programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in decimation mode. The device includes at least one user-configurable random access memory block, and that user-configurable random access memory is configured as coefficient memories and data sample memories. The memories are large enough to hold up to all of the coefficients of the filter and a plurality of data samples at one time. Because the data samples and coefficients need not be shifted through the filter at the programmable logic device clock rate, overclocking of the filter is not necessary. The filter can run at a clock rate which is the same as the input data rate, while taking advantage of the available random access memory to mimic a shift register.

Abstract: The n-tap filtering for generating interpolated pixels is converted into calculation of terms consisting of the difference and sum of the pixel values of adjoining pixels. When the difference is equal to or less than a predetermined value, the calculation related to the terms including the difference is omitted, thereby reducing the calculation amount in generating the interpolated pixels. In loop processing according to a flow chart of the pixel interpolating method, the reference pixels are accessed by one pixel per one loop processing for reading pixel values thereof, and the difference and sum of the pixel values are calculate using the adjoining pixel value already read one loop before, thereby interpolating the pixel values of consecutive pixels to be interpolated. Consequently, redundant reading of pixel values is avoided, with further beneficial effects on speedy generation of the interpolated pixels and reduction of the power consumption therein.

Abstract: A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.

Abstract: A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.

Abstract: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.

Abstract: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: Systems and methods for converting a data stream from a first sample rate to a second sample rate using a sample rate converter that employs selectable filters. In one embodiment, the filters are implemented by providing multiple sets of filter coefficients in a memory, selecting one of the sets of filter coefficients and performing coefficient interpolation to produce filter coefficients that are convolved with the input data stream to produce a re-sampled output data stream. The input signal can be an audio signal that is convolved with interpolated polyphase filter coefficients in the sample rate converter of a digital PWM audio amplifier. The set of filter coefficients can be selected by a value stored in a filter selection register that is modifiable by a DSP or by user input. The sets of filter coefficients can be stored in a single memory and interpolated according to a cubic spline interpolation algorithm.

Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.

Abstract: A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.

Abstract: An interpolation FIR filter uses a coefficient to generate an interpolation value of a first and second input value. The interpolation FIR filter has several arithmetic units, an adder, and a divider. The nth arithmetic unit outputs a partial product by selecting one of the first and second input values according to an nth bit of the coefficient, and multiplying the selected input value by 2(n?1). The adder outputs a sum all the partial products and the first input value. The divider divides the sum by 2m, wherein m is an amount of the arithmetic units.