Discrete Cosine Transform (i.e., Dct) Patents (Class 708/402)
  • Publication number: 20100082721
    Abstract: Inverse discrete cosine transform (type-III DCT), used in video/image and audio coding, is implemented in the form of FFT to lower computational complexity.
    Type: Application
    Filed: October 5, 2009
    Publication date: April 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventor: Mohamed F. Mansour
  • Patent number: 7634526
    Abstract: A method for selectable quantization for use in an encoder for compressing video and/or audio data includes processing that begins by receiving discrete cosine transform data of an encoded signal. The processing continues by generating a plurality of quantization matrixes of discrete cosine transform data based on a quantization table and a plurality of quantization scaling factors. The process continues by analyzing the plurality of quantization matrixes to identify one of the plurality of quantization matrixes having a best match of reduced data content and acceptable video quality. The processing continues by selecting the one of the plurality of quantized matrixes.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: December 15, 2009
    Assignee: VIXS Systems, Inc.
    Inventors: Indra Laksono, Jason Chan
  • Patent number: 7634525
    Abstract: A shared lossless Haar transform and an appended type-IV discrete cosine transform are combined to form a lossless discrete cosine type-IV transform having a fast pipeline architecture for providing fast reversible lossless DCT-IV transform data.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: December 15, 2009
    Assignee: The Aerospace Corporation
    Inventor: Hsieh S. Hou
  • Patent number: 7627623
    Abstract: Provided are an IMDCT co-processor and an audio decoder having the same.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: December 1, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Suk Ho Lee, Nak Woong Eum, Hee Bum Jung
  • Patent number: 7620675
    Abstract: Inverse discrete cosine transform (type-III DCT), used in video/image and audio coding, is implemented in the form of FFT to lower computational complexity.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: November 17, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Mohamed F. Mansour
  • Patent number: 7613761
    Abstract: A shared lossless Haar transform and an appended discrete cosine transform type-II are combined to form a discrete cosine type-II transform in a parallel pipelined architecture for providing lossless data transformation.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: November 3, 2009
    Assignee: The Aerospace Corporation
    Inventor: Hsieh S. Hou
  • Patent number: 7580843
    Abstract: A synthesis subband filter apparatus is provided. The apparatus is used for processing 18 sets of signals which each includes 32 subband sampling signals in accordance with a specification providing 512 window coefficients. The apparatus includes a processor for processing the 18 sets of signals in sequence. The processor further includes a converting module and a generating module. The converting module is used for converting the 32 subband sampling signals of the set of signals being processed into 32 converted vectors by use of 32-points discrete cosine transform (DCT), and writing the 32 converted vectors into 512 default vectors with a first-in, first-out queue. The generating module is used for generating 32 pulse code modulation (PCM) signals, relative to the set of signals being processed according to a set of synthesis formulae proposed in this invention.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: August 25, 2009
    Assignee: Quanta Computer, Inc.
    Inventors: Chih-Hsien Chang, Chih-Wei Hung, Hsien-Ming Tsai
  • Patent number: 7574468
    Abstract: A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations (IDCTs). In one embodiment, the distributed arithmetic MAC unit includes: (1) a first pipeline stage configured to perform dot products on received sequential input data and (2) a second pipeline stage coupled to the first pipeline stage and configured to compute additions and subtractions of the dot products to yield sequential output data.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: August 11, 2009
    Assignee: VeriSilicon Holdings (Cayman Islands) Co. Ltd.
    Inventor: Jitendra Rayala
  • Publication number: 20090198757
    Abstract: The present invention provides a method for avoiding rounding errors during rounding of values after performing an inverse discrete cosine transformation. In a first step a) coefficient values of a plurality of coefficients are summed up, wherein the coefficients belong to a block of coefficients. In a second step b), it is evaluated if the sum of the coefficient values is even numbered or odd numbered. In a third step c), then the coefficient block is transformed by means of the inverse discrete cosine transformation into a block of image pixels, wherein each image pixel comprises an image pixel value.
    Type: Application
    Filed: October 18, 2007
    Publication date: August 6, 2009
    Inventor: Thomas Sikora
  • Patent number: 7558815
    Abstract: The present invention provides a method, apparatus, and article of manufacture for controlling truncation error which is introduced when performing a transform equation as a result of lowering the precision of elements of the equation using shift right operations. This is achieved by associating a predetermined truncation amount with a plurality of operations of the transform equation and defining an ordered set of the operations to perform the transform which control the truncation error in the result if each operation introduced the predetermined truncation amount associated with it. Accordingly the transform is performed using the defined ordered set. For example the pre-determined truncation error could be an average truncation error.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: July 7, 2009
    Assignee: InfoPrint Solutions Company LLC
    Inventors: Joan LaVerne Mitchell, Arianne Therese Hinds
  • Patent number: 7555510
    Abstract: The present invention provides an input data control method and system for a data processing system. The system comprises at least one basic operation unit (BOU) and is used for transforming one input matrix X into data in a plurality of specified columns in an output matrix Y via an inverse discrete cosine transform procedure. The method generates and outputs a transform control signal together with the input matrix to at least one of the BOUs. A new transform control signal is generated according to the received transform control signal, and outputted together with the input matrix X, to other following BOUs. The step of generating the new transform control signals is repeated until each specific column of the output matrix Y is decoded by a corresponding BOU. A basic operation procedure is then performed, and the received input matrix is decoded to obtain the data in the specified columns corresponding to the transform control signal.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: June 30, 2009
    Assignee: MediaTek, Inc.
    Inventor: Chi-Cheng Ju
  • Publication number: 20090157785
    Abstract: A more efficient encoder/decoder is provided in which an N-point MDCT transform is mapped into smaller sized N/2-point DCT-IV, DST-IV and/or DCT-II transforms. The MDCT may be systematically decimated by factor of 2 by utilizing a uniformly scaled 5-point DCT-II core function as opposed to the DCT-IV or FFT cores used in many existing MDCT designs in audio codecs. Various transform factorizations of the 5-point transforms may be implemented to more efficiently implement a transform.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 18, 2009
    Applicant: QUALCOMM Incorporated
    Inventors: Yuriy Reznik, Ravi Kiran Chivukula
  • Publication number: 20090150469
    Abstract: The present invention provides a unified inverse discrete cosine transform (IDCT) microcode processor engine, which is able to process IDCT with different video standards and also achieves the processing speed requirement. The microcode processor engine comprises a read unit for reading input data; a shift left unit comprising: a first shift left block for left-shifting input data; and a second shift left block for left-shifting input data; an add unit for adding data output from the shift left unit; and a shift right unit for right-shifting data output from the add unit. The present invention also provides a system of inverse discrete cosine transform.
    Type: Application
    Filed: June 26, 2008
    Publication date: June 11, 2009
    Inventors: Zheng-Yu Zheng, Zheng-Wei JIANG, Franciscus SIJSTERMANS
  • Patent number: 7512539
    Abstract: An integer transform, which provides integer output values, carries out the TDAC function of a MDCT in the time domain before the forward transform. In overlapping windows, this results in a Givens rotation which may be represented by lifting matrices, wherein time-discrete sampled values of an audio signal may at first be summed up on a pair-wise basis to build a vector so as to be sequentially provided with a lifting matrix. After each multiplication of a vector by a lifting matrix, a rounding step is carried out such that, on the output-side, only integers will result. By transforming the windowed integer sampled value with an integer transform, a spectral representation with integer spectral values may be obtained. The inverse mapping with an inverse rotation matrix and corresponding inverse lifting matrices results in an exact reconstruction.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: March 31, 2009
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ralf Geiger, Thomas Sporer, Karlheinz Brandenburg, Jürgen Herre, Jürgen Koller
  • Publication number: 20080298699
    Abstract: A method and device that uses transform matrices to down-sample a DCT image directly in the DCT domain. The transform matrices have been selected to minimize an optimization problem which is a function of the visual quality of down-sampled images obtained using the matrices and the computational complexity associated with using the transform matrices. The transform matrices comprise a row transform matrix and a column transform matrix. A down-sampled image is produced by determining an intermediary matrix as the product of the DCT image and one of either the row transform matrix or the column transform matrix and then determining the down-sampled image as the product of the intermediary matrix and the transform matrix not already used to determine the intermediary matrix.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 4, 2008
    Inventors: Xiang Yu, En-hui Yang, Haiquan Wang
  • Patent number: 7451170
    Abstract: A data processing system transforms an input matrix with transform coefficients through an inverse discrete cosine transform procedure, and it consequentially obtains an output matrix. The input matrix comprises 2N×2N of discrete cosine transform coefficients, and the output matrix comprises 2N×2N of output data; both are sequentially indexed by the row and column index. The output matrix is obtained by summing up a plurality of partial output matrixes; each partial output matrix comprises a first partial sub-output matrix and at least one other partial sub-output matrix. The first partial sub-output matrix comprises a plurality of partial output data that has a predetermined symmetry characteristic. The partial output matrixes possess a number of symmetry relations. The first and other partial sub-output matrixes of each partial output matrix have one symmetry relation.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: November 11, 2008
    Assignee: MediaTek, Inc.
    Inventor: Chi-Cheng Ju
  • Patent number: 7437394
    Abstract: Discrete Cosine Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain for enabling recursive merges and splits in transform domain without data degradation. Input data in the time domain or spatial domain during either the split and merge radix-2 forward transform processing is firstly transform processed followed by combinational processing. In the split transform process, whole transformed data is split using combinational processing into first and second transformed data halves in the transform domain as a true split. In the merge transform process, first and second transform halves are merged using combinational processing into a merged transformed data whole in the transform domain. In either case, time or spatial domain input data can be transformed into the transform domain in the form of split halves or merged whole.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: October 14, 2008
    Assignee: The Aerospace Corporation
    Inventor: Hsieh S. Hou
  • Publication number: 20080215654
    Abstract: Reduced complexity inverse discrete cosine transform (IDCT) masks and a method for reducing the number of IDCT calculations in video decoding are provided. The method comprises: accepting an n×m matrix of DCT coefficients; performing (n?y) horizontal IDCT operations, where y is greater than 0; performing y scaling operations; and, generating an n×m block of pixel information. Some aspects of the method further comprise: performing (m?z) vertical IDCT operations, where z is in the range between 0 and m/2. In some aspects, performing (n?y) horizontal ICDT operations includes performing IDCT operations for the first (n?y) horizontal rows. Then, performing y scaling operations includes: selecting the DC component from the first position of each horizontal row; scaling the selected DC component; and, copying the scaled DC component into the remaining positions of each of horizontal row.
    Type: Application
    Filed: May 15, 2008
    Publication date: September 4, 2008
    Inventors: Shijun Sun, Shawmin Lei
  • Patent number: 7412470
    Abstract: The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: August 12, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Masuno, Tatsuro Juri
  • Patent number: 7395432
    Abstract: A watermark is embedded in spatial domain. However, the same effect as the watermark is embedded in frequency domain is obtained by inverse frequency transforming the watermark, and then embedding it. By doing that, robustness of the watermark is enhanced in comparison with conventional method for generating a watermark and adding it in spatial domain. Also, the watermark can be detected, even though an image is passed through stirmark, by enlarging the size of the watermark generated by inverse frequency transforming through re-sampling. In detecting the watermark, by high frequency filtering the watermarked image and getting all blocks of the watermarked image together, the effect of removing image component is obtained. Thereby, the detection speed of the watermark is improved, and the detection rate is increased as well.
    Type: Grant
    Filed: April 13, 2002
    Date of Patent: July 1, 2008
    Assignee: Markany, Inc.
    Inventors: Jung-Soo Lee, Jong-Uk Choi
  • Patent number: 7369989
    Abstract: A unified filter bank for use in encoding and decoding MPEG-1 audio data, wherein input audio data is encoded into coded audio data and the coded audio data is subsequently decoded into output audio data. The unified filter bank includes a plurality of filters, with each filter of the plurality of filters being a cosine modulation of a prototype filter. The unified filter bank is operational as an analysis filter bank during audio data encoding and as a synthesis filter bank during audio data decoding, wherein the unified filter bank is effective to substantially eliminate the effects of aliasing, phase distortion and amplitude distortion in the output audio data.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: May 6, 2008
    Assignee: STMicroelectronics Asia Pacific Pte, Ltd.
    Inventors: Mohammed Javed Absar, Sapna George
  • Patent number: 7346640
    Abstract: An image processing apparatus supporting both discrete wavelet transform and discrete cosine transform with reduced hardware resources. The image processing apparatus is composed of an input unit receiving a plurality of pixel data, a controlling unit selecting a desired transform from among discrete wavelet transform and discrete cosine transform, and providing a plurality of coefficients depending on the desired transform, and a processing unit which processes the pixel data using the plurality of coefficients to achieve the desired transform.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: March 18, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Yoichi Katayama
  • Patent number: 7340497
    Abstract: A signal processing device and method for performing a code string transform by transforming a time series signal with a frequency band from 0 to 20 kHz from a coding system into another, wherein the arithmetic operations of MDCT and IMDCT with a limited frequency band from 0 to 15 kHz are carried out at high speed by performing computations using an FFT operation with a short tap length in the IMDCT processing operation. This allows a reduced work area and a higher speed for arithmetic operations by reducing the number of multiplications and additions when performing MDCT operations, IMDCT operation and/or transforming code strings between different coding system.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: March 4, 2008
    Assignee: Sony Corporation
    Inventors: Atsushi Kikuchi, Hiroyuki Honma, Kyoya Tsutsui
  • Patent number: 7330866
    Abstract: A system for frequency-domain scaling for DCT computation. Scale factors are applied to coefficients during the final steps of composition of 2-point DCTs. The number of multiplications and required precision are reduced. Fixed values for various scale factors can be computed and stored prior to executing the DCT so that performance can be improved. The fixed values are derived by knowing the length of the time-domain sequence. Some fixed values can be derived independently of the length of the time-domain sequence. The approach of the invention can also reduce the number of multiplications to compute the transform, and allow smaller bit-width sizes by reducing the number of required high-precision calculations.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: February 12, 2008
    Assignee: NVIDIA Corporation
    Inventor: Fa-Long Luo
  • Patent number: 7325023
    Abstract: Preliminary Modified Discrete Cosine Transform (MDCT) coefficients are computed for a current frame of data and a next frame of data using a long window type. The computed preliminary MDCT coefficients of the current and next frames are then used to determine the window type of the current frame. If the determined window type is not the long window type, final MDCT coefficients are computed for the current frame using the determined window type.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 29, 2008
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Jeongnam Youn
  • Patent number: 7321690
    Abstract: A device and method for determining whether or not an image is blurred. The device and method comprises an input part for receiving an image; a block classification part for dividing the received image into blocks and classifying the divided blocks into character blocks and background blocks; a character block energy calculation part for calculating an average energy ratio of the character blocks; and a blurring detection part for calculating an average energy ratio of the character blocks and determining whether or not the image is blurred based on a comparison of the average energy ratio with a predetermined threshold.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: January 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chae-Whan Lim, Nam-Chul Kim, Ick-Hoon Jang, Chong-Heun Kim
  • Patent number: 7292730
    Abstract: Implementing a two-dimensional inverse discrete cosine transform function includes executing two one-dimensional inverse discrete cosine transforming functions. Each of the one-dimensional functions is controlled to operate on a matrix of coefficients in either of two different directions.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: November 6, 2007
    Assignee: Intel Corporation
    Inventor: Louis A. Lippincott
  • Patent number: 7263544
    Abstract: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: August 28, 2007
    Assignee: Intel Corp
    Inventors: Yan Hou, Hong Jiang, Kam Leung
  • Patent number: 7203717
    Abstract: A technique for computationally efficient evaluation of the Modified Discrete Cosine Transform (MDCT) using the Fast Fourier Transform (FFT) method is presented in which the input of the FFT block consists of a sequence of N complex numbers, and this complex data is evaluated using an N/2-Point FFT only, thereby descreasing computation burden almost by two.
    Type: Grant
    Filed: October 30, 1999
    Date of Patent: April 10, 2007
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Mohammed Javed Absar, Sapna George
  • Patent number: 7136890
    Abstract: An inverse discrete cosine transform (IDCT) apparatus is disclosed. The inverse discrete cosine transform (IDCT) apparatus can satisfy the bit accuracy of the standard recommendation and enable implementation of the ASIC by a smaller logic circuit, and simplify an interface between another sections of a video decoder. According to the present invention the image recovering performance of the video decoder installed to a digital TV receiver can be enhanced.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: November 14, 2006
    Assignee: LG Electronics Inc.
    Inventor: Jin Seok Im
  • Patent number: 7127482
    Abstract: An algorithm and hardware structure is described for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC ( multiply-add-accumulator) kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC (add-multiply-add-accumulator) kernals (described in detail below), when operating in a downsampling mode.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Yan Hou, Hong Jiang, Kam Leung
  • Patent number: 7117236
    Abstract: The present invention provides a device and method for applying 1-D and 2-D DCT and IDCT transforms to sets of input data, typically 8×8 or 16×16 matricies of coefficients. In one embodiment, the present invention provides input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the present invention may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: October 3, 2006
    Assignee: Macronix International Co. Ltd
    Inventors: Jiun-In Guo, Kun-Wang Liu
  • Patent number: 7098818
    Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: August 29, 2006
    Assignee: Fujitsu Limited
    Inventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
  • Patent number: 7096245
    Abstract: The present invention provides an apparatus and method for providing a programmable inverse discrete cosine transform, wherein the transform coefficients are loaded into a memory area of a core transform device and a variety of coding standards can thereby be handled by the same programmable core device. The core device is configured to process a certain sized data block, and the incoming source blocks are converted to conform to this size. After transformation, the proper sized result can be extracted from the transform device output. A switchable speed-up mode provides for 4-point transforms, rather than 8-point transforms. Alternatively, the invention also provides for dedicated transform hardware to be switchably used in conjunction with programmable transform hardware, depending upon the type of coding being used, and the speed of inverse transform desired.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: August 22, 2006
    Assignee: Broadcom Corporation
    Inventors: Vivian Hsiun, Alexander G. MacInnis, Xiaodong Xie, Sheng Zhong
  • Patent number: 7082450
    Abstract: The invention relates to an approximation of a DCT and a quantization which are to be applied subsequently to digital data for compression of this digital data. In order to improve the transform, it is proposed to simplify a predetermined transform matrix to require less operations when applied to digital data. In addition, elements of the simplified transform matrix constituting irrational numbers are approximated by rational numbers. These measures are compensated by extending a predetermined quantization to include the operations which were removed in the simplification of the predetermined transform matrix. The included operations are further adjusted to compensate for the approximation of elements of the simplified transform matrix by rational numbers. If the simplified transform matrix and the extended quantization are used as basis for implementation, a fast transform with a good resulting quality can be achieved.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 25, 2006
    Assignee: Nokia Corporation
    Inventors: Antti Hallapuro, Kim Simelius
  • Patent number: 7065543
    Abstract: The present invention relates to a distributed arithmetic module employing a zero input detection circuit that reduces electric power consumption by avoiding unnecessary calculation. An apparatus for performing a discrete cosine transform (DCT) on a video signal, including; input unit for receiving the video signal in a block by block basis; discrete cosine transform (DCT) unit for receiving each image data block from the input unit and conducting a discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) operation on the received image data block to generate a transformed image data block containing N×M pixel value; zero input detect unit for determining whether pixel values of a current image data block are all “0” and generating a detection signal in order to bypass the DCT/IDCT performing on the current image block; and output unit for outputting the transformed image data block as a transformed video signal.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 20, 2006
    Assignees: VK Corporation, Electronics and Telecommunications Research Institute
    Inventors: Ig Kyun Kim, Kyung Soo Kim
  • Patent number: 7058677
    Abstract: A method for selectable quantization for use in an encoder for compressing video and/or audio data includes processing that begins by receiving discrete cosine transform data of an encoded signal. The processing continues by obtaining a quantization table. The processing then continues by obtaining a plurality of scaling factors. The process then continues by generating a plurality of quantized value sets of the discrete cosine transform data based on the quantization table and the plurality of quantization scaling factors. The resulting data is then multiplied separately by each of the quantization scaling factors to produce the plurality of quantized values sets. The process then continues by selecting one of the plurality of quantized value sets based on quantization selection criteria.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: June 6, 2006
    Assignee: VIXS, Inc.
    Inventors: Indra Laksono, Jason Chan
  • Patent number: 7035332
    Abstract: A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes two sets of lookup tables to provide multiplication and add operations for the DCT and IDCT functions. Another embodiment of a core include one set of lookup tables, while another embodiment of a core includes no lookup table. The DCT/IDCT module provides forward DCT and IDCT functionality without the use of additional multipliers.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: April 25, 2006
    Assignee: WIS Technologies, Inc.
    Inventors: Ouyang He, Li Sha, Shuhua Xiang, Ping Zhu, Yaojun Luo
  • Patent number: 7024441
    Abstract: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Yan Hou, Hong Jiang, Kam Leung
  • Patent number: 7020671
    Abstract: Compressed data are decompressed using an inverse discrete cosine transform (IDCT). A first one directional (1D) IDCT is performed resulting in a plurality of first 1D IDCT coefficients followed by a second 1D IDCT resulting in a plurality of second 1D IDCT coefficients. In performing the first 1D IDCT and the second 1D IDCT a first plurality of intermediate butterfly computations are performed which include performing a plurality of intermediate multiplications resulting in a plurality of initial products and performing a plurality of intermediate additions resulting in intermediate product which are maintained at no more than 16-bits utilizing a round near positive (RNP) rounding scheme. Following the second 1D IDCT a rounding and shifting of the plurality of second 1D IDCT coefficients is performed utilizing a round away from zero (RAZ) rounding scheme resulting in a plurality of output coefficients which comply with the IEEE 1180 standard.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: March 28, 2006
    Assignee: Hitachi America, Ltd.
    Inventor: Arindam Saha
  • Patent number: 7020672
    Abstract: Data compressed according to a lossy DCT-based algorithm, such as the MPEG or MPEG2 algorithms, is decompressed according to a dynamically-selected set of DCT coefficients, with unused coefficients masked out. A macroblock of the data exhibiting little motion is decompressed with a small subset of DCT coefficients, while a macroblock exhibiting more motion is decompressed using a larger subset of DCT coefficients up the full set of DCT coefficients. Average computational complexity is thus kept low, enabling the use of inexpensive equipment, while degradation is minimized.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: March 28, 2006
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventors: Tse-Hua Lan, Zhun Zhong, Yingwei Chen
  • Patent number: 7007055
    Abstract: A fast and precise method to perform inverse and forward Discrete Cosine Transform (DCT) is disclosed. The method may be used for implementing a two-dimensional (2D) inverse or forward DCT that operates on an N×M coefficient block and has a higher accuracy than is specified by the IEEE 1180-1990 standard (for the inverse operation). The disclosed method includes the following stages: based on integer operations, a fixed point one dimensional (1D) DCT may be performed on each row of an input coefficient block, an integer-to-single-precision floating point result conversion may be performed, and a single precision floating point 1D DCT may be performed on each column of the coefficient block resulting from the previous stages.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Sergey N. Zheltov, Stanislav V. Bratanov, Roman A. Belenov, Alexander N. Knyazev
  • Patent number: 7007054
    Abstract: Faster discrete cosine transforms that use scaled terms are disclosed. Prior to application of a transform, equations are arranged into collections. Each collection is scaled by dividing each of the discrete cosine transform constants in the collection by one of the discrete cosine transform constants from the collection. Each of the scaled discrete cosine transform constants are then represented with approximated sums of powers-of-2. During the execution phase the block of input data is obtained. A series of predetermined sums and shifts is performed on the data. The output results are saved.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: February 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Brady, Jennifer Quirin Trelewicz, Joan LaVerne Mitchell
  • Patent number: 6996595
    Abstract: In a system having a plurality of processors 1 to M and each processor has corresponding output registers 1 to N an apparatus and method to transfer is claimed. The data comprises a current group of data and a next group of data. Each group of data comprises a plurality of portions of data. The current group of data from each processor 1 to M is transferred to its corresponding output register 1 to N. Each processor then receives and processes the next group of data. Simultaneously, the portion of data from output register N to output register N-1 is transferred. Similarly, each portion of data from output register N-1 is transferred to output register N-2, and so on. The portion of data from register 1 is transferred to a frame buffer.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: February 7, 2006
    Assignee: Qualcomm Incorporated
    Inventors: Judith LaRocca, Ann Chris Irvine
  • Patent number: 6990506
    Abstract: An integer transform matrix is used for implementing a Discrete Cosine Transform (DCT). Optimized values for the integer transform matrix are derived that satisfy certain normalization constraints and that also minimize the frequency distortion in the transform matrix.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 24, 2006
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Shijun Sun
  • Patent number: 6973469
    Abstract: A method is disclosed for performing a discrete cosine transform (DCT) using a microprocessor having an instruction set that includes SIMD floating point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating point form so that the registers each hold two floating point row data values; and (c) using SIMD floating point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-DCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-DCT, two columns are preferably processed in parallel using SIMD instructions to improve computational efficiency.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: December 6, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei-Lien Hsu, David Horton
  • Patent number: 6907438
    Abstract: A method is disclosed for performing an inverse discrete cosine transform (IDCT) using a microprocessor having an instruction set that includes SIMD floating-point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating-point form so that the registers each hold two floating-point row data values; and (c) using SIMD floating-point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating-point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-IDCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-IDCT, two columns are preferably processed concurrently using SIMD instructions to improve computational efficiency.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: June 14, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Horton, Yi Liu, Wei-Lien Hsu
  • Patent number: 6904151
    Abstract: The present invention relates to the methods of estimation and recovering of general affine geometrical transformations which were applied to data, extensible to any other defined class of geometrical transformations, according to the preamble of the dependent claims. The parameters of the undergone deformation are robustly estimated based on maxima given by a parametric transform such as Hough transform or Radon transform of some embedded information with periodical or any other known regular structure. The main applications of this invention are robust digital still image/video watermarking, document authentication, and detection of periodical or hidden patterns. In the case of periodical watermarks, the watermark can also be predistorted before embedding based on a key to defeat block-by-block removal attack.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: June 7, 2005
    Inventors: Frédéric Deguillaume, Sviatoslav Voloshynovskiy, Thierry Pun
  • Patent number: 6871208
    Abstract: A device and method are described that apply 1-D and 2-D discrete cosine transforms (DCT) and inverse discrete cosine transforms (IDCT) to sets of input data, typically 8×8 or 16×16 matricies of coefficients. One device includes input lines, logic to pre-add input values and generate opcrands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the device may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic or pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: March 22, 2005
    Assignee: Macronix International Co., Ltd.
    Inventors: Jiun-In Guo, Kun-Wang Liu
  • Patent number: RE40854
    Abstract: In an apparatus for carrying out a linear transform calculation on a product signal produced by multiplying a predetermined transform window function and an apparatus input signal, an FFT part (23) carries out fast Fourier transform on a processed signal produced by processing the product signal in a first processing part (21). As a result, the FFT part produces an internal signal which is representative of a result of the fast Fourier transform. A second processing part (22) processes the internal signal into a transformed signal which represents a result of the linear transform calculation. The apparatus is applicable to either of forward and inverse transform units (11, 12).
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: July 14, 2009
    Assignee: NEC Corporation
    Inventor: Masahiro Iwadare