Abstract: In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value if the input is within a first input range. The scale and bias unit also includes a processing unit coupled to the preclamping unit and configured to perform a calculation on the input to generate the output value. The processing unit does not perform the calculation if the input is within the first input range.

Abstract: A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the result D is a canonical-form extended-precision floating point number having a high order component and a low order component. The processor is a fused multiply-add processor with a multiplier, an adder, a normalizer and a rounder. The post-adder data path, the normalizer and the rounder each have a data width sufficient to represent post-adder intermediate results to permit the high and low order words of a correctly-rounded result D to be computed. The mantissas of the extended-precision result D are provided such that the high order word mantissa is stored to double precision registers.

Abstract: One embodiment of the present invention provides a system for performing a minimum/maximum computation for an interval operation. The system operates by receiving at least four floating-point numbers, including a first floating-point number, a second floating-point number, a third floating-point number and a fourth floating-point number. Next, the system computes a minimum/maximum of the at least four floating-point numbers, wherein if the at least four floating-point numbers include one or two default NaN (not-a-number) values and the remaining values are not default NaN values, the default NaN values are ignored in computing the minimum/maximum.

Abstract: A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.

Abstract: A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers, the significand of the floating point result is rounded, and the exponent of the result may be adjusted due to normalization or renormalization. The exponent adjustment due to renormalization or the exponent adjustment due to normalization and renormalization is combined with the significand rounding operation.

Abstract: A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an exponent portion of a standard length from a source without the FPU and transforms the denormal number into a normalized number having an exponent portion of an expanded length greater than the standard length, (2) a floating point execution core, coupled to the load unit, that processes the normalized number at least once to yield a processed normalized number, the expanded length of the exponent portion allowing the processed normalized number to remain normal during processing thereof and (3) a store unit, coupled to the floating point execution core, that receives the processed normalized number and transforms the processed normalized number back into a denormal number having an exponent portion of the standard length.

Abstract: Disclosed is a digital signal processor with a unit of an integral number, on a basis of a characteristic distributing a sign of data composed of a predetermined unit from MSB (most significant bit) to LSB (least significant bit), changing a negative number to a positive number when the sign of data is the negative number and performing a logical OR operation in accordance with each sign of data so as to support a floating point operation through a sign bit, an efficient number and number of 0 of a final result.

Abstract: The present invention provides a method, data processing system and computer program for comparing first and second floating point numbers involving providing a hierarchy of tests arranged to identify from said first and second floating point numbers whether said one or more exception conditions exist. Each test is arranged to generate a hit signal if that test predicts that one or more exception conditions exist. If the executed test generates a hit signal and is not the final test in the hierarchy, the method branches to the next test in the hierarchy, executes that test and returns to the step of determining whether the executed test has generated a hit signal. If the executed test generates a hit signal and is the final test in the hierarchy, an exception signal is generated indicating the presence of one or more exception conditions.

Abstract: A method and system for determining whether a result d of a floating-point operation on operands a, b, c is tiny (may underflow) is disclosed. In one embodiment, a prediction whether d is tiny is made in hardware, but this prediction may include false results. Operands a, b, c are scaled to a′, b′, c′ and then result d′ from the floating-point operation on operands a′, b′, c′ is calculated. A determination whether d will actually be tiny can be determined from the value of d′. A decision may then be made to proceed with either software or hardware calculations of d.

Abstract: A printer controller in which the image data received in indexed format is stored only in indexed format. The image data is converted to long format when required for rendering operations by using an appropriate lookup table. By storing the image data only in indexed format until the time of rendering, the memory requirements within a system may be minimized. According to another aspect of the present invention, floating point operations (providing higher precision) may be used in a interpreter block and fixed point operations (providing more speed) may be used in a rendering block, while avoiding/reducing image artifacts in upscaled images. A check is performed to determine whether a pixel in the upscaled image maps back to fall within the boundary of the source image, and corrective action is taken if the pixel does not fall within the boundary.

Abstract: An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the first detection bits indicate a difference of zero. A second module generates second detection bits from the first and second operands, where the second detection bits indicate a difference of one. A combiner combines the first and second detection bits to determine whether the difference of two numbers is less than two. The apparatus and method is used in determining to bypass normalization in floating point calculation.

Abstract: Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Then a third product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Next a fourth product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. And finally, the output interval is produced including an output interval lower-point and an output interval upper-point, the output interval lower-point being the minimum of the first product and the third product, and the output interval upper-point being the maximum of the second product and the fourth product.

Abstract: Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and a first input interval lower-point. Next, computing an output interval includes producing a second result from the conditional selection, the operands respectively including a second input interval upper-point, the first input interval upper-point, and the first input interval lower-point. Furthermore, computing an output interval includes producing a third result from a conditional division using the first operand, the second operand, and the third operand, the operands respectively including the first result, the second input interval upper-point, and the second input interval lower-point.

Abstract: Operations that involve denormalized numbers are handled by restructuring the input values for an operation as normalized numbers, and performing calculations on the normalized numbers. As a first step in the process of performing an operation, a determination is made whether input values for the operation contain one or more denormalized numbers. For certain types of operations, a determination is made whether the input values are such that the output value from the operation will be a denormalized number. For each operation in which either the input values or output values comprise a denormalized number, the input values are scaled to produce values that are not denormalized. Once the appropriate factoring has been carried out, the requested operation is performed, using normalized numbers, to produce an intermediate result which is then adjusted to account for the initial scaling.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.

Abstract: A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floating point value fl in a general purpose processor. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute conversion operation between fixed-point and floating-point values with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster conversion operations between fixed-point and floating-point values.

Abstract: One embodiment of the present invention provides a system for representing intervals within a computer system to facilitate efficient and sharp arithmetic interval operations. The system operates by receiving a representation of two intervals. These representations include a first floating-point number representing a first endpoint of the interval and a second floating-point number representing a second endpoint of the interval. Next, the system performs an interval arithmetic operation using the interval operands to produce an interval result. In performing this arithmetic operation, if the first endpoint is negative infinity and the second endpoint is finite, the system treats the first endpoint as a negative overflow toward negative infinity. On the other hand, if the second endpoint is positive infinity and the first endpoint is finite, the system treats the first endpoint as a positive overflow toward positive infinity.

Abstract: A method of executing arithmetic operations in a data processing apparatus wherein first and second numbers having a main frame “e-mode format are converted to IEEE double format. Arithmetic operations are then performed using the first and second numbers in IEEE double format to form a result in IEEE double format. The IEEE double format result is then converted back to main frame e-mode format. The conversion of the first and second e-mode numbers to IEEE format includes a step of shifting a mantissa of each e-mode number by a single step of subtracting 2Nexp where Nexp is the exponent of the IEEE double under formation.

Abstract: A method and system for generating numerical test cases for testing binary floating-point arithmetic units for addition and subtraction operations, in order to verify the proper operation of the units according to a specified standard. The space for eligible test-cases is compatible with masks which stipulate the allowable forms of the operands and the result, including constant as well as variable digits in both the exponent and significand fields. The test-cases, which are generated randomly, cover the entire solution space without excluding any eligible solutions. All standard rounding modes are supported, and if a valid solution does not exist for a given set of masks, this fact is reported. The method is general and can be applied to any standard, such as the IEEE floating-point standard, in any precision.

Abstract: Methods and apparatus are disclosed for determining a floating-point exponent associated with an underflow condition or an overflow condition. The methods and apparatus determine the ‘true’ value of a floating-point exponent based on a truncated value of the floating-point exponent passed from a floating-point hardware unit to an exponent determination module when the floating-point hardware unit encounters an underflow condition or an overflow condition. The determined value of the floating-point exponent may then be passed to a floating-point software unit for additional floating-point calculations, if necessary. If the floating-point hardware unit does not encounter an underflow condition or an overflow condition, the floating-point hardware unit and/or the floating-point software unit preferably perform the floating-point operation without the assistance of the exponent determination module.

Abstract: There is provided a parallel computer and a parallel computing method which allows high precision parallel calculation to be executed without requiring a hardware scale while maintaining high calculation speed. A system is constructed by connecting a host processor with a plurality of special purpose processors via buses. The host processor carries out the operation in a format of double-precision floating-point and the special purpose processor carries out the operation in an internal format of floating-point. The special purpose processor comprises an input data converting section for converting from the double-precision to the internal format and an output data converting section for converting from the internal format to the double-precision. Because the sign part and the exponent part can use data in common in the data before and after the conversion, only the mantissa part is converted by a specific procedure.

Abstract: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Abstract: A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. The adder circuit includes intermediate registers to provide multi-threaded capability. Products interleaved in time are accumulated into separate sums simultaneously.

Abstract: A floating point to fixed point converter suitable for determining values for an n-bit frame buffer of a graphics adapter is disclosed. The converter includes a floating point unit that receives a floating point input value and calculates a floating point adjusted input value from the received value. Comparator circuitry is configured to compare a fixed point portion of the adjusted input value to a fixed point comparison value and to generate a fixed point output value responsive to the result of the comparison. The floating point unit may add a floating point constant to the received input to calculate the adjusted input value. The floating point constant may include a rounding component and a range component. The range component adjusts received values into a range defined by a single floating point exponent value such as the range from 1.0 to 2.0.

Abstract: A floating point unit includes a multiplier, an approximation circuit, and a control circuit coupled to the multiplier and the approximation circuit. The approximation circuit is configured to generate an approximation of a difference of the first result from the multiplier and a constant. The control circuit is configured to approximate a function specified by a floating point instruction provided to the floating point unit for execution using an approximation algorithm. The approximation algorithm comprises at least two iterations through the multiplier and optionally the approximation circuit. The control circuit is configured to correct the approximation from the approximation circuit from a first iteration of the approximation algorithm during a second iteration of the approximation algorithm by supplying a correction vector to the multiplier during the second iteration. The multiplier is configured to incorporate the correction vector into the first result during the second iteration.

Abstract: A method for distinguishing an ordinary binary floating point number from an extraordinary binary floating point number is provided, the method including adding 1 to a B-bit biased exponent of a binary floating point number to produce a (B+1)-bit augmented exponent and sign-extending the augmented exponent to produce a (B+n)-bit transformed exponent. The method also includes testing the (B+n)-bit transformed exponent to determine if the (B+n)-bit transformed exponent is less than 2.

Abstract: A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central processing unit having a converter unit and a set of conversion registers. The load/store instructions having data requiring conversion include an index field for identifying one of the conversion registers. Each one of the conversion registers includes information on the type of conversion required and any scaling factors to be applied. Upon receiving one of these instructions, the converter uses the identified conversion register to perform the conversion and stores the converted data into the corresponding register or memory location.

Abstract: A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction.

Abstract: A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable to perform a look ahead operation and establish the location of the MSB (Most Significant Bit) in the calculation results; and combinational circuits for performing the rounding off process and the calculation of the variables by using information concerning a carry, which is generated by the pseudo carry generator and based on the location of the MSB determined by the MSB look ahead circuit.

Abstract: The invention provides circuitry for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to the at least one number, the first part providing a result. A second part is arranged to identify at least one characteristic of the at least one number and to provide an output and correction circuitry for providing, if necessary, a correct result in dependence on the output of the second part, wherein said first and second parts are arranged to operate in parallel.

Abstract: A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the remaining significand by the calculated exponent difference, a first bit inverter, an adder, a leading-zero anticipation circuit for anticipating the consecutiveness of leading zeros from the significands, a leading-zero counter for counting the anticipated number of leading zeros, a left shifter for shifting an output value from the adder, a second bit inverter for taking two's complement of an output value from the left shifter, an incrementer for incrementing an output value from the second bit inverter by one, a compensation shifter for shifting an output value from the incrementer, an exponent subtracter for subtracting the number counted by the leading-zero counter from the larger exponent, and a decrementer for decrementing an output exponent from the exponent subtracter by one.

Abstract: According to the invention, optimization of an application by elimination of redundant operand conversions is disclosed. According to one embodiment, the optimization comprises receiving an application that includes one or more operations, with one or more operands of the operations being converted from a first format to a second format before performing an operation; determining the origin of the one or more operands that are converted from the first format to the second format; and if the origin of any of the one or more operands that are converted from the first format to a second format is a conversion from the second format to the first format, then eliminating the redundant conversion from the second format to the first format and from the first format to the second format.

Abstract: An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding co-efficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding co-efficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation.

Abstract: An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one group, determines a plurality of scale factors for the plurality of operands, respectively, and provides a running sum of the plurality of scale factors. The extended exponent floating point unit further scales the plurality of operands to obtain a plurality of scaled operands, multiplies the plurality of scaled operands to obtain a group product, and scales the group product to obtain a scaled group product. The scaled group product is adjusted based on the running sum. The plurality of operands are grouped such that when all the plurality of scaled operands in the at least one group are multiplied an overflow or underflow will not occur.

Abstract: One embodiment of the present invention provides a system for performing a minimum computation for an interval multiplication operation. This system receives four floating-point numbers, including a first floating-point number, a second floating-point number, a third floating-point number and a fourth floating-point number. The system then computes a minimum of the four floating-point numbers, wherein if the four floating-point numbers include one or more default NaN (not-a-number) values, the system sets the minimum to negative infinity. One embodiment of the present invention provides a system for performing a minimum computation for an interval division operation. This system receives four floating-point numbers, including a first floating-point number, a second floating-point number, a third floating-point number and a fourth floating-point number.

Abstract: In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose.

Abstract: The proposed fast single precision floating point accumulator of the present invention uses base 32 computation in an attempt to completely remove the need for a costly 8-bit subtractor in the exponent path as is commonly found in conventional designs. It also replaces the expensive variable shifter in the mantissa path with a constant shifter which significantly reduces the cost of the present invention relative to earlier floating point accumulators. The variable shifter required for base 2 to base 32 conversion has been moved outside the accumulator loop. This approach allows comparison of the two input exponents using a comparator. The mantissas are shifted by constant amount to bring them into partial alignment. They are then added or the appropriate mantissa is chosen as the result. The input stream to the accumulator does not need to be cumulative.

Abstract: The floating point number data processing means is for use in microprocessor systems and finds application in AC motor drive technology. The format used includes a sign bit, a seven bit signed exponent and an eight bit mantissa. The mathematical functions are performed in a gate array using registers which are mapped into a memory of the microprocessor system, the particular mathematical function being dependent upon a particular choice of registers. An unsigned integer comparison of floating point numbers is used to give a correct result.

Abstract: A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point operand data structure comprises a first portion having floating point operand data and a second portion having embedded status information associated with at least one status condition of the operand data. The status condition may be determined from only the embedded status information. The status condition may also be associated with at least one floating point operation that generated the operand data structure. The outcome of a conditional floating point instruction may be based on the embedded status information without regard to contents of the floating point status register.

Abstract: A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.

Abstract: A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first storage area to higher order bits of a result, moving a second operand occupying higher order bits of a second storage area to lower order bits of the result, and negating one of the first and second operands of the result.

Abstract: A system for providing a floating point sum comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data with the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the sum of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

Abstract: One embodiment of the present invention provides a system for performing a minimum/maximum computation for an interval operation. The system operates by receiving at least four floating-point numbers, including a first floating-point number, a second floating-point number, a third floating-point number and a fourth floating-point number. Next, the system computes a minimum/maximum of the at least four floating-point numbers, wherein if the at least four floating-point numbers include one or two default NaN (not-a-number) values and the remaining values are not default NaN values, the default NaN values are ignored in computing the minimum/maximum.

Abstract: The processing elements of a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

Abstract: Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention provides a method of enhancing support of an interval computation when performing a floating point arithmetic operation, comprising the steps, performed by a processor, of receiving a first floating point operand, receiving a second floating point operand, executing the floating point arithmetic operation on the first floating point operand and the second floating point operand, determining whether a NaN substitution is necessary, producing a floating point result if the NaN substitution is determined to be unnecessary, and substituting an alternative value as the floating point result if the NaN substitution is determined to be necessary.

Abstract: A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for converting the 16-bit floating point number into a representative native floating point value. Thereafter, the native microprocessor floating point instruction set may perform operations upon the converted data. Upon completion, the native floating point data representation may be converted back into the 16-bit floating point value.

Abstract: A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may supply the operand to the analysis circuit. The result generator circuit is responsive to at least one control signal and asserts a result signal if the floating point analysis circuit matches the floating point status to a predetermined format specified by the control signal. The result signal can condition the outcome of a floating point instruction. The result generator may also respond to multiple control signals asserted when testing a single operand for different formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, exact, and inexact.

Abstract: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal,