Abstract: An interface control circuit includes an interface wrapper, a logic circuit, a multiplexer and a command decoder. The interface wrapper transceives a plurality of first signals in a first interface, converts the first signals to a plurality of second signals in a second interface, and generates at least one first command signal according to the first signals. The logic circuit receives the second signals, and generates a second command signal according to the second signals. The multiplexer receives the first command signal and the second command signal, and generates a third command signal according to the first command signal and the second command signal. The command decoder receives the third command signal and generates the decoded command according to the third command signal.

Abstract: An information processing device includes a first processor core of 2n-bits unit, a second processor core of n-bit(s) unit, a DRAM set including a first DRAM and a second DRAM of n-bit(s) unit, a first transmitting path between the first processor core and the DRAM set, a second transmitting path between the second processor core and the first or second DRAM, a transmitting path switching circuit, and a power supply controlling circuit. In normal operation, with switching to the first transmitting path and supplying power to the first processor core and the first and second DRAMs, the first processor core uses the first and second DRAMs. In power saving operation, with switching to the second transmitting path, supplying power to the second processor core and the first DRAM and stopping power to the first processor core and the second DRAM, the second processor core uses the first DRAM.

Abstract: A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

Abstract: Embodiments relate to coordinating the operations of subsystems in a communication system of an electronic device where a coexistence hub device monitors the state information transmitted as coexistence messages over one or more multi-drop buses, processes the monitored coexistence messages and sends out control messages as coexistence messages to other systems on chips (SOCs). The coexistence hub device can also update the operations of the communication system. The coexistence hub device may receive an operation policy from a central processor and may execute the operation policy without further coordination of the central processor. The coexistence hub device broadcasts the control messages as coexistence messages according to the executed operation policy.

Abstract: Described herein are several embodiments relating to modular irrigation controllers. In many implementations, the irrigation controllers are modular in that various functional components of the irrigation controller are implemented in removable modules that when inserted into position within the controller, expand the capabilities of the controller. Also described are various different types of expansion modules that may be coupled to the modular controller, having as variety of functions and features, as well as related methods of use and configuration of these modules in the controller. In some embodiments, a serial communication bus is provided between a control unit of a modular irrigation controller and an expansion module.

Abstract: Switches and groups of IO ports may be divided into separate switch modules and IO modules that can be connected by high-speed low-loss management cables in a variety of configurations. Thereafter, the separate modules may be replaced independently of each other. The switch module may recognize, and thereafter ignore, unconnected ports, removing the performance penalty that sometimes arises when fewer than all available ports are connected. The switch module may rapidly adjust to addition, subtraction, and replacement of connected IO modules.

Abstract: An object of the present disclosure is to provide a network device and a method for setting the network device that can, in developing functional modules, perform abnormality detection based on statistical information and setting verification in consideration of a dependency relationship between the functional modules and statistical information and can address a change in a policy in the setting verification and a change in a condition in the abnormality detection. In the network device according to the present disclosure, an existing setting of each module, external information, a dependency relationship, and a policy are collected at one location (setting verification unit) by using a common language. When a new setting is made to the modules, a new dependency relationship is set, or new external information is acquired, the new setting is sent to the setting verification unit and checked against the existing setting, the external information, and the dependency relationship.

Abstract: Various aspects disclosed herein are directed to dynamic filtering and tagging functionality implemented in collaborative, social online education networks.

Abstract: A method of real-time data security of a communications bus, the method comprising the steps of: reading at least an early portion of a message being transmitted over a communications bus, determining whether the message is suspicious, according to at least one rule applied on the read early portion of the message, and upon determining that the message is suspicious, corrupting at least a part of the message.

Abstract: An apparatus comprises at least one processing device that is configured to control delivery of input-output operations from a host device to a storage system over selected ones of a plurality of paths through a network, wherein the paths are associated with respective initiator-target pairs, the initiators being implemented on the host device and the targets being implemented on the storage system. The at least one processing device is further configured to identify a particular one of the initiators that comprises multiple virtual initiators having respective virtual identifiers, to determine a negotiated rate of the particular initiator, to determine a negotiated rate of a corresponding one of the targets, and to limit amounts of bandwidth utilized by the multiple virtual initiators in communicating with the corresponding target based at least in part on the negotiated rate of the particular initiator and the negotiated rate of the corresponding target.

Abstract: An aspect includes memory access optimization for an I/O adapter in a processor complex. A memory block distance is determined between the I/O adapter and a memory block location in the processor complex and determining one or more memory movement type criteria between the I/O adapter and the memory block location based on the memory block distance. A memory movement operation type is selected based on a memory movement process parameter and the one or more memory movement type criteria. A memory movement process is initiated between the I/O adapter and the memory block location using the memory movement operation type.

Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the IO request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.

Abstract: A vehicle control apparatus controls a vehicle that is performing automated driving traveling. The vehicle control apparatus comprises: a communication unit configured to acquire deceleration information of another vehicle by communication with the other vehicle; a setting unit configured to set, for a deceleration of the vehicle, a range of an allowable deceleration that allows a vehicle speed change within a predetermined range; a determination unit configured to compare the deceleration of the vehicle with a deceleration included in the deceleration information and determine whether deceleration control of matching the deceleration of the vehicle with the deceleration of the other vehicle can be performed within the range of the allowable deceleration; and a control unit configured to perform the deceleration control of the vehicle based on a determination result of the determination unit.

Abstract: Embodiments for performing rolling software upgrades in a disaggregated computing environment. A rolling upgrade manager is provided for upgrading one or more disaggregated servers. A designated memory area is used for storing an updated software component, and a disaggregated server is switched to the designated memory area from a currently assigned memory area when performing the software upgrade. A process state and program data is maintained in the currently assigned memory area while maintaining the updated software component in the designated memory area such that the process state and program data are read from the currently assigned memory area and the updated software component is read from the designated memory area during currently executing operations of the disaggregated server.

Abstract: This disclosure relates to a communicating apparatus, a communication method, a program, and a communication system that each enable execution of more reliable communication. A communicating apparatus includes a transmitting and receiving part that executes transmission and reception of signals with at least one or more other communicating apparatuses through a data signal line and a clock signal line, and an error avoiding part that, in a state where a communication system configured to be able to execute communication through a bus already operates, executes a process of avoiding occurrence of any error occurring when a communicating apparatus is additionally connected to the communication system. This technique is applicable to, for example, a bus IF.

Abstract: According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.

Abstract: A server with a master-slave architecture and a method of reading and writing information thereof provided by the present disclosure include a master node, a multi-path selector and at least two slave nodes. Each slave node is connected to the master node through the multi-selector. The slave node includes a slave-node BIOS and a slave-node memory. The slave-node BIOS is configured to record slave-node information in the slave-node memory. The master node includes a master-node BIOS, a master-node memory and a baseboard management controller. The master-node BIOS is configured to record master-node information in the master-node memory. The baseboard management controller is configured to access the master-node memory and decide to access the slave-node memory of one of the slave nodes through the multi-path selector.

Abstract: In one aspect of buffer credit management in accordance with the present description, buffer over-commit logic determines a buffer over-commit value as, in one embodiment, proportional to a determined difference value between the average duration of an I/O operation over data transmission channels connected to a target control unit, and an average of cumulative lifespans that a set of buffers of the target control unit is committed to an I/O operation. In another aspect, buffer over-commit logic determines a buffer over-commit value as, in one embodiment, inversely proportional to buffer lifespan. In another aspect, buffer over-commit logic determines a buffer over-commit value as, in one embodiment, proportional to the determined difference value and inversely proportional to buffer lifespan. Other features and aspects may be realized, depending upon the particular application.

Abstract: An information processing device capable of reducing an amount of data to be monitored in an onboard system is provided. The information processing device obtains a first log from the onboard system, determines whether an abnormality is included in communication data of the first log using the first log, and, in a case where the abnormality is determined to be included in the communication data, outputs first detection results indicating that the abnormality is included in the communication data to the onboard system. The first detection results is output, as a transmission instruction to cause transmission of a second log from the onboard system to the information processing device, with the second log including a larger amount of data than the first log.

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Abstract: A method and system for manages mapping of universal serial bus (USB) connectors to a plurality of USB host controllers. The method determines an enumeration of USB connectors in a system, identifying USB host controllers in the system, generating a grouping for a USB connector with USB host controllers, and configures USB routing in the system to map the USB connector with the USB host controllers according to the grouping.

Abstract: An event notification method of a storage device includes detecting an event in the storage device, writing an asynchronous event information entry corresponding to the event in a completion queue of a host, and transmitting an interrupt corresponding to a transmission of the asynchronous event information entry to the host. The asynchronous event information entry is provided to the host regardless of reception of an asynchronous event request command from the host.

Abstract: An example system includes a universal serial bus receptacle, a hub controller coupled to the receptacle, and a monitor scalar coupled to the hub controller. In that example, the hub controller may receive an information scheme from a device and determine a display arrangement for data of the device. In that example, the monitor scalar causes a screen to display data of the device and a power consumption level.

Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.

Abstract: An example frame shuffle is communicatively coupled to a midplane of a frame. The frame shuffle includes a first group of optical connectors. Each of which are communicatively coupled to a resource device via the midplane. The frame shuffle also includes a second group of optical connectors, each of which communicatively couples with a frame shuffle of an adjacent frame. The frame shuffle also includes a routing device to optically interconnect the resource devices and another group of resource devices of the adjacent frame. The frame shuffle also includes a frame shuffle fan to provide fresh air through the frame shuffle and direct exhaust air through the midplane.

Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.

Abstract: Embodiments of the present invention relate to systems and methods for ingesting input data containing a plurality of records into a data lake. In an embodiment, the method comprises splitting the input data into a plurality of input splits consisting of a balanced number of records; reading the records from the plurality of input splits in parallel, regardless of the format and encoding of the input source; converting the input data within the records into at least one key/value pair; transforming the values input data into a serializable format; sorting the key/value pairs of the transformed values such that the records are sorted in the same order as they were read; writing the transformed values to an output file; and storing the output file to the data lake.

Abstract: One embodiment of the present disclosure describes a loopback network including a loopback datapath and a plurality of memory devices. The plurality of memory devices may include a first memory device coupled to a first trunk connector of the first loopback datapath via a first branch connector. The plurality of memory devices may also include a second memory device coupled to the first trunk connector of the first loopback datapath via a second branch connector. When data communicated with the first memory device is targeted by loopback parameters, the first memory device may output a first loopback data signal generated based at least in part on the first data to the first loopback datapath, and the second memory device may block output from the second memory device to the first loopback datapath.

Abstract: An image transmission method uses image transmission equipment to transmit image signals from an electronic device to a display device, the equipment which includes a base device coupled to the display device, and a peripheral device coupled to an electronic device. The base device wirelessly communicates with the peripheral device. After the electronic device obtains an image transmission program from an outside source existing outside the peripheral device and executes the image transmission program, image signals from the electronic devices can be transmitted to the display device via the peripheral device and the base device.

Abstract: A master node of a distributed acquisition system is provided. The master node includes a communication interface for interfacing between a control component and a bus and the control component. The bus is coupled to one or more slave nodes distributed in the acquisition system. The control component is configured to acquire a configuration that provides a definition for a packet interval, wherein the packet interval definition provides an adequate timing margin to ensure that communication packets transmitted by the master node and the one or more slave nodes occur only at harmonics of the packet interval definition, distribute a time reference packet of the communication packets based on the packet interval definition via the bus to all of the slave nodes of the distributed acquisition system, and schedule transmission of communication packets transmitted by the master node via the bus to the one or more selected slave nodes based on the packet interval definition.

Abstract: A power management system and a power management method are provided. The power management system includes a host manager and at least one server. The server communicates with the host manager. The server includes at least one processor, at least one voltage regulator, and a voltage regulator controller. The voltage regulator provides an actual power to the corresponding processor. The voltage regulator controller adjusts the actual power provided by the voltage regulator. The host manager controls the voltage regulator controller in the server and uses the voltage regulator controller to adjust the actual power provided by the voltage regulator for managing a power of the processor.

Abstract: An information processing system includes a first information processing device, and a second information processing device, wherein the first information processing device includes a first memory that stores first firmware in which first setting information related to a first setting of first hardware of the first information processing device is recorded, and a first processor configured to generate, by executing the first firmware, data including the first setting information recorded in the first firmware, and the second information processing device includes a second memory that stores second firmware for reproducing the first setting in setting processing of second hardware of the second information processing device based on the first setting information included in the generated data, and a second processor configured to reproduce, by executing the second firmware, the first setting based on the first setting information in the setting processing of the second hardware.

Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

Abstract: A controller may include a first processor suitable for sequentially storing commands provided from a host into one of first and second mailboxes of a memory according to types of the commands; and a second processor suitable for serving the commands stored in the first and second mailboxes, wherein, when provided from the host is a first command corresponding to the same logical address as a second command stored in the second mailbox, the first and second commands being of different types, the first processor stores the first command into the first mailbox and stores into the memory a priority information representing the second command having a higher processing priority to the first command, and wherein the second processor serves the commands stored in the first mailbox and the second mailbox by referring to the priority information.

Abstract: A memory system memory system includes a first chip configured to perform a first operation, a second chip configured to perform a second operation, and a stacked memory device including a stacked structure of a plurality of memories. The stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus.

Abstract: An apparatus includes a processor and a machine-readable medium coupled to the processor and comprising instructions. The instructions, when loaded into the processor and executed, configure the processor to identify that a USB element has attached to a USB hub at a port, classify the USB element according to power operations of the USB element, and assign an upstream or downstream setting of the port based upon the classification of the USB element based on power operations of the USB element.

Abstract: A communication device may include a wireless interface configured to repeat operating sequentially in a plurality of states including a first state and a second state. The communication device may acquire first information from the wireless interface in a case where the wireless interface operating in the first state sends the first polling signal to a first external device and receives a response signal to the first polling signal from the first external device, and supply a specific signal to the wireless interface in a case where the first information is acquired from the wireless interface, the specific signal being for causing the wireless interface to use, as a duration time period of the second state, a specific time period instead of the second predetermined time period, the specific time period being longer than the second predetermined time period.

Abstract: A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function.

Abstract: Systems, methods, and devices for assigning addresses to a plurality of functional modules carried by a movable object are provided. In one aspect, a method can comprise: (a) transmitting an activation signal from a control module to a functional module of the plurality of functional modules via a first communication interface, thereby activating the functional module for addressing, wherein the plurality of functional modules are each configured to control a component of the movable object; (b) transmitting an addressing signal comprising an address from the control module to each functional module of the plurality of functional modules via a second communication interface different from the first communication interface, thereby causing the address to be assigned to the activated functional module of step (a); and (c) repeating steps (a) and (b) for each functional module, thereby assigning an address to each functional module.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.

Abstract: An access control apparatus includes a memory, and a processor coupled to the memory and configured to, in response to an access request to a storage device, output an access command through a first path to a first controller among a plurality of controllers that control the storage device, the access command being a command to access the storage device, when no response to the access command to the first controller is received before a predetermined time passes after the output of the access command, control a second controller different from the first controller among the plurality of controllers through a second path coupled to the second controller such that the second controller stops processing executed by the first controller according to the access command, and output the access command through the second path after receiving a response to the control on the second controller.

Abstract: A message processing system that provides a processing flow, the message processing system comprising an input message consumer configured to consume input messages from an input message queue, where the input messages comprise priority information. The message processing system includes a command producer configured to produce commands for a next step in the processing flow. Each command produced may include a target time determined using priority information extracted from an input message to which that command corresponds. The message processing system comprises a queue for commands. The message processing system further comprises a command consumer configured to select commands that have expired target times from the command queue for processing and consume the selected commands from the command queue.

Abstract: A semiconductor device preventing reduction of reliability due to the impact of heat after shipment is provided. A semiconductor device of the disclosure includes a built-in self-test circuit 110 and a resistive random-access memory. The built-in self-test circuit 110 includes a reforming information setting part 230 for performing reforming of the resistive random-access memory. When the operation of a forming execution part 220 or a test execution part 210 is performed, a flag is set to “1” for the reforming information setting part 230. Moreover, when a power supply mounted on a circuit board by IR reflow is turned on, the built-in self-test control part 200 references the flag of the reforming information setting part 230, and if the flag is “1”, then the forming execution part 220 executes the reforming of the resistive random-access memory.

Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.

Abstract: Radio-assisted tamper protection in a HSM electronic device. Radio signals received from one or more network elements on a network are used for determining values of a set of network parameters that identify the electronic device in a predefined state. A tamper detection state signal may be generated responsive to the detected tampering state. The electronic device may be inhibited from operation in response to the tamper detection state signal.

Abstract: Translation of boot code read request commands from an on-board processor of a system on a chip (SoC) from a bus protocol (e.g., advanced high-performance bus (AHB) protocol) into a sequence of commands understandable by a serial interface of the SoC to read boot code from an off-board (e.g., flash or other non-volatile) memory device. The serial interface of the memory device may include a relatively low pin count (e.g., 5 pins) and boot code of the memory device may be modified after tape-out of the SoC free of necessitating a subsequent tape-out of the SoC.

Abstract: An example method to hide a presence of a storage device is provided herein. The method masks the presence of the storage device using a microcontroller that controls a presence bit. The method unmasks the presence of the storage device using the array controller to instruct the microcontroller to change the value of the presence bit after installation is complete.

Abstract: An interconnect, and method of handling supplementary data in an interconnect, are provided. The interconnect has routing circuitry providing a plurality of paths, and routing control circuitry to use the plurality of paths to establish routes through the interconnect between source devices and destination devices coupled to the interconnect, to enable system data to be routed through the interconnect between the source devices and the destination devices. The system data relates to functional operation of a system comprising the interconnect, the source devices and the destination devices. At least a subset of the paths are redundant paths whose use by the routing control circuitry provides the system data with resilience to faults when routing the system data through the interconnect.

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.