Abstract: A device according to various embodiments may comprise: a transceiver unit configured to transmit or receive information; and a control unit operatively coupled to the transceiver unit, wherein the control unit may be configured to receive, from each of a plurality of control devices that transmit a request for data to a storage device, state information of each of the plurality of control devices, to determine a threshold value for an outstanding data request of each of the plurality of control devices on the basis of the received state information, and to transmit the threshold value to at least one other device.

Abstract: A storage system in one embodiment comprises a plurality of storage devices and a storage controller. The storage system is configured to implement a loopback replication process in which one or more source storage objects are replicated to one or more corresponding target storage objects within the storage system. The storage system is further configured to divide a storage space provided by at least portions of the storage devices of the storage system into slices, to subdivide the slices into source slices and target slices, and to replicate a source storage object associated with at least one of the source slices to a target storage object associated with at least one of the target slices. The source storage object may be associated with at least one of the source slices by, for example, storing the source storage object across portions of the storage devices in designated ones of the source slices.

Abstract: A wireless receiving device for a human powered vehicle comprises a receiver having a first mode, and a second mode in which the receiver consumes less electric power than in the first mode. A controller is configured to set the receiver with the second mode if the receiver does not receive the communication signal in a first-mode period during which the receiver operates in the first mode. The controller is configured to count a consecutive number of a plurality of no-communication periods if no-communication periods consecutively occur. The controller is configured to set the receiver with the first mode if the consecutive number of the no-communication periods is less than a count threshold. The controller is configured to control the receiver to continue the second mode until a release condition is satisfied if the consecutive number is more than or equal to the count threshold.

Abstract: A bus system is provided. The bus system includes a master device, a bus, and a plurality of slave devices electrically connected to the master device via the bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. When a first slave device communicates with the master device through the bus, in a first phase of a plurality of phases in each assignment period, the first slave device sets the alert-handshake control line to a first voltage level via the alert handshake pin, wherein the first phase corresponds to the first slave device. In the phases other than the first phase in each assignment period, the alert-handshake control line is at a second voltage level. Each of the phases includes two clock cycles.

Abstract: The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. A bus IF is constituted by a master having an initiative of communication and a slave that communicates with the master under the control of the master. Additionally, the slave is provided with a detection unit that, when detecting a change in level of a signal line representing a declaration of initiation or end of communication by the master, outputs a detection signal indicating that the change in level of the signal line representing a declaration of initiation or end of communication has been detected, and a false detection avoidance unit that invalidates output of the detection signal during a specific time slot set in advance. The present technology can be applied to, for example, a bus IF that performs communication in conformity with the I3C standard.

Abstract: Electronic devices according to various embodiments of the present invention comprise: a connector for communicating serial data to an external electronic device; a nonvolatile memory; and a processor, wherein the processor is configured to: acquire identification information of the external electronic device via the connector; confirm whether or not a designated mode of the external electronic device is supported at least on the basis of the identification information; based on the identification that the external electronic device supports the designated mode, acquire first additional information associated with the external electronic device; based on the identification that the external electronic device does not support the designated mode, acquire second additional information associated with the external electronic device; and store the identification information or at least a part of the second additional information in the nonvolatile memory.

Abstract: A device includes a general-purpose input/output node, a serial identifier register, and serial identifier reassignment circuitry. The serial identifier register stores a serial identifier associated with the device. The serial identifier reassignment circuitry is coupled to the general-purpose input/output node and the serial identifier register. The serial identifier reassignment circuitry sets a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node. By setting a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node, the serial identifier may be easily changed using a pull-up or pull-down resistor external to the device.

Abstract: Various embodiments execute a program with improved cache efficiency. In one embodiment, a first subset of operations of a program is performed on a plurality of objects stored in one or more data structures. The first subset of operations has a regular memory access pattern. After each operation in the first subset of operations has been performed, results of the operation are stored in one of the plurality of queues. Each queue in the plurality of queues is associated with a different cacheable region of a memory. A second subset of operations in the program is performed utilizing at least one queue in the plurality of queues. The second subset of operations utilizes results of the operations in the first subset of operations stored in the queue. The second subset of operations has an irregular memory access pattern that is regularized by localizing memory locations accessed by the second subset of operations to the cacheable region of memory associated with the at least one queue.

Abstract: A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

Abstract: The electronic device includes a master element and a plurality of slave elements that are daisy-chain-connected. The slave element includes an input terminal connected to a slave element adjacently provided on the opposite side of the master element, an output terminal connected to the slave element adjacently provided on the side of the master element or the master element, and a first switch that is provided in a section between the input terminal and the output terminal used as a transmission path of transmission data and is connected to the transmission path in series. The master element receives the transmission data transmitted from the slave element to be the transmission source via the transmission path, and at least the slave element to be the transmission source includes a data transmission unit that is connected to the transmission path via a second switch and transmits the transmission data.

Abstract: An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.

Abstract: A method can be used for monitoring a processing circuit. The processing circuit generates a response to a request and the response is compared with an expected response. A pass pulse is generated when the response matches the expected response. The causing, comparing and generating steps are repeated a number of times A frequency at which pass pulses occur is evaluated.

Abstract: Systems, methods, and apparatus for optimizing bus latency using bit-interleaved bidirectional transmission on a serial bus are described. A method performed at a device coupled to a serial bus includes pairing with a second device in a transaction to be conducted over the serial bus, transmitting a first data bit to the second device over a data line of the serial bus in a first part of each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus, and receiving a second data bit transmitted by the second device on the data line in a second part of each cycle. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

Abstract: Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide, at most, two integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device (i.e., a master device). At least one of integrated circuits may comprise a first interface and a second interface, wherein the second interface is connected to the host in a manner that is opposite that of the first interface.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, a plurality of slave devices electrically connected to the master device via the eSPI bus, and a first resistor. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. The first resistor is coupled between the alert handshake control line and a power supply. Each slave device obtains the number of slave devices according to a first voltage of the alert handshake control line.

Abstract: A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.

Abstract: A system comprising an arrangement of multiple processor modules, and an external interconnect for communicating data in the form of packets to outside the arrangement. The interconnect comprises an exchange block configured to provide flow control. One of the processor modules is arranged to send an exchange request message to the exchange block on behalf of others with data to send outside the arrangement. The exchange block sends an exchange-on message to a first of these processor modules, to cause the first module to start sending packets via the interconnect. Then, once this processor module has sent its last data packet, the exchange block sends an exchange-off message to this processor module to cause it to stop sending packets, and sends another exchange-on message to the next processor module with data to send, and so forth.

Abstract: Apparatus and associated methods relate to a networked system having a master and multiple slaves, where each slave stores a unique (actual) slave address and a non-unique (virtual) slave address in memory, such that each slave is configured to respond to request messages addressed to the slave's non-unique slave address if a sensor device associated with the is in an active state when the slave receives the request message. In an illustrative example, the networked system may be a Fieldbus-style network (e.g., a network implementing the Modbus protocol). A sensor device may be a break-beam, capacitive touch, or push-button device, for example. An output indicator/actuator may be associated with a sensor device to indicate the status of the sensor device to a user. A networked system implementing sensor-activated response gating may beneficially expand the number of slave devices on the network while achieving low latency response times.

Abstract: An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device.

Abstract: A system for preventing faulty connection between PoC and PoE. The system includes a signal generating circuit for generating a detection signal of a detection format of a powered device. A signal feedback circuit is configured to receive the detection signal, and to send a feedback signal to a power source equipment. A signal detecting circuit is configured to detect the feedback signal. A first control switch is coupled to the signal detecting circuit. A second control switch is coupled to the signal feedback circuit.

Abstract: An electronic device associates first information and at least a first portion of a first image, and uses a second image that includes a portion corresponding to at least the first portion of the first image to access the associated first information.

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: A waveform observation system includes two communication nodes, a waveform observation apparatus, and a signal generation portion. The two communication nodes execute a full-duplex communication by a differential signal through a transmission line. The waveform observation apparatus observes a communication signal waveform in the transmission line in response to an input of a trigger signal. The signal generation portion outputs the trigger signal. One of the two communication nodes generates a clock signal, and transmits a signal in synchronization with the clock signal. Remaining one of the two communication nodes reproduces the clock signal included in the signal received from the one of the two communication nodes, and transmits a signal in synchronization with the clock signal that is reproduced. The signal generation portion outputs the trigger signal when equal to or more than two symbols indicated by the signal output to the transmission line consecutively coincide with one another.

Abstract: A first device and a second device enter a USB monitoring mode. The second device transmits monitoring messages on a periodic basis, while the first device has a monitoring timer that it resets each time a monitoring message is received. If a monitoring message is not received before the monitoring timer expires, the first device starts a reconnect timer. After a certain number of failed attempts to receive monitoring messages, the first device takes corrective action to restore USB communications.

Abstract: Provided are a data communication system for a high speed interface and a data transmission apparatus and a data reception apparatus of the data communication system. The data communication system includes the data transmission apparatus that configures a packet including a command and a plurality of components, determines a run length of data of the packet, and performs encoding, and the data reception apparatus that decodes the data of the encoded packet.

Abstract: A microcomputer including first and second CPUs is provided. The first and second CPUs may execute identical control programs in parallel. The microcomputer may control a write access by the first or second CPU. The microcomputer may compare an output of the first CPU with an output of the second CPU. Data is written to a write target unit. The microcomputer outputs a write response signal to the first and second CPUs when a data write destination of the first and second CPUs is the write target unit. The microcomputer outputs an abnormality determination signal when data output from the first CPU mismatches with data output from the second CPU. The microcomputer writes the data to the write target unit when the data write destination of the first and second CPUs is the write target unit and the abnormality determination signal is not input.

Abstract: A circuit for controlling a memory includes a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator generates at least one frequency control signal. The clock generator, coupled to the frequency generator, increases or decreases the frequency of a clock signal by a multiple number of times according to the frequency control signal, such that the frequency of the clock signal is adjusted from an initial frequency to a target frequency. The memory controller, coupled to the clock generator, receives the clock signal and controls the memory according to the clock signal.

Abstract: Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

Abstract: A CPU of an MFP receives battery information from a first external device via a first interface, determines whether a total amount of electric power supplied to a plurality of interfaces from a power supply is maintained, and reduces an amount of the electric power supplied to the first external device via the first interface in a case where determining that the first external device has no battery based on the battery information in response to determining that the total amount of the electric power supplied to the plurality of the interfaces from the power supply is not maintained.

Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.

Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Abstract: An apparatus for providing a BMC via an M.2 slot includes a presence module that determines whether a baseboard management controller (“BMC”) is coupled to an M.2 expansion slot, the M.2 expansion slot configured to also receive a non-BMC device, a bus module that enables communication between a serial peripheral interface (“SPI”) bus and the M.2 expansion slot in response to the BMC being present in the M.2 expansion slot, and a signal conversion module that receives management control signals from the BMC via an unused pin-out of the M.2 expansion slot, in response to the BMC being present in the M.2 expansion slot, and transfers the management control signals to the SPI bus.

Abstract: Graph data of a DAG is received. The data describes a module to be started by way of nodes connected by edges, wherein some nodes are submodule nodes that correspond to submodules of said module. Submodule nodes are connected via edge(s) that reflect a data dependency between the corresponding submodules. Each of said submodules is a hardware module or a software submodule, capable of producing and/or consuming data that can be consumed and/or produced, by other submodule(s) of said module, based on the DAG. Asynchronous execution is started of two of said submodules, respectively corresponding to two submodule nodes located in independent branches of the DAG. A third submodule node(s) is determined that is a descendant of each of said two submodule nodes, according to an outcome of the execution of the corresponding two submodules. Execution is started of a third submodule that corresponds to the determined third submodule node.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: A bus system is provided. The bus system includes a master device, a bus and a plurality of slave devices. The slave devices and the master device are electrically connected through the bus. The master device communicates with the slave devices by using a one-to-one communication mechanism. The slave devices communicate with the master device by using an arbitration mechanism in which one of the slave devices is selected to communicate with the master device.

Abstract: A control system that distributes information from a control device to a reception device includes a read request transmission unit that transmits a read request for information to the control device, an information generation unit that generates information in response to the read request, an information transmission unit that transmits the generated information to the reception device, and a distribution cycle computation unit that computes a distribution cycle based on a generation interval of the read request. The information transmission unit transmits the information in accordance with the distribution cycle computed by the distribution cycle computation unit.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

Abstract: Technologies for managing errors in a remotely accessible memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory sled is to write test data to a byte-addressable memory region in the memory pool. The memory region is to be accessed by a remote compute sled. The memory sled is also to read data from the memory region to which the test data was written, compare the read data to the test data to determine whether a threshold number of errors are present in the read data, and send, in response to a determination that the threshold number of errors are present in the read data, a notification to the remote compute sled that the memory region is faulty.

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

Abstract: Systems, methods, and apparatus for improving end-to-end timing closure of a serial bus are described. An apparatus is coupled to a serial bus through an interface circuit and has a clock generator that provides a first clock signal, a delay circuit that is adapted to generate a second clock signal by delaying the first clock signal, and a controller that is configured to cause the interface circuit to use an edge of the first clock signal to initiate transmission of a first data bit over the serial bus during a write operation, delay the first clock signal to obtain a second clock signal, and cause the interface circuit to use an edge of the second clock signal to capture a second data bit from the serial bus during a read operation. The edge of the second clock signal is delayed with respect to the edge of the first clock signal.

Abstract: A method of switching an apparatus state of a first apparatus having a first universal serial bus (USB) interface connected via a connecting wire with a second USB interface of a second apparatus is provided. The method may include receiving a state switching instruction, setting a level of a configuration channel (CC) in a USB interface circuit corresponding to the first USB interface from a first high level to a first low level via a logic controller of the first apparatus when the state switching instruction instructs the first apparatus to perform a master-to-slave switch, and setting the level of the CC in the USB interface circuit corresponding to the first USB interface from the first low level to the first high level via the logic controller of the first apparatus when the state switching instruction instructs the first apparatus to perform a slave-to-master switch.

Abstract: A transfer device includes: a converter configured to convert an address contained in a command CMD1 transmitted from a master device, to an address indicating an internal slave device, and transfer a command CMD2K to the stated internal slave device; a first parity calculator configured to calculate a first parity bit formed of one bit for the command CMD2K; and a judgment circuit configured to judge whether or not a predetermined abort condition is satisfied. When the predetermined abort condition is satisfied, the converter outputs the first parity bit as a parity bit of the command CMD2K.

Abstract: A data communication system applied in an Inter-Integrated Circuit (I2C) bus serving more than one master device includes a first master device, a second master device, and a logic control unit. The logic control unit receives serial data line (SDA) signal and serial clock line (SCL) signal from the I2C bus of the first master device and of the second master device, and determines a priority between the first master device and the second master device, control of the I2C bus without prejudicing any current messaging is allocated accordingly. A data communication method is also provided.

Abstract: A processor comprising multiple tiles on the same chip, and an external interconnect for communicating data off-chip in the form of packets. The external interconnect comprises an external exchange block configured to provide flow control and queuing of the packets. One of the tiles is nominated by the compiler to send an external exchange request message to the exchange block on behalf of others with data to send externally. The exchange sends an exchange-on message to a first of these tiles, to cause the first tile to start sending packets via the external interconnect. Then, once this tile has sent its last data packet, the exchange block sends an exchange-off control packet to this tile to cause it to stop sending packets, and sends another exchange-on message to the next tile with data to send, and so forth.

Abstract: A communication system that involves superimposing data over DC power. The data takes the form of high bitrate digital signals, where the bitrate is much higher than 0 Hz (DC); this separation allows the AC signal to be easily separated from the DC power. The physical system consists of a two conductor cable, and integration is modular, in that multiple slaves can be connected and disconnected to a master through a routing bus also comprising two conductors. The master can communicate bi-directionally with the slave(s), and the data is encoded using DC-balanced encoding in an FPGA. The data is sent to and from a differential signaling transmitter/receiver pairs at each end of the cable. The system is may be used with position sensors, and provides the benefit of reducing cable costs and sensor size due to the decrease in number of conductors and elimination of power components in the sensor.

Abstract: A computer-implemented method includes pseudo-invalidating a first Dynamic Address Translation (DAT) table of a DAT structure associated with a workload. A page fault occurring during translation of a virtual memory address of data required by the workload is detected. Responsive to the page fault, the DAT structure is traversed. The DAT structure includes one or more DAT tables, and each DAT entry in each of the one or more DAT tables is associated with an in-use bit indicating whether the DAT entry is in use. Traversing the DAT structure includes pseudo-invalidating each of one or more DAT entries in the DAT structure that are involved in translating the virtual memory address for which the page fault occurred; and identifying a first page frame referenced by the virtual memory address for which the page fault occurred. The data in the first page frame is processed responsive to the page fault.

Abstract: The described device is used for communicating with a sensor, especially in the form of a touch-sensitive input and/or output device, e.g. a touch screen, via a control unit that can be controlled using a remote controller. A functional block that performs signaling to communicate with the control unit is provided in a receiver component which is or can be connected to a transmitter component via a communication link.

Abstract: A display apparatus includes a display panel including a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the plurality of data lines including a plurality of first data lines and a plurality of second data lines, a scan driver configured to sequentially output a plurality of scan signals to the plurality of scan lines, a first data driver circuit configured to sequentially output a plurality of first data signals to the plurality of first data lines, and a second data driver circuit configured to sequentially output a plurality of second data signals to the plurality of second data lines based on a feedback signal received from the first data driver circuit.