Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.
Type:
Grant
Filed:
December 20, 2019
Date of Patent:
March 30, 2021
Assignee:
Micron Technology, Inc.
Inventors:
Robert M. Walker, James A. Hall, Jr., Frank F. Ross
Abstract: A method for a data search includes: executing a first process of obtaining a query template used for generating a query, the query template including an output definition statement and a search condition statement, the output definition statement indicating one or more data items as search targets, and the search condition statement indicating a relationship between an identifier to be designated by a search request and the one or more data items, the relationship including a parameter to be replaced by the designated identifier when the query is generated using the query template; executing a second process when the search request includes identifiers, the second process including generating a query based on first query templates each of which is the query template obtained by the first process based on each of the identifiers; and executing a third process that includes obtaining a search result searched based on the generated query.
Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
Type:
Grant
Filed:
July 16, 2015
Date of Patent:
March 9, 2021
Assignee:
NXP B.V.
Inventors:
Surendra Guntur, Sebastien Antonius Josephus Fabrie, Jose de Jesus Pineda de Gyvez
Abstract: The present invention includes provides secure, instant, and anonymous connections between two devices. The invention pairs a “cap” device with a capacitive touchscreen to a “cam” device with a camera sensor. For example, typical smartphones and tablets can be paired with each other, and these devices can be paired to even larger touchscreens, such as smart whiteboards and touchscreen monitors. The invention uses the cap device's touchscreen to detect and track the cam device, and displays color-modulated pairing data directly underneath the camera once the camera is touching the screen. The pairing data is used as configuration data for a bidirectional link, such as an ad-hoc WiFi or Bluetooth link. These links are established without requiring user configuration. As such, the present invention provides a unidirectional communication mechanism from the touchscreen to the camera, which is used to bootstrap a full bidirectional, high-speed link.
Type:
Grant
Filed:
April 20, 2017
Date of Patent:
March 9, 2021
Assignee:
CARNEGIE MELLON UNIVERSITY
Inventors:
Bo Robert Xiao, Christopher Harrison, Scott E. Hudson
Abstract: In response to a detected presence of an intended target appliance within a logical topography of controllable appliances identity information associated with the intended target appliance is used to automatically add to a graphical user interface of a controlling device an icon representative of the intended target appliance and to create at a Universal Control Engine a listing of communication methods for use in controlling corresponding functional operations of the intended target appliance. When the icon is later activated, the controlling device is placed into an operating state appropriate for controlling functional operations of the intended target appliance while the Universal Control Engine uses at least one of the communication methods to transmit at least one command to place the intended target appliance into a predetermined operating state.
Abstract: An external information saving unit sets a reference word related to a situation of a change element at reception of external information and associates and saves the external information and the reference word in an information DB. An external information extraction unit extracts a search word from search information input by a user and extracts the external information associated with the reference word, in which a matching rate with the search word is equal to or greater than a predetermined level, from the external information saved in the information DB. An extracted information output unit displays the external information extracted by the external information extraction unit on a display.
Abstract: Provided are a storage system and a storage control method wherein, when communication is disabled (communication via a data communication path is disabled) in spite of replacement of a second CTL among a first CTL and the second CTL that are redundant storage controllers and that are coupled via the data communication path, the first CTL executes a write process of writing dirty data and data management information to one or more storage devices while maintaining acceptance of I/O requests from a host. The replaced second CTL reads the data management information from the one or more storage devices. The first CTL stops accepting I/O requests from the host. The replaced second CTL starts accepting I/O requests from the host.
Abstract: An industrial control system with communication bar and power bar is provided. The industrial control system comprises a plurality of I/O modules; a plurality of terminal boards; at least one communication bar having an input connected with a controller and a plurality of output interfaces, wherein each output interface connects with one I/O module or one terminal board; at least one power bar having an input connected with power supply and a plurality of output interfaces, wherein each output interface connects with one I/O module or one terminal board; wherein each I/O module communicates with one corresponding terminal board through the communication bar respectively.
Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.
Type:
Grant
Filed:
December 29, 2017
Date of Patent:
December 29, 2020
Assignee:
Intel Corporation
Inventors:
Mariusz Barczak, Dhruvil Shah, Kapil Karkra, Andrzej Jakowski, Piotr Wysocki
Abstract: Systems and methods for providing a continuous uptime of guest Virtual Machines (“VMs”) during upgrade of a virtualization host device. The methods comprising: connecting all of the guest VMs' frontends or drivers to at least one old control VM which is currently running on the virtualization host device and which contains old virtualization software; creating at least one upgraded control VM that contains new virtualization software and that is to replace the old VM in the virtualization host device; connecting the guest VMs' frontends or drivers to the upgraded VM; and uninstalling the old control VM from the virtualization host device.
Abstract: Disclosed are aspects of communication between user-space and kernel-space. In some examples, an application programming interface (API) signature is defined for an API. The API signature specifies a callback and a callback parameter size. A transport allocates temporary storage based on the callback parameter size specified by the API signature. A callback parameter is stored in the temporary storage. The callback is invoked based on the callback parameter.
Abstract: Systems and methods are described to monitor and record user context and engagement with music. In an exemplary method, a user device receives an audio input of a user's audio environment, for example through a microphone. From the audio input, a song playing in the user's audio environment is identified by a user device. This may be done by consulting a database of audio features. The user device determines the user context and/or a user's level of engagement with the song. The context may include the time and location at which the song was playing. The level of engagement may be determined by monitoring whether, for example, the user danced or otherwise moved to the song, whether the user sang along to the song, and/or whether the user turned up the volume of the song.
Abstract: Disclosed herein are systems and techniques for adaptive use of multiple power supplies in a communication system. For example, in some embodiments, a slave device may include: an upstream transceiver to couple to an upstream link of a bus of a communication system; and circuitry to couple to the upstream link of the bus and to a local power supply, wherein the circuitry is to switch from providing the local power supply to power the slave device to providing bus power supplied by the upstream link of the bus to power the slave device.
Type:
Grant
Filed:
June 27, 2018
Date of Patent:
December 1, 2020
Assignee:
Analog Devices Global Unlimited Company
Inventors:
Stuart Patterson, Martin Kessler, Prashant Tripathi
Abstract: A storage controller is provided with an optical circuit switch (OCS) for managing active-passive backend storage arrays. For this purpose a system includes a host computer system, a backend storage array having a first controller and a second controller, an optical circuit switch (OCS) connected between the host computer system and the first and second controllers, and a storage system controller comprising a failover detector to detect a failover of the first controller when the first controller is in an active state and the second controller is in a passive state, and an OCS controller to control the OCS to switch connection of the host computer system from the first controller to the second controller based on the failover detector detecting a failover of the first controller to place the second controller in an active state.
Type:
Grant
Filed:
July 24, 2018
Date of Patent:
November 10, 2020
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Grzegorz P. Szczepanik, Lukasz Jakub Palus, Kushal Patel, Sarvesh Patel
Abstract: Techniques are disclosed for managing access to shared computing resources in a computing system which include representing resources as objects and managing access to those objects using the construct of a resource instance manager. A set of resource instance managers responds to all commands requesting access to a set of respective shared resources. Access to each shared resource is managed by a unique resource instance manager for that resource which maintains a consistent state for that shared resource. Each resource instance manager determines, in response to receiving requests to allow execution of commands and using a set of predefined rues, whether those commands may be safely executed concurrently with other commands acting on the same shared resource. If the commands cannot be executed concurrently, the resource instance managers change the order in which queued commands are executed or abort execution of one or more commands.
Type:
Grant
Filed:
July 28, 2017
Date of Patent:
November 10, 2020
Assignee:
EMC IP Holding Company LLC
Inventors:
Amitava Roy, Shyamsunder Singaraju, Norman Speciner, Lorenzo Bailey, Robert Andrew Foulks, Rajesh Kumar Gandhi, Daniel S. Keefe
Abstract: A fair scheduling system with methodology for scheduling queries for execution by a database management system in a fair manner. The system obtains query jobs for execution by the database management system and cost estimates to execute the query jobs. Based on the cost estimates, the system causes the database management system to execute the query jobs as separate sub-query tasks in a round-robin fashion. By doing so, the execution latency of low cost query jobs that return few results is reduced when the query jobs are concurrently executed with high cost query jobs that return many results.
Type:
Grant
Filed:
June 27, 2017
Date of Patent:
October 27, 2020
Assignee:
Palantir Technologies Inc.
Inventors:
Michael Harris, John Carrino, Eric Wong
Abstract: A switching device, a Peripheral Component Interconnect Express (PCIe) system, and a switching system, where the switching system includes a first switching device and a second switching device. The first switching device and the second switching device are coupled using a network. The first switching device includes a plurality of PCIe upstream ports configured to connect to at least one host, the second switching device comprises at least one PCIe downstream port configured to connect to at least one input/output (I/O) device, and the second switching device is configured to receive a first data packet from the first switching device using the network, convert the first data packet to a second data packet complying with a PCIe protocol, and transmit the second data packet to a target I/O device of the second data packet.
Abstract: Techniques for processing I/O operations may include: detecting, at a host, a sequence of I/O operations to be sent from the host to a data storage system, wherein each of the I/O operations of the sequence specifies a target address included in a first logical address subrange of a first logical device; sending, from the host, the sequence of I/O operations to a same target port of the data storage system, wherein each of the I/O operations of the sequence includes an indicator denoting whether resources used by the same target port in connection with processing said each I/O operation are to be released subsequent to completing processing of said each I/O operation; receiving the sequence of I/O operations at the same target port of the data storage system; and processing the sequence of I/O operations.
Type:
Grant
Filed:
August 2, 2019
Date of Patent:
October 13, 2020
Assignee:
EMC IP Holding Company LLC
Inventors:
Jaeyoo Jung, Ramesh Doddaiah, Owen Martin, Arieh Don
Abstract: A client device for accessing remote storage devices. The client device includes: a processing unit communicatively connected to: a network interface and a memory; the network interface configured to communicatively connect the client device to a network comprising the client device and a storage server, the storage server comprising one or more storage devices, a remote direct memory access network interface controller (rNIC), and a primary processing unit; the memory containing instructions, that, when executed by the processing unit, configure the client device to: send an input/output (I/O) request for a storage device of the one or more storage devices; receive an indication from the rNIC based on the sent I/O request, the indication including an interrupt generated by the rNIC in response to the I/O request.
Abstract: An apparatus, system, and method to manage communications within a network, such as a wireless network and/or at least partially included within a hazardous area, includes creating a master CRC array from master configuration structures, creating a main master CRC value from the master CRC array, receiving a main slave CRC value, and determining if the main master CRC value and the main slave CRC value are different.
Type:
Grant
Filed:
March 12, 2014
Date of Patent:
September 22, 2020
Assignee:
Sensia LLC
Inventors:
Thomas M. Madden, Robert Diederichs, Jerry Yee
Abstract: A method for handling network I/O device virtualization is provided. The method comprises, translating, by a virtual machine monitor, a guest physical address of a virtual machine to a host physical address in response to an I/O request from at least one virtual machine among a plurality of virtual machines, transmitting, by a virtual machine emulator, an instruction request including the translated address information to an extended device driver associated with the virtual machine from which the I/O request is forwarded, inserting, by the extended device driver, the translated address into a transmission queue, and performing a direct memory access for the I/O request using a physical I/O device according to the transmission queue.
Abstract: There is provided a communication apparatus, including: a transmission/reception unit that transmits/receives a signal to/from a different apparatus; a confirmation signal detection unit that detects one of a reception confirmation signal and a non-reception confirmation signal, the reception confirmation signal and the non-reception confirmation signal being transmitted from the different apparatus that has received the signal transmitted from the transmission/reception unit; and a conflict avoiding unit that instructs the transmission/reception unit to transmit an abort signal for instructing to interrupt communication after ignoring a predetermined number of bits following the non-reception confirmation signal when the confirmation signal detection unit has detected the non-reception confirmation signal.
Abstract: Power loss in a client device is detected. In response to the detecting of the power loss, an electronic card is alerted that the power loss is about to occur, where the electronic card includes a volatile storage and a non-volatile storage. A transfer of data from the volatile storage to the non-volatile storage is triggered in response to the alert.
Type:
Grant
Filed:
August 5, 2019
Date of Patent:
July 21, 2020
Assignee:
Hewlett-Packard Development Company, L.P.
Inventors:
Byron A. Alcorn, Scott W. Briggs, Joel Pierre Lefebvre
Abstract: A portable terminal includes: a display; a user interface; a memory; a network interface; and a controller, the controller performs performing a deciding processing of deciding the display mode of instructions objects corresponding to the external instructions specified in the first specifying processing, based on attribute information; performing a display control processing of controlling the display to display a selection screen including instructions objects having the display mode decided in the deciding processing; performing a first receiving processing of receiving a user operation of selecting an object included in the selection screen, via the user interface; performing, in response to the operation of selecting a instructions object in the first receiving processing, an activation processing of activating an external instructions corresponding to the selected object; performing an designation information acquiring processing of acquiring designation information from the external instructions activa
Abstract: Certain aspects of the present disclosure provide an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.
Type:
Grant
Filed:
February 18, 2019
Date of Patent:
May 19, 2020
Assignee:
QUALCOMM Incorporated
Inventors:
Punit Kishore, Jais Abraham, Pawan Chhabra
Abstract: According to one general aspect, an apparatus may include a first cache configured to store data. The apparatus may include a second cache configured to, in response to a fill request, supply the first cache with data, and an incoming fill signal. The apparatus may also include an execution circuit configured to, via a load request, retrieve data from the first cache. The first cache may be configured to: derive, from the incoming fill signal, address and timing information associated with the fill request, and based, at least partially, upon the address and timing information, schedule the load request to attempt to avoid a load-fill conflict.
Abstract: An apparatus and method are described for performing virtualization using virtual machine (VM) sets. For example, one embodiment of an apparatus comprises: graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; a hypervisor to virtualize the GPU to share the GPU among a plurality of virtual machines (VMs); and VM set management logic to establish a plurality of VM sets, each set comprising a plurality of VMs, the VM set management logic to partition graphics memory address (GMADR) space across each of the VM sets but to share the GMADR space between VMs within each VM set.
Abstract: A method, device and computer program product for enabling a Single Root Input/Output Virtualization (SR-IOV) function in an endpoint device. The method comprises: receiving, at an adapter, a request message from a virtual machine, the request message indicating an operation to be performed on the endpoint device by the virtual machine; parsing the request message to obtain a first request Transaction Layer Packet (TLP); determining whether a type of a first request TLP is a peer-to-peer transmission supported TLP or a peer-to-peer transmission unsupported TLP; in response to determining that the type of the first request TLP is a peer-to-peer transmission supported TLP, generating a second request TLP based on the first request TLP; and sending the second request TLP to the endpoint device. With this solution, the SR-IOV function is enabled in the endpoint device which does not support the SR-IOV function without the need of changing the endpoint device.
Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.
Type:
Grant
Filed:
December 5, 2018
Date of Patent:
April 14, 2020
Assignee:
Apple Inc.
Inventors:
Stephan G. Meier, Tyler J. Huberty, Gerard R. Williams, III, Pradeep Kanapathipillai
Abstract: The saving of data in an information technology (IT) infrastructure offering activity resumption functions is disclosed. For these purposes, a saving system is provided with at least one first and one second sets of data storage and at least one first and one second memory controllers associated with the first and second data storage, respectively. The saving system is furthermore provided with a microcontroller configured to duplicate a stream of commands and of data destined for the first memory controller to the second memory controller in a mode of normal use allowing a local replication of data in the second set of data storage and to address a distinct stream of commands and of data to each of the first and second memory controllers in a mode of remote replication.
Type:
Grant
Filed:
May 1, 2014
Date of Patent:
March 31, 2020
Assignee:
BULL SAS
Inventors:
Jean-Olivier Gerphagnon, Corine Marchand, Philippe Lachamp
Abstract: A PCIe (Peripheral Component Interconnect Express) protocol converter for connection to a central processing unit (CPU) node having a root complex, a CPU memory fabric and CPU memory may include independent PCIe links, a fabric interface and a fabric switch connected to the fabric interface. Each of the links may include an endpoint for connection to the root complex. The fabric switch is connected to the fabric interface of each of the links and is connectable to a remote node. The fabric switch transmits writes of a single write request from the remote node across both links. Each fabric interface is to transmit an acknowledgment to the remote node in response to a write of the writes becoming observable at the CPU node hi Michael, hi Michael,.
Type:
Grant
Filed:
September 18, 2018
Date of Patent:
March 24, 2020
Assignee:
Hewlett Packard Enterprise Development LP
Inventors:
Shawn K. Walker, Derek A. Sherlock, Gary Gostin
Abstract: A secure and fault-tolerant, or variation-tolerant, method and system to turn a set of N shares into an identifier even when only M shares from this set have a correct value. A secret sharing algorithm is used to generate a number of candidate identifiers from subsets of shares associated with asset parameters of a collection of assets. The most frequently occurring candidate identifier is then determined to be the final identifier. The method has particular applicability in the fields of node locking and fingerprinting.
Type:
Grant
Filed:
November 9, 2018
Date of Patent:
March 24, 2020
Assignee:
IRDETO B.V.
Inventors:
Phillip Alan Eisen, Michael James Wiener, Grant Stewart Goodes, James Muir
Abstract: A method for controlling bus-networked devices is useable in a system comprising a gateway, an open field bus electrically connected to the gateway, and a pluggable connection cable electrically connecting the gateway to a plurality of bus subscribers. The gateway starts a configuration mode to control a bus subscriber and to generate a new target configuration including the bus subscriber. According to an initial target configuration, the bus subscriber is not expected by the gateway.
Abstract: A gaming system and processor module are therefore adapted to support simultaneous execution of two or more operating system instances. Program code is provided for play of the game uses two or more cooperating component processes partitioned such that at least one of the component processes executes using a first operating system instance, and at least one other cooperating component process executes using a further operating system instance. Each operating system instance may execute in its own virtual machine.
Type:
Grant
Filed:
August 12, 2015
Date of Patent:
March 17, 2020
Assignee:
ARISTOCRAT TECHNOLOGIES AUSTRALIA PTY LIMITED
Abstract: A method is provided for increasing throughput in a distributed storage network (DSN). A storage unit (SU) of the DSN receives a set of access requests regarding a set of encoded data slices and determines whether processing one or more access requests from the set of access requests can be delayed. Based on performance information regarding the one or more access requests the SU queues the requests and delays the processing of the requests in order to achieve higher throughput.
Type:
Grant
Filed:
February 16, 2017
Date of Patent:
March 3, 2020
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Andrew D. Baptist, Greg R. Dhuse, Manish Motwani, Jason K. Resch, Praveen Viraraghavan, Ilya Volvovski, Ethan S. Wozniak
Abstract: An apparatus, method, system, and program product are disclosed for mirroring resynchronization. In one example, an apparatus includes a mirroring status determination module that detects suspension of mirroring. The apparatus, in a further embodiment, includes a suspension determination module that determines a first change in at least one parameter that resulted in the detected suspension of mirroring. In various embodiment, the apparatus includes a parameter detection module that detects a second change in the at least one parameter that enables resuming minoring. In some embodiments, the parameter detection module detects the first change in the at least one parameter. In one embodiment, the apparatus includes a synchronization module that resumes minoring in response to the parameter detection module detecting the second change.
Type:
Grant
Filed:
October 12, 2015
Date of Patent:
March 3, 2020
Assignee:
International Business Machines Corporation
Inventors:
Dash D. Miller, Miguel A. Perez, David C. Reed, Max D. Smith
Abstract: Embodiments of the present disclosure generally relate to managing phys of a data storage target device. In one embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device across a link reset includes transmitting a common target phy address for a plurality of target phys during a first link reset, storing the common target phy address in a non-volatile memory of the data storage device, resetting the target phys, and transmitting the stored common target phy address for the plurality of target phys during a second link reset. In another embodiment, a method of automatically managing phys of a data storage target device by a controller of the data storage device includes matching a received host address for a plurality of target phys and configuring the plurality of target phys into a wide port for the plurality of target phys with the matched received host address.
Type:
Grant
Filed:
May 19, 2017
Date of Patent:
February 18, 2020
Assignee:
WESTERN DIGITAL TECHNOLOGIES, INC.
Inventors:
Darin Edward Gerhart, Nicholas Edward Ortmeier, Xin Chen
Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.
Type:
Grant
Filed:
August 29, 2017
Date of Patent:
February 18, 2020
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Veronica S. Davila, Trung N. Nguyen, Louis A. Rasor
Abstract: A computer-executable method, system, and computer program product for managing a Parallel-Logged File System (PLFS) on a data storage system, wherein the data storage system is in communication with an application that updates the data storage system with checkpoint data, the computer-executable method, system, and computer program product comprising receiving a first checkpoint including data from the application; analyzing the data in the first checkpoint to determine whether a pattern exists in the checkpoint data; and upon a positive determination, adding the pattern into PLFS.
Type:
Grant
Filed:
September 30, 2013
Date of Patent:
February 11, 2020
Assignees:
EMC IP Holding Company LLC, Triad National Security, LLC
Inventors:
John M. Bent, Sorin Faibish, Zhenhua Zhang, Jun He, Aaron Torres, Gary Grider
Abstract: A method includes an interconnect performing a partial direct memory access of a packet to obtain packet header data of a packet header, using the packet header data to generate a packet forwarding decision identifying a packet destination address, and initiating a direct memory access of a packet payload to the packet destination address.
Abstract: Techniques for inter-host communication may include issuing a first message from a first host; and sending the first message from the first host to a second host. Sending the first message may include transmitting the first message indirectly to the second host over a first connection between a first data storage system and a second data storage system. The first connection may be used in connection with data replication to maintain a first device of the first data storage system and a second device of the second data storage system as synchronous mirrored copies of a first logical device. Multiple logical devices configured for synchronous replication may be used for inter-host communication. Alternatively, a single logical device configured for synchronous replication may be used for inter-host communication.
Abstract: According to non-limiting embodiments disclosed herein, the functionality of an object cache in a server can be extended to monitor and track web traffic, and in particular to perform rate accounting on selected web traffic. As the server communicates with clients (e.g., receiving HTTP requests and responding to those requests), the server can use its existing object cache storage and existing object cache services to monitor web traffic by recording how often a client makes a particular request in the object cache and/or other data about the requests. Preferably, the object cache is still used for conventional caching of objects, the object cache thus providing a dual role by storing both web objects and rate accounting data.
Abstract: Methods, systems and an apparatus for an embedded web server in a data acquisition device to facilitate access to data acquired by the data acquisition device by one or more web-enabled devices. The embedded web server packages the data for enhanced access by the client over two or more communication pathways using standard data communication protocols and without disrupting the operation of the data acquisition device in which the web server is embedded.
Type:
Grant
Filed:
April 8, 2016
Date of Patent:
January 7, 2020
Assignee:
OMRON Corporation
Inventors:
Joseph J. Dziezanowski, Serge Limondin, Erik S. Lewerenz, Matthew Van Bogart
Abstract: Servicing I/O operations directed to a dataset that is synchronized across a plurality of storage systems, including: receiving, by a follower storage system, a request to modify the dataset; sending, from the follower storage system to a leader storage system, a logical description of the modification to the dataset; receiving, from the leader storage system, information describing the modification to the dataset; processing, by the follower storage system, the request to modify the dataset; receiving, from the leader storage system, an indication that the leader storage system has processed the request to modify the dataset; and acknowledging, by the follower storage system, completion of the request to modify the dataset.
Type:
Grant
Filed:
August 8, 2017
Date of Patent:
December 31, 2019
Assignee:
Pure Storage, Inc.
Inventors:
Deepak Chawla, David Grunwald, Steven Hodgson, Tabriz Holtz, Ronald Karr
Abstract: A first I/O controller of a storage server sends a first command to a first solid state drive (SSD) of the storage server via a first submission queue of the first SSD, wherein the first command is a first read command or a first write command. The first I/O controller receives a first acknowledgement from the first SSD that the first command has been completed via a first completion queue of the first SSD. A second I/O controller of the storage server sends a second command to the first SSD of the storage server via a second submission queue of the first SSD, wherein the second command is a second read command or a second write command. The second I/O controller receives a second acknowledgement from the first SSD that the second command has been completed via a second completion queue of the first SSD.
Abstract: According to an embodiment of the present invention, a global node system architecture that is specific to a read many and write infrequently application comprising: a plurality of global nodes distributed throughout a global region, each global node comprises: a memory that stores a set of data that is replicated at each node of the plurality of global nodes where each node is a self-contained node so that each node of the plurality of global nodes comprises an exact replica of data; and a processor coupled to the memory and programmed to: synchronize data updates at each of the plurality of global nodes; automatically detect a nearest global node with respect to each of the plurality of global nodes; and initiating a communication with the nearest global node.
Type:
Grant
Filed:
December 24, 2015
Date of Patent:
December 10, 2019
Assignee:
JPMorgan Chase Bank, N.A.
Inventors:
Hirenkumar Patel, David Woodstrom, Bret Goldsmith
Abstract: Systems and methods for managing coherency in a processing system comprising a memory involve one or more aperture cache coherency (ACC) blocks. The ACC blocks monitor accesses to the memory using aliased addresses, wherein the aliased addresses map to locations in an aliased address domain of the memory. The ACC blocks also monitor accesses to the memory through a functional address aperture using aperture addresses, wherein a function of the aperture addresses map to locations in an aperture address domain of the memory. The ACC blocks are further configured to maintain coherency between one or more of data in a first location of the memory, the first location belonging to the aliased address domain and the aperture address domain; one or more copies of the data accessed using the aperture addresses; or one or more copies of the data accessed using the aliased addresses.
Type:
Grant
Filed:
July 11, 2018
Date of Patent:
December 10, 2019
Assignee:
Qualcomm Incorporated
Inventors:
Bohuslav Rychlik, Wesley James Holland, Hao Liu, Andrew Edmund Turner
Abstract: Storage group performance targets are achieved by managing resources using discrete techniques that are selected based on learned cost-benefit rank. The techniques include delaying start of IOs based on storage group association, making a storage group active or passive on a port, and biasing front end cores. A performance goal may be assigned to each storage group based on volume of IOs and the difference between an observed response time and a target response time. A decision tree is used to select a correction technique which is biased based on the cost of deployment. The decision tree maintains an average benefit of each technique and over time with rankings based on maximizing cost-benefit.
Type:
Grant
Filed:
March 16, 2016
Date of Patent:
December 3, 2019
Assignee:
EMC IP HOLDING COMPANY LLC
Inventors:
Owen Martin, Arieh Don, Michael Scharland
Abstract: In an example embodiment, a Software Defined Networking (SDN) application identifies a domain based on a destination address of a packet that is associated with a primary service. The domain corresponds to the primary service, and the primary service is configured to trigger one or more support flows from one or more ancillary services. The SDN application identifies the one or more support flows based on the domain, and generates one or more rules for distribution to one or more network elements that handle packets of the one or more support flows from the one or more ancillary services.
Type:
Grant
Filed:
June 30, 2017
Date of Patent:
November 26, 2019
Assignee:
Cisco Technology, Inc.
Inventors:
Mario Baldi, Han Hee Song, Antonio Nucci, Marco Mellia, Martino Trevisan, Idilio Drago
Abstract: A port is dynamically added to and removed from a virtual switch. The new port may be allocated when there is sufficient free memory in a pool of memory associated with the virtual switch. When an existing port is deallocated, the portion of the pool of memory allocated to that existing port is freed up. As a result, a virtual machine that requires one or more ports on the virtual switch may be provisioned on a host so long as the pool of memory is sized properly and memory usage on the host is not excessive.
Type:
Grant
Filed:
March 31, 2014
Date of Patent:
November 19, 2019
Assignee:
VMware, Inc.
Inventors:
Santhosh Sundararaman, Jia Yu, Mark Pariente, Ganesan Chandrashekhar