Decentralized Arbitrating Patents (Class 710/242)
  • Patent number: 10505860
    Abstract: A scheduling system includes a request masking circuit configured to receive a plurality of original requests for priority arbitration among a plurality of entries, the plurality of original requests include a last original request and a first original request following the last original request. A last mask associated with a last grant result for the last original request is received from a mask generator circuit. A first masked request is generated by applying the last mask to the first original request. A request selection circuit is configured to generate a first selected request based on the first original request and the first masked request. The mask generator circuit is configured to generate a first mask based on the first selected request. The first mask is associated with a first grant result for the first original request.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 10, 2019
    Assignee: XILINX, INC.
    Inventors: Chuan Cheng Pan, Kiran S. Puranik
  • Patent number: 10459773
    Abstract: The PLD management system includes a PLD management unit that manages the usage status of each of one or more PLDs. The PLD management unit receives a PLD usage request from a request source module which is one of a plurality of processing modules sharing each of the one or more PLDs. when the PLD management unit receives the usage request, the PLD management unit performs control to prevent two or more processing modules including the request source module from utilizing the same PLD at the same time based on a current usage status of a PLD corresponding to the usage request and content of the usage request.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: October 29, 2019
    Assignee: HITACHI, LTD.
    Inventors: Mitsuhiro Okada, Akifumi Suzuki, Takayuki Suzuki, Yuichiro Aoki, Naoya Nishio
  • Patent number: 10296388
    Abstract: A method, system and computer program product for optimally allocating objects in a virtual machine environment implemented on a NUMA computer system. The method includes: obtaining a node identifier; storing the node identifier in a thread; obtaining an object identifier of a lock-target object from a lock thread; writing a lock node identifier into the lock-target object; traversing an object reference graph where the object reference graph contains an object as a graph node, a reference from the first object to a second object as an edge, and a stack allocated to a thread as the root node; determining whether a move-target object contains the lock node identifier; moving the move-target object to a subarea allocated to a lock node if it contains the lock node identifier, and moving the move-target object to the destination of the current traversal target object if the lock node identifier is not found.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Takeshi Ogasawara
  • Patent number: 10205545
    Abstract: The present document discloses a method and apparatus for creating a resource. In the above method, receiving a resource creation request from a transmitting end, herein information carried in the resource creation request carries resource creation information corresponding to a resource to be created; and determining whether a first resource name needs to be reallocated to the resource to be created and creating the resource to be created according to the resource creation information. According to the technical solutions provided by the present document, the management of resource names by a CSE is enhanced, and the uniqueness of the resource names is ensured, consequently the application scenarios of an M2M service provider are expanded, and at the same time the duplicated registration of the same resources is avoided.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: February 12, 2019
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD
    Inventor: Hao Wu
  • Patent number: 10127171
    Abstract: A circuit arrangement, network-on-chip, and a method for transmitting information are disclosed. In one embodiment, an electrical circuit is provided comprising a plurality of circuit blocks comprising a first circuit block, a second circuit block, and a third circuit block, and a connection structure coupled to the plurality of circuit blocks, wherein the first circuit block is configured to send a request comprising information corresponding to the request and an address onto the connection structure, wherein the second circuit block is configured to initiate a transmission onto the connection structure in response to receiving the request, and wherein the third circuit block is configured to receive the transmission and wherein the address is assigned to the third circuit block.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Helmut Reinig, Soeren Sonntag
  • Patent number: 9928142
    Abstract: Systems, methods, and computer program products to perform an operation comprising determining, by a processor, a process identifier of a process associated with a page fault based on an interrupt source number, wherein the page fault was triggered by a coherent accelerator, executing the process on the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vishal C. Aslot, Bruce Mealey, Mark D. Rogers, Randal C. Swanberg
  • Patent number: 9830675
    Abstract: An image-processing apparatus includes a memory in which first image data is recorded, wherein the first image data includes second image data an offset-calculating block configured to calculate an offset when transfer data is read for each row, wherein an amount of position gap between a storage area of data of a first row of the first image data and a storage area of data of a second row includes the offset and wherein the access boundary is a boundary of data capable of being accessed through one access to the memory, a write block configured to write the first image data, a write control block configured to control the write block, a read block configured to read the second image data, a read control block configured to control the read block, and an image-processing block configured to perform image processing on the second image data.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 28, 2017
    Assignee: OLYMPUS CORPORATION
    Inventor: Kazue Chida
  • Patent number: 9660936
    Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: May 23, 2017
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Riccardo Locatelli, Michael Soulie, Francesco Giotta, Raffaele Guarrasi, Giuseppe Guarnaccia
  • Patent number: 9542236
    Abstract: Techniques are disclosed for efficiently sequencing operations performed in multiple threads of execution in a computer system. In one set of embodiments, sequencing is performed by receiving an instruction to advance a designated next ticket value, incrementing the designated next ticket value in response to receiving the instruction, searching a waiters list of tickets for an element having the designated next ticket value, wherein searching does not require searching the entire waiters list, and the waiters list is in a sorted order based on the values of the tickets, and removing the element having the designated next ticket value from the list using a single atomic operation. The element may be removed by setting a waiters list head element, in a single atomic operation, to refer to an element in the list having a value based upon the designated next ticket value.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 10, 2017
    Assignee: Oracle International Corporation
    Inventor: Oleksandr Otenko
  • Patent number: 9336169
    Abstract: Techniques are disclosed to provide arbitration between input ports and output ports of a switch. For each of at least one input port of a group of input ports, a respective request is received specifying for the respective input port to be allocated a clock cycle in which to send data to a group of output ports. A grant of the request of a primary input port is issued at each clock cycle, the primary input port including a first input port of the at least one input port. Upon a determination, subsequent to a first clock cycle count elapsing, that an input arbiter has not yet accepted any grant of the request of the primary input port, a grant is issued at each clock cycle, including alternating between issuing a grant of the request of the primary input port and of an alternate input port, respectively.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Vibhor K. Srivastava, Brian T. Vanderpool
  • Patent number: 9323703
    Abstract: Techniques are disclosed to provide arbitration between input ports and output ports of a switch. For each of at least one input port of a group of input ports, a respective request is received specifying for the respective input port to be allocated a clock cycle in which to send data to a group of output ports. A grant of the request of a primary input port is issued at each clock cycle, the primary input port including a first input port of the at least one input port. Upon a determination, subsequent to a first clock cycle count elapsing, that an input arbiter has not yet accepted any grant of the request of the primary input port, a grant is issued at each clock cycle, including alternating between issuing a grant of the request of the primary input port and of an alternate input port, respectively.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Vibhor K. Srivastava, Brian T. Vanderpool
  • Patent number: 9172613
    Abstract: In a multiple interface, low power and lossy network comprising a plurality of nodes, a low transmission power and medium transmission power topology are defined for the network and a channel-hopping schedule is defined for the devices operating in each topology. A sender determines that data is capable of being transmitted via a link on the low transmission power topology. The sender determines the transmission parameters for the transmission of the data over the link on the low transmission power topology and determines a low transmission power channel for transmission of the data. The sender transmits the determined channel and the transmission parameters to the receiver. The sender transmits the data via the determined channel in the low transmission power topology.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 27, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Jonathan W. Hui, Jean-Philippe Vasseur, Wei Hong
  • Patent number: 8984194
    Abstract: The present invention discloses an arbitration mechanism for controlling access of a plurality of nodes external to a shared resource, to which accesses by the number of nodes must be restricted, is applicable to any shared source in a computer or computer-controlled system. The present design delivers the following advantageous features. It provides localized arbitration to obtain resource access and localized self-management of resource mastery; eliminates resource seizure locally; it allows equal access to the share resource, encapsulate all four above features with the same circuit/protocol.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: March 17, 2015
    Assignee: Numia Medical Technology LLC
    Inventors: Duane E. Allen, James Jay Allen
  • Patent number: 8965947
    Abstract: A control and communication system including a number of automation units which are adapted to process signals in function plans within the automation unit and which are connected in the same level to a common communication bus for providing a peer-to-peer communication between the automation units, further includes an engineering unit being connected to the communication bus and being adapted to provide functions allowing at least one automation unit to exchange signals to a function plan which is attributed to another automation unit.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: February 24, 2015
    Assignee: Siemens Aktiengesellschaft
    Inventors: Andreas Drebinger, Jochen Zingraf
  • Patent number: 8938559
    Abstract: Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: January 20, 2015
    Assignee: National Instruments Corporation
    Inventors: Sundeep Chandhoke, Jason D. Tongen
  • Patent number: 8892801
    Abstract: Arbitration circuitry for arbitrating between a plurality W of requests R for access to a shared resource. Included are state bits storage storing I state bits Q and generating 2I output bits comprising the true and compliment values of each stored state bit and routing circuitry for generating a set of mask signals M from the output bits. Grant circuitry receives the set of mask signals and the plurality of requests, and grants access to the shared resource to an asserted request having regard to the priority ordering encoded by the set of mask signals. State bit update circuitry is responsive to a trigger condition to perform an update causing a change in the priority ordering encoded by the set of mask signals. The routing circuitry provides a pattern of connections such that each mask signal in the set is directly connected to one of said output bits.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: November 18, 2014
    Assignee: ARM Limited
    Inventor: Andrew David Tune
  • Patent number: 8819323
    Abstract: A port A request queue is configured with a port AQ0 to a port AQn for each of request types Q0 to Qn connected with a requester resource busy flag controller Q0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ0 to turn a busy flag on when it is determined that a data request from the port AQ0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ0 inhibits output of a data request as long as the busy flag is on.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Limited
    Inventor: Masaru Nishiyashiki
  • Patent number: 8793421
    Abstract: Techniques are disclosed relating to request arbitration between a plurality of master circuits and a plurality of target circuits. In one embodiment, an apparatus includes an arbitration unit coupled to a plurality of request queues for a target circuit. Each request queue is configured to store requests generated by a respective one of a plurality of master circuits. The arbitration unit is configured to arbitrate between requests in the plurality of request queues based on information indicative of an ordering in which requests were submitted to the plurality of request queues by master circuits. In some embodiments, each of the plurality of master circuits are configured to submit, with each request to the target circuit, an indication specifying that a request has been submitted, and the arbitration unit is configured to determine the ordering in which requested were submitted based on the submitted indications.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 29, 2014
    Assignee: Apple Inc.
    Inventors: William V. Miller, Chameera R. Fernando
  • Patent number: 8769176
    Abstract: A system including a first communication module to transmit or receive data via an antenna in accordance with a first communication standard; a second communication module to transmit or receive data via the antenna in accordance with a second communication standard; and an arbitration module. The arbitration module outputs a first mutual grant where both the first communication module and the second communication module are able to simultaneously transmit data via the antenna; a second mutual grant where both the first communication module and the second communication module are able to simultaneously receive data via the antenna; a third mutual grant where the first communication module and the second communication module are able to simultaneously transmit and receive data, respectively, via the antenna; and a fourth mutual grant where the first communication module and the second communication module are able to simultaneously receive and transmit data, respectively, via the antenna.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Marvell International Ltd.
    Inventors: Gladys Yuen Yan Wong, Timothy J. Donovan, Timothy Li, Ken Yeung
  • Patent number: 8688881
    Abstract: An integrated circuit device (100) comprising a first plurality of components (102-112), a second plurality of buses (114-124, 140, 142) for transmitting transaction requests from said components (102-112) to a resource (138) shared by said components (102-112) and a third plurality of arbiters (132-136) arranged in at least two levels of arbitration. Each transaction request has attached priority value that is used by the arbiters to determine which of the components should be granted access to the resource (138).
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: April 1, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Rowan Nigel Naylor
  • Patent number: 8619554
    Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: December 31, 2013
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Robin Hotchkiss
  • Patent number: 8612990
    Abstract: A storage system may include a set of storage devices; a controller; and a management device. The controller may arbitrate among operations for execution by the set of storage devices, where the operations are received from users that are associated with priority levels. The controller may maintain queues, corresponding to the users, to queue operations from the users. The controller may additionally include a scoring component and a scheduler. The scoring component may maintain a score for each queue. The scheduler may choose, from the queues and based on the score of each queue, one of the operations to service. The management device may receive usage updates, from the controller, reflecting usage of the set of storage devices; calculate a maximum allowed usage levels, based on the received usage updates, for each user; and transmit the calculated maximum usage levels to the controller.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 17, 2013
    Assignee: Google Inc.
    Inventors: Lawrence E. Greenfield, Alexander Khesin
  • Patent number: 8612713
    Abstract: Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: December 17, 2013
    Assignee: Electronics & Telecommunications Research Institute
    Inventors: Bup Joong Kim, Woo Young Choi, Kook Jin Nam, Byung Jun Ahn
  • Patent number: 8543750
    Abstract: A method is provided for interfacing a plurality of processing components with a shared resource component. A token signal path is provided to allow propagation of a token through the processing components, wherein possession of the token by a given processing component enables the latter to conduct a transaction with the shared resource component. Token processing logic is also provided for propagating the token from one processing component to another along the token signal path, the propagating being done at a propagation rate that is related to a transaction rate associated with the shared resource component. The token processing logic also generates a trigger signal at least in part based on the token and propagates to trigger signal to the shared resource component to convey initiation of a transaction with the shared resource component.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: September 24, 2013
    Assignee: Octasic Inc.
    Inventors: Tom Awad, Martin Laurence, Martin Filteau, Pascal Gervais, Douglas Morrissey
  • Patent number: 8539130
    Abstract: The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: September 17, 2013
    Assignee: NVIDIA Corporation
    Inventors: David B. Glasco, Dane T. Mrazek, Samuel H. Duncan, Patrick R. Marchand, Ravi Kiran Manyam, Yin Fung Tang, John H. Edmondson
  • Patent number: 8495266
    Abstract: Various embodiments of the present invention are directed to a distributed lock and distributed locking protocol to allow multiple communicating entities to share access to a computing resource. Certain embodiments of the present invention employ a data storage register implemented by the communicating entities to hold a value reflective of a distributed lock state.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: July 23, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: James M. Reuter
  • Patent number: 8473661
    Abstract: A method and system for providing multi-process protection using direct memory mapped control registers is disclosed. According to one embodiment, a computer-implemented method provides a set of control registers for each execution unit of a plurality of execution units in a controller switch. The controller switch facilitates communication between a host system and one or more devices connected to a plurality of device ports of the controller switch. A device driver is provided to allow users' processes to access the controller switch and to grant exclusive access to each execution unit of the plurality of execution units. A first access request to access an execution unit of the plurality of execution units is received from a first process. A set of direct accessible addresses to the set of control registers of the execution unit is allocated, and the first process is granted to exclusive access the execution unit until the first process release the exclusive access to the execution unit.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: June 25, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ching-Ping Chou, Darren Kwan
  • Patent number: 8402186
    Abstract: In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventor: Sarathy Jayakumar
  • Publication number: 20130054856
    Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Inventors: Kie Woon Lim, E-Liang Chew, Khee Wooi Lee, Darren L. Abramson
  • Patent number: 8356128
    Abstract: A digital processing system employing multiple arbiters, all designed to allocate a resource to a same entity in response to a same condition. In an embodiment, the entities needing the resource may send a request to all the arbiters, and the specific entity to which the resource is allocated, receives indication of the allocation from a closest one of the arbiters. As a result, the latency in receipt of indication of allocation may be reduced. The features are described in the context of a bus as a resource.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: January 15, 2013
    Assignee: NVIDIA Corporation
    Inventor: Aditya Mittal
  • Patent number: 8352669
    Abstract: Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an Ni-input by Mi-output switch fabric, wherein Ni and Mi are positive integers greater than one. Each crossbar switch includes an input buffer at each input node, a crosspoint buffer at each crosspoint of the switch fabric, and an output buffer at each output node. The input buffer has an arbiter that reads data packets from the input buffer according to a first scheduling algorithm. An arbiter reads data packets from a crosspoint buffer queue according to a second scheduling algorithm. The output node receives segments of data packets provided from one or more corresponding crosspoint buffers.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: January 8, 2013
    Assignee: LSI Corporation
    Inventors: Ephrem Wu, Ting Zhou, Steven Pollock
  • Patent number: 8325715
    Abstract: An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: December 4, 2012
    Assignee: Futurewei Technologies, Inc.
    Inventors: William J. Dally, Philip P. Carvey, Larry R. Dennison, P. Allen King
  • Patent number: 8321872
    Abstract: Hardware resources sharing for a computer system running software tasks. A controller stores records including a mutex ID tag and a waiter flag in a cache. Lock and unlock registers are readable by the controller and loadable by the tasks with a mutex ID specifying a hardware resource. The controller monitors whether the lock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it sets the record's waiter flag. If not, it adds a record having a tag corresponding with the mutex ID. The controller also monitors whether the unlock register for loading with a mutex ID, and then determines whether it corresponds with the tag of a record in the cache. If so, it determines whether that record's waiter flag is set and, if so, it clears that record from the cache.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: November 27, 2012
    Assignee: Nvidia Corporation
    Inventor: James R. Terrell, II
  • Patent number: 8307147
    Abstract: A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: November 6, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ori Goren, Yaron Netanel
  • Patent number: 8274972
    Abstract: A communication system is provided, including a first master device to operate as a master of a communication according to a first protocol, a second master device to operate as a master of a communication according to a second protocol, a common slave device to operate as a slave of the communication according to the first protocol and the second protocol with respect to the first master device and the second master device, and a switch to control a connection between the common slave device and the first master device and between the common slave device and the second master device for a communication between the common slave device and one of the first master device to and the second master device. Thus, embodiments of the present invention provide a communication system that minimizes cost increases and improves communication speed in a system in which a plurality of master devices communicate with a slave device performing the same function as the master devices.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeong-kee Park
  • Patent number: 8244944
    Abstract: A wireless network device including an antenna, a first communication module, and a second communication module. The first communication module is configured to transmit or receive packets of data in accordance with a first communication standard, and the second communication module is configured to transmit or receive packets of data in accordance with a second communication standard. The wireless network device further includes an arbitration module configured to grant access of each of the first communication module and the second communication module to the antenna so that the first communication module and the second communication module can respectively transmit or receive data packets in accordance with the first communication protocol and the second communication protocol.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: August 14, 2012
    Assignee: Marvell International Ltd.
    Inventors: Gladys Yuen Yan Wong, Timothy J. Donovan, Timothy Li, Ken Yeung
  • Patent number: 8238911
    Abstract: Methods, apparatus, and computer-readable media for management and arbitration of dedicated mobile communication resources for mobile applications are provided. Mobile applications can be given a priority level that establishes an importance with respect to one or more other mobile applications and at least one mobile resource. If competing applications attempt to access the mobile resource concurrently, access can be provided to an application having higher priority level. Furthermore, control of a resource can be taken away from an application having lower priority in order to affect control of such resource for a higher priority application. In one aspect, a privilege code of an application can be verified prior to establishing control of the resource for the application, to mitigate a likelihood of inappropriate transfer of resources.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: August 7, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Tianyu Li D'Amore, Uppinder Singh Babbar, David C. Park, Srinivasan Balasubramanian
  • Patent number: 8209689
    Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Patent number: 8156273
    Abstract: A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: April 10, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christine E. Moran, Matthew D. Akers, Annette Pagan
  • Patent number: 8127063
    Abstract: A distributed process control equipment ownership arbitration system and method for arbitrating equipment ownership conflicts are disclosed. Individual control modules representing various process control entities within a process control system define a plurality of lists or queues for storing equipment arbitration information. Requests by one process control entity to acquire ownership over another process control entity are represented by an arbitration token that represents the ownership relationship sought by the acquiring process control entity. Copies of the arbitration token are communicated between the respective control modules and stored in the various arbitration queues defined by the control modules, depending on the status of the acquisition request.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: February 28, 2012
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Godfrey Roland Sherriff, Gary Keith Law
  • Patent number: 8122175
    Abstract: A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Keshavram N. Murty, Tessil Thomas, Keshavan Tiruvallur
  • Patent number: 8117616
    Abstract: A deadlock prevention mode indicator is provided, wherein the deadlock prevention mode indicator is a lock that can be held in a shared mode or in an exclusive mode by one or more of a plurality of threads, and wherein the plurality of threads can cause deadlocks while acquiring a plurality of data locks. An execution of the plurality of threads is serialized by allowing a data lock to be acquired by a thread in response to the thread holding the deadlock prevention mode indicator, wherein serializing the plurality of threads avoids any deadlock from occurring.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventor: Russell Lee Lewis
  • Publication number: 20120017017
    Abstract: A port A request queue is configured with a port AQ0 to a port AQn for each of request types Q0 to Qn connected with a requester resource busy flag controller Q0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ0 to turn a busy flag on when it is determined that a data request from the port AQ0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ0 inhibits output of a data request as long as the busy flag is on.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 19, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Masaru Nishiyashiki
  • Patent number: 8099539
    Abstract: A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a final output on an interface to provide glitchless switching of an interface signal, connecting the interface signal to a tri-state buffer, and setting the direction of a data and address bus based on the connection of the interface signal to the tri-state buffer. The method may include applying a fair arbitration policy to ensure that none of the devices coupled to the interface signal and application threads running on processor requiring data from different devices are starved.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: January 17, 2012
    Assignee: LSI Corporation
    Inventors: Rajendra Sadanand Marulkar, Gurvinder Pal Singh
  • Patent number: 8090895
    Abstract: An information processing system including plural information processing devices multi-dimensionally connected with one another, where each of the information processing devices includes first and second receiving storage devices to store data allocated to first and second virtual channels in respective data transmitting and receiving directions, a virtual channel control unit to compare a position in a dimension of a destination information processing device with a position in the same dimension of an own information processing device, and if the comparison result indicates that the position of the own information processing device matches a position one information processing device before the position of the destination information processing device, change one of the first and the second virtual channels to the other one, and a data storage unit to store the allocated data in a corresponding one of the first and second storage devices.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: January 3, 2012
    Assignee: Fujitsu Limited
    Inventor: Yuzo Takagi
  • Patent number: 8078764
    Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 13, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba, Keitaro Uehara, Yuji Tsushima
  • Patent number: 8046086
    Abstract: A system and method for implementing a control process within a process control system and resolving inconsistencies during execution of the control process includes loading the logical structure of the control process, loading a plurality of instantiation objects or processes when the control process is instantiated, using the instantiation objects to instantiate a procedural element of the control process as the control process calls for the procedural element during execution, executing the procedural element as part of the control process, and deconstructing the procedural element as execution of the procedural element is completed during execution of the control process. Resolution of inconsistencies includes executing a first model of an entity in a controller, executing a second model of the entity in an execution engine, detecting a difference between the models, generating a prompt and receiving an operation instruction to continue the process or abort the process.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: October 25, 2011
    Assignee: Fisher-Rosemount Systems, Inc.
    Inventors: Nathan Pettus, Will Irwin, Kim Conner, Mickey Nanda
  • Publication number: 20110179248
    Abstract: A device and methods are provided for adaptive bandwidth allocation for memory of a device are disclosed and claimed. In one embodiment, a method includes receiving, by a memory interface of the device, a memory access request from a first client of the memory interface, and detecting available bandwidth associated with a second client of the memory interface based on the received memory access request. The method may further include loading a counter, by the memory interface, for fulfilling the access request, wherein the counter is loaded to include bandwidth associated with the first client and the available bandwidth associated with the second client, and granting the memory access request for the first client based on bandwidth allocated for the counter.
    Type: Application
    Filed: June 18, 2010
    Publication date: July 21, 2011
    Applicant: ZORAN CORPORATION
    Inventor: Junghae Lee
  • Patent number: 7950014
    Abstract: Aspects of the subject matter described herein relate to detecting the ready state of a user interface element. In aspects, a synchronization object is created to indicate when a user interface element is ready. Data is then loaded into the user interface element. After the data is loaded, an indication is made via the synchronization object that the user interface element is ready. After this occurs, a thread waiting on the synchronization object may interact with the user interface element with confidence that the user interface element is ready.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: May 24, 2011
    Assignee: Microsoft Corporation
    Inventor: Ronald R. Martinsen
  • Patent number: 7949812
    Abstract: A wireless network device includes a first communication module to communicate with at least one of first devices and a second communication module to communicate with at least one of second devices. An arbitration module receives a request for communication from the first communication module, detects when the second communication module is communicating in a locked mode, and denies request for communication from the first communication module when the second communication module is communicating in the locked mode. Transmission or reception of a packet in the locked mode is not interrupted to avoid loss of the packet. The arbitration module grants the request for communication from the first communication module when the second communication module is communicating in the locked mode and when granting the request for communication from the first communication module does not require stopping the second communication module from communicating in the locked mode.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: May 24, 2011
    Assignee: Marvell International Ltd.
    Inventors: Gladys Yuen Yan Wong, Timothy J. Donovan, Timothy Li, Ken Yeung