Interrupt Inhibiting Or Masking Patents (Class 710/262)
  • Publication number: 20140082241
    Abstract: The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction.
    Type: Application
    Filed: February 28, 2011
    Publication date: March 20, 2014
    Inventors: Leonardo Vainsencher, Yaron P. Folk, Yuval Itkin
  • Patent number: 8661177
    Abstract: A method and apparatus are provided for controlling system management interrupts is disclosed. An interrupt filter comprises a memory, a comparator and a logic circuit. The memory is adapted to contain a list indicating one or more devices with permission associated with an interrupt signal. The comparator is adapted to receive an interrupt signal containing type information from the one or more devices. The comparator is adapted to compare the interrupt type against the list to determine if the one or more devices is permitted to send the interrupt signal. The logic circuit blocks or passes the interrupt signal in response to the result of the comparison.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 25, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, Mark D. Hummel
  • Patent number: 8650430
    Abstract: In a communication system in which data is transmitted and received in synchronization with a clock signal, a peripheral device cannot transfer data to a host device when the host device stops outputting the clock signal and thus the peripheral device cannot promptly transmit an interrupt request to the host device. A peripheral device transmits an interrupt request to a host device using a signal line for a clock signal when the clock signal output has been stopped. The host device receives the interrupt request, and resumes outputting a clock signal to enable data transmission and reception to and from the peripheral device. This enables the peripheral device to transmit an interrupt request to the host device promptly when the output of the clock signal from the host device has been stopped.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: February 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Masahiro Nakamura, Tadashi Ono, Isao Kato
  • Publication number: 20130339562
    Abstract: A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.
    Type: Application
    Filed: March 8, 2013
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Damian L. Osisek, Timothy J. Slegel
  • Publication number: 20130339561
    Abstract: A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Damian L. Osisek, Timothy J. Slegel
  • Patent number: 8612661
    Abstract: An interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the interrupt-notification control unit determines a correlation among the interrupt requests to control a time to send the interrupt requests together to the processor.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: December 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takashi Shimada
  • Patent number: 8612659
    Abstract: Hardware interrupts are routed to one of multiple processors of a virtualized computer system based on priority values assigned to the codes being executed by the processors. Each processor dynamically updates a priority value associated with code being executed thereby, and when a hardware interrupt is generated, the hardware interrupt is routed to the processor that is executing a code with the lowest priority value to handle the hardware interrupt. As a result, routing of the interrupts can be biased away from processors that are executing high priority tasks or where context switch might be computationally expensive.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: December 17, 2013
    Assignee: VMware, Inc.
    Inventors: Benjamin C. Serebrin, Raviprasad Mummidi
  • Patent number: 8612660
    Abstract: A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator indicating the receipt of the first interrupt and recording a first timestamp based on the receipt of the first interrupt. The system and method further adapted to virtually execute a routine for the first interrupt that includes determining if the second indicator is set, record a second timestamp based on the virtual execution of the routine and determine an interrupt latency based on the first and second timestamp.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: December 17, 2013
    Assignee: Wind River Systems, Inc.
    Inventors: Maarten Koning, Tomas Evensen
  • Patent number: 8612658
    Abstract: An interrupt reducing device driver module reduces the rate at which interrupts from a peripheral burden a processor. The interrupt reducing device driver determines when data is associated with the interrupt. When data is present, such as when indicated by an interrupt status register, further interrupts are masked and a buffer associated with the peripheral is read-out. This read-out continues while data is present in the buffer. Once no further data is present, the data interrupts are unmasked. Reduction in the rate of interrupts prevents resource starvation and improves overall system response. Additionally, the processor and associated components are able to enter and remain in low power modes, improving battery life.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 17, 2013
    Assignee: Amazon Technologies, Inc.
    Inventor: Manish Lachwani
  • Patent number: 8612986
    Abstract: A computer program product for scheduling threads in a multiprocessor computer comprises computer program instructions configured to select a thread in a ready queue to be dispatched to a processor and determine whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, the computer program instructions are configured to select a processor, set a current processor priority register of the selected processor to least favored, and dispatch the thread from the ready queue to the selected processor.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jos M. Accapadi, Mathew Accapadi, Andrew Dunshea, Mark E. Hack, Agustin Mena, III, Mysore S. Srinivas
  • Publication number: 20130326102
    Abstract: A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
  • Patent number: 8589612
    Abstract: A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: November 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromichi Yamada, Kotaro Shimamura, Nobuyasu Kanekawa, Yuichi Ishiguro
  • Publication number: 20130290586
    Abstract: The access device comprises a memory and a device controller configured to send and receive a data control right between the data recording device and a central controller provided in a host device. When having received a request to interrupt transfer of data from the central controller while data is being transferred from the data recording device, the device controller releases the data control right from the data recording device, and has the data recording device determine whether or not mismatching has occurred in file system management information for data stored in the memory. The device controller then returns the data control right to the data recoding device when it is determined that mismatching has occurred in the file system management information. The data recording device releases the data control right after eliminating the mismatching in the file system management information according to the returned data control right.
    Type: Application
    Filed: June 27, 2013
    Publication date: October 31, 2013
    Inventors: Masahiro NAKAMURA, Takuji MAEDA
  • Patent number: 8566493
    Abstract: Methods of operation and interrupt controllers for generating interrupt signals to a unit, which could enter an active mode and a non-active mode, are disclosed. The interrupt controllers have interrupt logic (204) adapted for receiving requests for interrupt, activity mode logic (202) adapted for receiving information whether the unit is in non-active mode, and delay control logic (203) adapted for delaying the interrupt to the unit when the received information indicates that the unit is in non-active mode.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: October 22, 2013
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Harald Gustafsson, Ulf Morland, Per-Inge Tallberg
  • Patent number: 8549201
    Abstract: A method comprises maintaining, in a first electronic device, a list of one or more electronic devices associated with a user, receiving, in the first electronic device, a first command, in response to the first command, forwarding a command to block interrupts on one or more electronic devices on the list of electronic devices. Other embodiments may be described.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventors: Jeffrey C. Sedayao, Vishwa Hassan, Douglas P. Devetter, Terry H. Yoshi, David W. Stone
  • Patent number: 8539489
    Abstract: Improving the performance of multitasking processors are provided. For example, a subset of M processors within a Symmetric Multi-Processing System (SMP) with N processors is dedicated for a specific task. The M (M>0) of the N processors are dedicate to a task, thus, leaving (N?M) processors for running normal operating system (OS). The processors dedicated to the task may have their interrupt mechanism disabled to avoid interrupt handler switching overhead. Therefore, these processors run in an independent context and can communicate with the normal OS and cooperation with the normal OS to achieve higher network performance.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 17, 2013
    Assignee: Fortinet, Inc.
    Inventor: Jianzu Ding
  • Patent number: 8521912
    Abstract: Methods and systems for direct device access are disclosed. Aspects of one method may include a plurality of GOSs directly accessing a first network interface device, where the first network interface device may provide access to a network. One or more of the GOSs may be migrated to directly access a second network interface device, based on state information for each of the GOSs, where the state information may be maintained by the host. The GOSs may communicate data to a device coupled to the network by direct accessing the first and/or second network interface device. Similarly, the first and/or second network interface device may communicate data received from a device coupled to the network to one or more of the plurality of GOSs via direct access of the first and/or second network interface device.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: August 27, 2013
    Assignee: Broadcom Corporation
    Inventors: Eliezer Aloni, Uri Elzur, Rafi Shalom, Kobby Carmona, Caitlin Bestler
  • Patent number: 8504750
    Abstract: Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plural functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 6, 2013
    Assignee: QLOGIC, Corporation
    Inventors: Bradley S. Sonksen, Richard S. Moore
  • Patent number: 8504752
    Abstract: The interrupt level storing unit (16) stores one or more interrupt levels indicating the priority of a generated interrupt and stores the interrupt level having the highest priority among the stored interrupt levels as a second interrupt mask level. The second interrupt type determination unit (13) sets an interrupt level corresponding to the interrupt type of a newly generated interrupt. The priority determination unit (14) notifies the interrupt to the virtual machine control unit (20) when the interrupt level of the newly generated interrupt is higher than the stored second interrupt mask level. As a result, the priority of the virtual machine can be determined according to the task priority and the switching of virtual machines can be adequately controlled even if the virtual machines cannot notify the task priority.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: August 6, 2013
    Assignee: Panasonic Corporation
    Inventors: Katsuhiro Arinobu, Tadao Tanikawa, Katsushige Amano
  • Patent number: 8504753
    Abstract: Suspendable interrupts are described that allow a processor to remain in an idle state for a longer period of time. Each suspendable interrupt defines a maximum delay value that specifies the maximum delay software associated with the interrupt can wait between a receipt of an interrupt signal associated with the suspendable interrupt and raising the interrupt for servicing by the software. The delay value allows suspendable interrupts to be masked when a processor is placed in the idle state if they can be dealt with at a next scheduled wake time of the processor, allowing the processor to potentially remain in the idle state for a longer period of time.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 6, 2013
    Assignee: QNX Software Systems Limited
    Inventor: Attilla Danko
  • Patent number: 8499111
    Abstract: An information processing apparatus includes an interrupting signal control device including a mask controller, the mask controller controlling whether or not to mask at least one interrupting signal serving as a trigger signal triggering a predetermined process; and a clock control device including an interrupting clock signal controller, the interrupting clock signal controller sends a clock signal to the interrupting signal control device when at least one interrupting signal is not masked, and stops sending the clock signal to the interrupting signal control device when at least one interrupting signal is masked.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Limited
    Inventor: Mitsuo Honta
  • Patent number: 8495267
    Abstract: Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, John M. Borkenhagen, Dan E. Poff
  • Patent number: 8484389
    Abstract: An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two processors 310, 314 from racing to access the same system resources in their respective interrupt service routines.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 9, 2013
    Assignee: Entropic Communications, Inc.
    Inventor: Puranjoy Bhattacharya
  • Patent number: 8478922
    Abstract: The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brenton F. Belmar, David Craddock, Janet R. Easton, Mark S. Farrell, Thomas A. Gregg, Damian L. Osisek, Donald W. Schmidt, Gustav E. Sittmann, III, Richard P. Tarcza
  • Patent number: 8478924
    Abstract: In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O) commands for which corresponding I/O completions have not been received. Deliveries of interrupts are executed on the basis of the current level and in an absence of enabling timing-triggered delivery of an interrupt.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: July 2, 2013
    Assignee: VMware, Inc.
    Inventors: Irfan Ahmad, Maxime Austruy, Mallik Mahalingam
  • Publication number: 20130166803
    Abstract: A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Janet R. Easton, Norbert Hagspiel, Bernd Nerz
  • Patent number: 8473662
    Abstract: Provided is a method capable of providing an improved response property appropriate for the characteristics of a system by automatically choosing an interrupt handling mode used for each device. The method is a method in which the embedded operating system kernel determines a handling mode for all individual interrupts, the method includes: dividing interrupt handling modes into a first interrupt handling mode and a second interrupt handling mode which has a different process speed from the first interrupt handling mode, and variably determining a distribution ratio in which each of the interrupts are distributed to the first interrupt handling mode or to the second interrupt handling mode according to a predetermined process condition during boot-up.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: June 25, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dong-Hyouk Lim, Yung-Joon Jung, Yong-Bon Koo, Chae-Deok Lim, Dong-Sun Lim
  • Publication number: 20130159577
    Abstract: The variation of the timing of starting interrupt processing in response to a timer interrupt request is reduced regardless of the condition of processing of other interrupts. A semiconductor data processing device incorporated in each of plural electronic control devices coupled to a network for time-triggered communication system is provided with a central processing unit, a communication control circuit and an interrupt control circuit. The communication control circuit has a local time timer for use in time-triggered communication and issues, based on time counting by the local time timer, a timer interrupt request for time-triggered communication. When a timer interrupt request for time-triggered communication is received, the interrupt control circuit performs control to cause the central processing unit to delay, by a predetermined reservation time, starting the interrupt processing to be performed in response to the timer interrupt request.
    Type: Application
    Filed: November 1, 2012
    Publication date: June 20, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: RENESAS ELECTRONICS CORPORATION
  • Publication number: 20130159575
    Abstract: Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for example, whether they execute tasks of the same job or receive power from the same converter. Once one of compute nodes in the group detects that a parameter (i.e., temperature, current, power consumption, etc.) has exceeded a first threshold, power throttling on all the nodes in the group may be activated. However, before deactivating power throttling, a plurality of parameters associated with the group of compute nodes may be monitored to ensure they are all below a second threshold. If so, the power throttling for all of the compute nodes is deactivated.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: International Business Machines Corporation
    Inventors: Thomas M. Gooding, Brant L. Knudson, Cory Lappi, Ruth J. Poole, Andrew T. Tauferner
  • Publication number: 20130159576
    Abstract: A method and apparatus are provided for controlling system management interrupts is disclosed. An interrupt filter comprises a memory, a comparator and a logic circuit. The memory is adapted to contain a list indicating one or more devices with permission associated with an interrupt signal. The comparator is adapted to receive an interrupt signal containing type information from the one or more devices. The comparator is adapted to compare the interrupt type against the list to determine if the one or more devices is permitted to send the interrupt signal. The logic circuit blocks or passes the interrupt signal in response to the result of the comparison.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Inventors: Andrew G. Kegel, Mark D. Hummel
  • Publication number: 20130145066
    Abstract: An early interrupt feature enables generation of interrupts prior to completion of an analog-to-digital conversion to be used in a processor PID calculation. Even though an analog-to-digital conversion is still in process, the PID application software can use the early interrupt time to begin execution of an interrupt service routine (ISR). The early interrupt can improve the throughput and response time of the PID control loop by overlapping the completion of the ADC conversion with the processor overhead associated with the interrupt request. A plurality of pipelined registers, each having substantially the same delay time as the pipelined stages of the ADC, are selectable to provided a delay time that may be used to generate an early interrupt, wherein the latency time between an ADC conversion and processing of an interrupt relating to that ADC conversion may thereby be shortened.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventor: Bryan Kris
  • Patent number: 8458386
    Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: June 4, 2013
    Assignee: Apple Inc.
    Inventors: Michael J. Smith, Josh P. de Cesare, Mark D. Hayter
  • Patent number: 8448239
    Abstract: A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.
    Type: Grant
    Filed: March 5, 2011
    Date of Patent: May 21, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dennis M. O'Connor, Mark N. Fullerton, Ray Richardson
  • Publication number: 20130124769
    Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model, The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.
    Type: Application
    Filed: January 10, 2013
    Publication date: May 16, 2013
    Inventors: Bruce Fleming, Arvind Mandhani
  • Patent number: 8443423
    Abstract: Apparatus, systems, and methods may operate to receive from a requesting device, at a memory device, a request to access a memory domain associated with the memory device, and to deny, by the memory device, the request if the memory domain comprises any part of a secure domain, and the requesting device has not asserted a secure transfer indication. Additional operations may include granting the request if the memory domain comprises some part of the secure domain and the requesting device has asserted the secure transfer signal, or if the memory domain comprises only a non-secure domain. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: May 14, 2013
    Assignee: Atmel Corporation
    Inventor: Erik Knutsen Renno
  • Patent number: 8424016
    Abstract: Briefly, techniques to manage interrupts and swaps of threads operating in critical region. In an embodiment, a thread is to be interrupted during a first critical region with an interrupt routine. The thread may be set to restart at a beginning of the first critical region in response to an indication that the thread is working in a critical region. Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 16, 2013
    Assignee: Intel Corporation
    Inventor: Joseph S. Cavallo
  • Patent number: 8392918
    Abstract: A technique to process interrupts on a virtualized platform. A plurality of virtual machines (VMs) runs on the virtualized platform having at least a processor. The VMs include a power VM. A VM scheduler schedules the VMs for execution on the virtualized platform according a scheduling policy. A virtualized interrupt mask controller controls masking an interrupt from an interrupting source according to the scheduling policy. An interrupt is masked from an interrupting source according to the scheduling policy for at least one of the VMs; and the at least one of the VMs is caused to get the interrupt when the at least one of the VMs is enabled according to the scheduling policy.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventor: Eric K. Mann
  • Patent number: 8392635
    Abstract: Embodiments of the invention are directed to systems and methods for reducing the number of interrupts on a controller for a non-volatile storage device to improve data transfer performance of the storage system. The embodiments described herein selectively enable an interrupt generated by host transfer hardware for a host command. The interrupt can be enabled or disabled by considering the command type, availability of interface resources to accept additional host transfers, and the command size. Embodiments described herein are useful for host interfaces implementing a tagging scheme for host transfers with a limited range of identification tags.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: March 5, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jing Booth, Rebekah A. Wilson
  • Patent number: 8386683
    Abstract: An information processing device in which interrupts are generated when some events are occurred. The information processing device includes: an interrupt generating unit to generate an interrupt; an interrupt control unit to receive the generated interrupt, count an interrupt reception count per unit time, notify of the interrupt and delay, if the counted interrupt reception count per unit time exceeds a predetermined value, the interrupt notification; and an interrupt processing unit to process the notified interrupt.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: February 26, 2013
    Assignee: Fujitsu Limited
    Inventor: Masahide Hiroki
  • Patent number: 8386666
    Abstract: A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: February 26, 2013
    Assignee: Marvell International Ltd.
    Inventors: Ofer Bar-Shalom, Mark N. Fullerton, Alon Tsafrir
  • Patent number: 8380908
    Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: February 19, 2013
    Assignee: Intel Corporation
    Inventors: Bruce L. Fleming, Arvind Mandhani
  • Patent number: 8380907
    Abstract: A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Lisa C. Heller, Damian L. Osisek, Charles F. Webb
  • Patent number: 8356131
    Abstract: System, method, and program to determine whether to interrupt a process, e.g., a write function, to carry out another process, e.g., a high priority read function, in a device that uses memory devices, e.g., eMMC devices, that use a single channel to carry out two different processes, e.g., write and read processes.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: January 15, 2013
    Assignee: Sony Mobile Communications AB
    Inventor: Wladyslaw Bolanowski
  • Patent number: 8335881
    Abstract: A method for handling an interrupt during testing of at least one logic block of a processor includes performing a test on at least one logic block of a processor; during the performing, receiving an interrupt; determining a progress status of the test in response to receiving the interrupt; and determining when the processor responds to an interrupt, wherein the determining when the processor responds to an interrupt is based on the progress of the test.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: December 18, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David M. Welguisz, Gary R. Morrison
  • Patent number: 8315173
    Abstract: Disclosed is a transmission apparatus in which a plurality of elements implement virtually one apparatus. Each element includes at least one main signal package and a monitor control package that is connected to the main signal package via an intra-apparatus bus 40 and connected to another monitor control package via an inter-apparatus communication bus. The monitor control package in one element, on occurrence of a malfunction in the main signal package being monitored, collects an alert from the main signal package being monitored, and transmits an alert masking control signal, using the inter-apparatus bus, to the monitor control package of another element to which belong the main signal package of a masking target. The main signal package of the masking target suppresses alerting of a second-order malfunction in case of detection of the second-order malfunction on receipt of the alert masking control signal.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: November 20, 2012
    Assignee: NEC Corporation
    Inventor: Kimio Ozawa
  • Patent number: 8286162
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: October 9, 2012
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Patent number: 8271978
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Patent number: 8266620
    Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: September 11, 2012
    Assignee: MIPS Technologies, Inc.
    Inventor: Kevin D. Kissell
  • Patent number: 8261284
    Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: September 4, 2012
    Assignee: Microsoft Corporation
    Inventor: Jork Loeser
  • Patent number: 8255602
    Abstract: This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: August 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Paul Kimelman