Abstract: An extremely low overhead method calculates CPU load in the presence of both CPU idling and frequency scaling. The method measures time the CPU is idled while waiting for a wakeup. This invention uses a feature in current DSPs with the capability of delaying ISR processing on wake from IDLE. Using this mechanism it is possible to determine the time before IDLE, the time immediately following CPU wakeup, and then run the wakeup ISR. The delta time can be accumulated and compared to total time to determine true CPU load.

Abstract: An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.

Abstract: An interrupt controller has an interrupt register unit receiving a plurality of interrupt source signals, an interrupt detector coupled to the interrupt register unit, a counter unit coupled to the interrupt detector, wherein on the first occurrence of an interrupt source signal the counter unit defines a time window during which the interrupt register stores further interrupt source signals, and an interrupt request unit coupled to the counter unit for generating an interrupt request signal.

Abstract: A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention.

Abstract: Disclosed are methods for handling RDMA connections carried over packet stream connections. In one aspect, I/O completion events are distributed among a number of processors in a multi-processor computing device, eliminating processing bottlenecks. For each processor that will accept I/O completion events, at least one completion queue is created. When an I/O completion event is received on one of the completion queues, the processor associated with that queue processes the event. In a second aspect, semantics of the interactions among a packet stream handler, an RDMA layer, and an RNIC are defined to control RDMA closures and thus to avoid implementation errors. In a third aspect, semantics are defined for transferring an existing packet stream connection into RDMA mode while avoiding possible race conditions. The resulting RNIC architecture is simpler than is traditional because the RNIC never needs to process both streaming messages and RDMA-mode traffic at the same time.

Abstract: A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and a separate send handler are provided to simultaneously process completion of a send event and a receive event. In addition, separate queues are provided to communicate receipt of an event to the respective interrupt handler.

Abstract: Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: Embodiments of an interrupt mailbox in host memory are described herein. In an implementation, a device connected to a host writes interrupt data corresponding to an interrupt generated by the device to host memory. Then, the host, when processing the interrupt, accesses the interrupt data from the host memory.

Abstract: System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register.

Abstract: An interrupt notification block stored in host memory is disclosed that contains an image of the interrupt condition contents that may be stored in a host attention register in a host interface port. The interrupt notification block is written by the host interface port and pre-fixed into the port pointer array of a host at the time the host interface port updates the pointers stored in a port pointer array in host memory. The host may then read the interrupt notification block to determine how to process a response or an interrupt rather than having to read the host attention register in the host interface port across the host bus.

Abstract: A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: A multithreaded processor capable of allocating interrupts is described. In one embodiment, the multithreaded processor includes an interrupt module and threads for executing tasks. The interrupt module can identify a priority for each thread based on a task priority for tasks being executed by the threads and assign an interrupt to a thread based at least on its priority.

Abstract: A system includes an integrated encoder comprising an optical storage controller for coupling to an optical storage medium, and a data encoder for coding input data coupled to the optical storage controller, a first external memory coupled to a first memory controller in the integrated encoder, and a second external memory coupled to a second memory controller in the integrated encoder. In one aspect, the integrated encoder further comprises a first memory arbiter for selectively directing access to the first external memory by the optical storage controller and the data encoder, and a second memory arbiter for selectively directing access to the second external memory by the optical storage controller and the data encoder.

Abstract: An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request request.

Abstract: An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned by the main control unit 112 during the execution of the main process, as a sub-process. An event detector 162 detects an event occurrence upon which an interrupt task is to be preferentially executed during the execution of the main process. An interrupt notification unit 164 notifies the sub-control unit 116 of interrupt information indicative of an interrupt task in response to the detected event. The sub-control unit 116 notified of the interrupt information executes the interrupt task specified by the interrupt information, as a sub-process.

Abstract: Methods and systems are provided for remotely securing data in a wireless device. A user sends a data message containing instructions for securing data to a remotely located wireless device. Securing data includes recovering data, purging data, locking the wireless device, and locating the wireless device within a communications network. After the data message is sent, a determination is then made as to whether the wireless device is active in the communications network. If the wireless device is active, the data message is sent to the wireless device. If the wireless device is inactive, the data message is temporarily stored in a database until the wireless device is determined to be active. An application program resident on the wireless device is executed upon receiving the data message to secure the data. The data message also includes instructions for retrieving data for identifying an owner of the wireless device.

Abstract: An event notifying method notifies one or a plurality of events from a device to a processor by queuing to a queue in a processor system having one or a plurality of processors. A number of non-notified events existing in the queue is managed by a counter unit, and an inconsistent state of the counter unit caused by differences in updating timings of the counter unit from the device and the processor is temporarily permitted.

Abstract: A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.

Abstract: An information handling system recovers from memory errors associated with a memory unit that supports operation of an SMI handler by using another memory unit to support operation of the SMI handler. For example, if an SMI handler detects an error associated with a DIMM that supports operation of the SMI handler, then an SMI handler location module moves the SMI handler to another DIMM. For instance, a jump command is activated to jump to a pre-existing copy of the SMI handler stored at another DIMM. As another example, a relocation of the SMI handler to another DIMM is performed by changing address information used by the chipset and CPUs to run the SMI handler.

Abstract: A method for distributing interrupt load to processors in a multiprocessor system. The method includes executing current transactions with multiple processors (104, 106, 108) where each transaction is associated with one of the processors, generating an interrupt request, estimating a transaction completion time for each processor and directing the interrupt request (102) to the processor having the least estimated transaction completion time. Estimating a transaction completion time occurs periodically so that information pertaining to transaction times is stored and continually updated. According to one aspect of the invention, the step of estimating a transaction completion time for each processor occurs when the interrupt request is generated. According to another aspect of the invention, the step of communicating the interrupt request includes communicating the interrupt request to an intermediary processor prior to estimating the transaction completion time.

Abstract: A system (150) and method provide for the transfer of at least one packet (194) comprising data between a user space (152) and a kernel space (154) associated with a server (156) that is positioned in a distributed network arrangement (192) with a plurality of clients (158, 160, 162, 164). A distribution program (168) associated with the user space (152) is operable to accumulate the at least one packet (194). An application program interface (174) associated with the user space (152) transfers the at least one packet (194) to the kernel space (154) with a number of software interrupts (204). A driver (176) associated with the kernel space (154) is operable to distribute the at least one packet (194) to a subset of the plurality of clients (158, 160, 162, 164) in response to receiving the number of software interrupts (204). The number of software interrupts (204) is less than one software interrupt per packet per client.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status registers containing interrupt status information for the plurality of channels, interrupt sources are specifically assigned to individual processors in the multiprocessor device so that the assigned processor can efficiently determine the source and priority of an interrupt by reading the register information.

Abstract: A distributed control system and methods of operating such a control system are disclosed. In one embodiment, the distributed control system is operated in a manner in which interrupts are at least temporarily inhibited from being processed to avoid excessive delays in the processing of non-interrupt tasks. In another embodiment, the distributed control system is operated in a manner in which tasks are queued based upon relative timing constraints that they have been assigned. In a further embodiment, application programs that are executed on the distributed control system are operated in accordance with high-level and/or low-level requirements allocated to resources of the distributed control system.

Abstract: A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral device, including relevant setting values of a hardware IRQ routing, is input and compared with a PCI IRQ routing table pre-stored in a boot control unit. Then, whether errors exist in the current setting values of the relevant control parameters and flags of all the relevant control units are automatically checked. If an incorrect setting value is found, a corresponding diagnosis result message is displayed for informing the user to make a modification. Therefore, users can know the reasons that cause the computer peripheral device to operate abnormally and make the modification quickly and effectively.

Abstract: A system includes a plurality of partitions having respective operating systems, and a resource shared by the partitions. The resource has plural segments, where a first one of the segments is accessed to invoke a first interrupt. An operating system of a first one of the plurality of partitions invokes, in response to the first interrupt, a routine to cause generation of a second interrupt to a second one of the plurality of partitions.

Abstract: Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit end-of-interrupt command by providing an automatic EOI capability even when a physical interrupt controller offers no such mechanism. The use of a message pending bit for inter-partition communications facilitates avoiding an EOI command of inter-processor interrupts used in inter-partition communications whenever no further messages are cued for a particular message slot. A virtualized interrupt controller facilitates the selective EOI of an interrupt even when it is not the highest priority in-service interrupt irrespective of whether a physical interrupt controller provides such functionality.

Abstract: Embodiments of the present invention provide methods and systems for allocating multiple tags to multiple requesters in back to back clock cycles. A tag pool may be divided into a predetermined number of sections. Each requester may be associated with at least one of the sections in the tag pool. When multiple tag requests are received from multiple requesters each section containing available tags may provide a tag to a requester associated with the section per clock cycle. Therefore, multiple tags may be provided to multiple requesters in back to back clock cycles, thereby increasing efficiency and improving performance.

Abstract: An interrupt controller superior in maintenance performance and expandability. An interrupt controller 10 comprises a queue circuit 11 that holds channel numbers corresponding to interrupt inputs in the order of priority levels, and a queue control circuit 12 that changes the order of the channels held in the queue circuit 11 according to a new order of the priority levels when a priority level that corresponds to any channel number is changed. The order of the channel numbers in the queue circuit 11 is changed at a time of setting the priority levels unrelated to interrupt inputs. In order to select an interrupt to be notified to a CPU 20, an interrupt factor selection circuit 15 checks whether or not each channel number held in the queue circuit 11 has an interrupt input in turn from the head of the queue.

Abstract: A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.

Abstract: A DMA interrupt coalescer processes interrupts received from a DMA channel of a DMA controller by transmitting an interrupt request to an interrupt controller if a coalescing condition is satisfied after receiving one or more delayable interrupts, or transmitting the interrupt request regardless of the satisfaction of the coalescing condition if a non-delayable interrupt is received. The coalescing condition is satisfied if a non-zero period of time has transpired since a first of the one or more delayable interrupts was received, or if a number of the one or more delayable interrupts received exceeds a programmed value.

Abstract: Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application.

Abstract: This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plurality of times. A software interrupt counter or a hardware interrupt counter for retaining the number of times of occurrence of an interrupt request generation event counts up when a software processing which generates a software interrupt or a hardware event that generates a hardware interrupt occurs, and counts down when a CPU performs a processing for removing the interrupt request. If the value of the software interrupt counter and the value of the hardware interrupt counter are not zero, a software interrupt request signal and a hardware interrupt request signal to the CPU are asserted.

Abstract: Within a processing of a sender task, a transmission request occurs that a data item be sent to a processing of a recipient task. The data item is then once stored in a queue from which the recipient task can retrieve the data item when the recipient task is thereafter activated. When the data item is stored, it is determined whether the queue already stores another data item. When no another data item is being stored, an activation request for activating the recipient task is outputted to the operating system. When another data item is being stored, no activation request is outputted. Within the processing of the recipient task, all the data items are retrieved from the queue. This decreases the activation/termination of the recipient task, reducing the processing load.

Abstract: An interrupt control apparatus that controls an interrupt process request caused by a predetermined interrupt factor is disclosed. The interrupt control apparatus includes: an obtaining unit configured to obtain an interrupt process request signal including an interrupt factor identifier associated with at least equal to or more than two interrupt factors; an interrupt process unit configured to execute an interrupt process requested by the interrupt process request signal; and a control unit configured to control the interrupt process unit so as not to execute interrupt processes caused by interrupt factors associated with the interrupt factor identifier until the interrupt process executed by the interrupt process unit ends.

Abstract: The present invention relates to an adaptive interrupts coalescing system with recognizing minimum delay packets. The adaptive interrupts coalescing system of the invention comprises a first calculating device, a packet header parser, a second calculating device, and an interrupt controller. The first calculating device is used for calculating packet information of a plurality of packets. The packet header parser is used for recognizing the type of service field in each packet and for generating a minimum delay control signal. The second calculating device is used for determining a coalescing interrupt number signal according to the packet information and the minimum delay control signal. The interrupt controller is used for transmitting an interrupt control signal to process the packet according to the coalescing interrupt number signal.

Abstract: A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and a separate send handler are provided to simultaneously process completion of a send event and a receive event. In addition, separate queues are provided to communicate receipt of an event to the respective interrupt handler.

Abstract: In a computer having a unit for outputting an interrupt request to a processor, a delay condition from occurrence of an interrupt event to issue of an interrupt request to the processor can be dynamically determined depending on the processor load status, etc. The interrupt request output unit includes a unit for obtaining a determination factor of a delay condition from the occurrence of an interrupt event to the issue of an interrupt request to the processor, and a unit for determining a delay condition corresponding to the obtained determination factor. For example, a time up to a read of an interrupt factor by the processor is obtained as a determination factor, and is multiplied by a coefficient, thereby determining a delay time as a delay condition.

Abstract: A method and apparatus for recording moving picture data encoded using a prediction encoding system, in which the playback control information is recorded along with moving picture data encoded using the MPEG system. The playback control information includes the information specifying a program decoding starting picture and a display starting picture and the information specifying the program decoding terminating picture and a display terminating picture. During reproduction, the playback control information is first read out and moving picture data are decoded based on this information. This enables seamless reproduction from a pre-skipping picture to a post-skipping picture.

Abstract: Embodiments of an interrupt mailbox in host memory are described herein. In an implementation, a device connected to a host writes interrupt data corresponding to an interrupt generated by the device to host memory. Then, the host, when processing the interrupt, accesses the interrupt data from the host memory.

Abstract: Certain aspects of a method and system for coalescing task completions may include coalescing a plurality of completions per connection associated with an I/O request. An event may be communicated to a global event queue, and an entry may be posted to the global event queue for a particular connection based on the coalesced plurality of completions. At least one central processing unit (CPU) may be interrupted based on the coalesced plurality of completions.

Abstract: The present invention provides an electronic device comprising: —a position sensor (102; 302; 502), —a first integrated circuit component (106; 306; 506) coupled to the position sensor for acquisition of position data (112; 312), —a memory (114; 314) for storing the position data, a second integrated circuit component (108; 308), wherein the first integrated circuit component comprises means (110; 348) for signalling the acquisition of the position data to the second integrated circuit component, the second integrated circuit component comprising means (108; 364, 374) for reading the position data from the memory in response to the signalling.

Abstract: Embodiments of the present invention provide improved event handling between systems. In one embodiment, the present invention includes software event handling method comprising receiving a first event from a first source system in a plurality of source systems, the first event including event information, accessing context information corresponding to the first event, generating a second event based on at least a portion of the event information and context information using one or more rules, assigning a priority to the second event, and sending the second event to a first target system in a plurality of target systems.

Abstract: Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers to handle interrupts triggered by the function blocks of multi-protocol optical networking modules (MPONM). Each registered interrupt handler may handle interrupts triggered by one or more function blocks of any of the MPONM, and/or for one or more cause. In one embodiment, the one or more interrupt dispatchers are equipped to determine the triggering function block and the cause, and determine the interrupt handlers, if any, are to be notified. Each of the interrupt handlers to be notified is notified accordingly, including the triggering function block and the cause.

Abstract: Certain aspects of a method and system for delayed completion coalescing may be disclosed. Exemplary aspects of the method may include accumulating a plurality of bytes of incoming TCP segments in a host memory until a number of the plurality of bytes of incoming TCP segments reaches a threshold value. A completion queue entry (CQE) may be generated to a driver when the plurality of bytes of incoming TCP segments reaches the threshold value and the plurality of bytes of incoming TCP segments may be copied to a user application. The method may also include delaying in a driver, an update of a TCP receive window size until one of the incoming TCP segments corresponding to a particular sequence number is copied to the user application. The CQE may also be generated to the driver when at least one of the incoming TCP segments is received with a TCP PUSH bit SET and the TCP receive window size is greater than a particular window size value.

Abstract: A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an interrupt. If one of the co-processors generated an interrupt, the ISR schedules the DPC for execution and disables sending of further interrupts from all of the co-processors. The DPC services pending interrupts from any of co-processors, then re-enables sending of interrupts from the co-processors.