Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

Abstract: A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.

Abstract: In accordance with an embodiment, a method of operating a processor includes operating in a first operating mode that prohibits access to a protected memory area, receiving a priority interrupt (PI) signal, operating in a second operating mode in response to receiving the PI signal, and executing a first routine by asserting a semi-privileged interrupt (SPI). Access to the protected memory area is permitted in the second operating mode, and the first routine operates in the second operating mode and is interruptible by the PI signal.

Abstract: An information handling system is provided. The information handling system includes an information handling device having one or more processors in communication with a network interface card. The network interface card includes one or more interfaces for receiving frames the information handling device is coupled to an external network device. The device also includes a memory that is in communication with the one or more processors and stores a classification matrix. The classification matrix is used to generate a current interrupt throttling rate from a plurality of candidate interrupt throttling rates that are applied to the received frames according to at least two properties of each frame of the received frames. A method for providing adaptive interrupt coalescing is also provided.

Abstract: Numerous embodiments of a method and apparatus for processing latency sensitive electronic data with interrupt moderation are disclosed.

Abstract: A method of scheduling and controlling asynchronous tasks to provide deterministic behavior in time-partitioned operating systems, such as an ARINC 653 partitioned operating environment. The asynchronous tasks are allocated CPU time in a deterministic but dynamically decreasing manner. In one embodiment, the asynchronous tasks may occur in any order within a major time frame (that is, their sequencing is not statically deterministic); however, the dynamic time allotment prevents any task from overrunning its allotment and prevents any task from interfering with other tasks (whether synchronous or asynchronous).

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: A central manager receives tick subscription requests from subscribers, including a requested period and an allowable variance. The manager selects a group period for a group of requests, based on requested period(s) and allowable variance(s). In some cases, the group period is not a divisor of every requested period but nonetheless provides at least one tick within the allowable variance of each requested period. Ticks may be issued by invoking a callback function. Ticks may be issued in a priority order based on the subscriber's category, e.g., whether it is a user-interface process. An application platform may send a tick subscription request on behalf of an application process, e.g., a mobile device platform may submit subscription requests for processes which execute on a mobile computing device. Tick subscription requests may be sent during application execution, e.g., while the application's user interface is being built or modified.

Abstract: An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller that is configured to determine a notification timing for an interrupt request to call the interrupt handler, the notification timing being determined based on the load and an effect of execution of the interrupt handler on user performance of the thread under execution by the processor; and notify the processor of the interrupt request, based on the notification timing. When the load is higher than a threshold, the interrupt controller sets the notification timing for an interrupt request that does not affect the user performance, to be later than the notification timing for an interrupt request that affects the user performance. Based on notification of the interrupt request, the processor calls and executes the interrupt handler that corresponds to the interrupt request.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method.

Abstract: A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority.

Abstract: A controller for controlling interrupt processing in a multiple-interrupt system is provided. The controller includes multiple watchdog timers (WDTs), each provided for each of interrupt priorities. The controller includes interrupt priority selectors, each of which receives each interrupt request signal and outputs an activation signal to a corresponding WDT according to the priority of the interrupt request signal. The controller includes an interrupt processing circuit, which when a WDT has timed out, outputs, to a processor, an interrupt request signal having a priority one or more levels higher than the priority corresponding to the WDT. When multiple causes of interrupt are assigned to one of the interrupt priorities, the interrupt processing circuit gives priority to an interrupt request signal caused by the timeout of a WDT lower in priority level than the interrupt priority to detect that an abnormal operation has occurred in interrupt processing having the lower level priority.

Abstract: An interrupt control apparatus and interrupt control method reduce situations in which the output of interrupt information is suspended and thus reduce stress caused in a user, without missing the appropriate output timing for interrupt information having a high priority level. A priority level setting unit raises the value of a priority level for an interrupt voice message during a period in which the interrupt voice message is being outputted, and a voice output control unit, when interrupts from two or more overlapping interrupt voice messages occurs, carries out control in accordance with priority levels set for each of the two or more interrupt voice messages so that the interrupt voice message having the higher priority level value is preferentially outputted.

Abstract: A mechanism is provided for offloading an input/output (I/O) completion operation. Responsive to a second processor identifying that a flag has been set by a first processor requesting assistance in completing an I/O operation, the second processor copies an I/O response from a first I/O response data structure associated with the first processor to a second I/O response data structure associated with the second processor. The second processor deletes the I/O response from the first I/O response data structure, clears the flag, and processes the I/O operation by addressing the I/O response in the second I/O response data structure. Responsive to completing the I/O operation, the second processor deletes the I/O response from the second I/O response data structure.

Abstract: An application process operates at a privilege level lower than that of the kernel code of the operating system in which the process executes. When the application process requires performance of an operating system service for which the process lacks sufficient privileges to perform directly, rather than repeatedly requesting the service by issuing separate software interrupts, the process instead accumulates the data corresponding to the different service requests in a data container block and defers performance of the service. Whenever the process needs to complete the service, rather than deferring its performance, the process issues a single software interrupt that causes the kernel to use the accumulated data in the data container block to perform each of the N accumulated service requests. This reduces the number of interrupts that must be handled from N to one, thereby greatly reducing the overhead imposed by interrupt handling.

Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

Abstract: A method and circuit for a data processing system (20) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (27-29) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.

Abstract: A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.

Abstract: An interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the interrupt-notification control unit determines a correlation among the interrupt requests to control a time to send the interrupt requests together to the processor.

Abstract: Hardware interrupts are routed to one of multiple processors of a virtualized computer system based on priority values assigned to the codes being executed by the processors. Each processor dynamically updates a priority value associated with code being executed thereby, and when a hardware interrupt is generated, the hardware interrupt is routed to the processor that is executing a code with the lowest priority value to handle the hardware interrupt. As a result, routing of the interrupts can be biased away from processors that are executing high priority tasks or where context switch might be computationally expensive.

Abstract: A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.

Abstract: In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal.

Abstract: Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method.

Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated.

Abstract: The interrupt level storing unit (16) stores one or more interrupt levels indicating the priority of a generated interrupt and stores the interrupt level having the highest priority among the stored interrupt levels as a second interrupt mask level. The second interrupt type determination unit (13) sets an interrupt level corresponding to the interrupt type of a newly generated interrupt. The priority determination unit (14) notifies the interrupt to the virtual machine control unit (20) when the interrupt level of the newly generated interrupt is higher than the stored second interrupt mask level. As a result, the priority of the virtual machine can be determined according to the task priority and the switching of virtual machines can be adequately controlled even if the virtual machines cannot notify the task priority.

Abstract: Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation.

Abstract: In an embodiment, a peripheral component may include a command queue configured to store a set of commands to perform a transfer on a peripheral interface. Some of the commands may be long-latency commands, and the long-latency commands may be aborted to perform higher priority commands. In an embodiment, each command may have an abort attribute assigned by software which indicates whether or not the command is abortable. If a higher priority command needs to be performed while the long-latency command is in progress, the command may be aborted. In an embodiment, software may write an abort field in a control register to cause the long-latency command to be aborted.

Abstract: An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two processors 310, 314 from racing to access the same system resources in their respective interrupt service routines.

Abstract: A system and method of I/O path virtualization between a RAID controller and an environment service module (ESM) in a storage area network (SAN) is disclosed. In one embodiment, a type of I/O request is identified by an input/output (I/O) control engine upon receiving an I/O request from a host computer via a RAID controller. Further, a priority is assigned to the received I/O request based on the type of I/O request by the I/O control engine. Furthermore, the processing of the prioritized I/O request is interrupted by the I/O control engine. In addition, the prioritized I/O request is separated into a command I/O request or a status request. Also, the separated command I/O request or the status request is sent to an associated queue in a plurality of solid state drive (SSD) buffer queues (SBQ) in the I/O control engine.

Abstract: Provided is a method capable of providing an improved response property appropriate for the characteristics of a system by automatically choosing an interrupt handling mode used for each device. The method is a method in which the embedded operating system kernel determines a handling mode for all individual interrupts, the method includes: dividing interrupt handling modes into a first interrupt handling mode and a second interrupt handling mode which has a different process speed from the first interrupt handling mode, and variably determining a distribution ratio in which each of the interrupts are distributed to the first interrupt handling mode or to the second interrupt handling mode according to a predetermined process condition during boot-up.

Abstract: A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented.

Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: Briefly, techniques to manage interrupts and swaps of threads operating in critical region. In an embodiment, a thread is to be interrupted during a first critical region with an interrupt routine. The thread may be set to restart at a beginning of the first critical region in response to an indication that the thread is working in a critical region. Other embodiments are also claimed and disclosed.

Abstract: Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.

Abstract: A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, and an interrupt controller that determines whether or not an input interrupt request signal is associated with one or more than one of the plurality of hardware threads, and when the input interrupt request signal is associated, assigns the interrupt request to an associated hardware thread.

Abstract: An image forming device includes a processor configured to process image data, an image forming unit configured to perform image formation based on the image data processed by the processor, a cover configured to, when being opened, allow an external access to the image forming unit therethrough, a detector configured to detect whether the cover is opened, and an interrupting unit configured to, when determining with the detector that the cover is kept opened for a first time period, interrupt the processing of the image data by the processor.

Abstract: An application process operates at a privilege level lower than that of the kernel code of the operating system in which the process executes. When the application process requires performance of an operating system service for which the process lacks sufficient privileges to perform directly, rather than repeatedly requesting the service by issuing separate software interrupts, the process instead accumulates the data corresponding to the different service requests in a data container block and defers performance of the service. Whenever the process needs to complete the service, rather than deferring its performance, the process issues a single software interrupt that causes the kernel to use the accumulated data in the data container block to perform each of the N accumulated service requests. This reduces the number of interrupts that must be handled from N to one, thereby greatly reducing the overhead imposed by interrupt handling.

Abstract: Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.

Abstract: System, method, and program to determine whether to interrupt a process, e.g., a write function, to carry out another process, e.g., a high priority read function, in a device that uses memory devices, e.g., eMMC devices, that use a single channel to carry out two different processes, e.g., write and read processes.

Abstract: The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.

Abstract: An embodiment of the invention relates to an electronic device for processing interrupt requests. Interrupt requests that have the highest priority level are identified out of a plurality of interrupt requests. A priority word corresponding to a priority level is assigned to each interrupt request. The highest bit level of the bits at the most significant bit position of the priority words is identified. The bit level of the bit at the most significant bit position is compared with the highest bit level at this bit position. The priority words are then evaluated and compared consecutively and bit-by-bit. Priority words having a bit level at the respective bit position that corresponds to the highest bit level are further processed whereas priority words having a different bit level at the respected bit position are discarded.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: An enhanced interrupt controller is provided which is able to receive both hardware-generated and software-generated request signals. Data associated with each received interrupt or request signal is stored in a storage unit within the enhanced interrupt controller in an order which depends on the priority level of the data and, for data of the same level of priority, on the chronological order of receipt. The enhanced interrupt controller instructs the processor, with which it is in communication, to read the stored data from the controller in the stored order ensuring that data of higher priority is read before data of lower priority. A method of routing hardware-generated and software-generated signals from an enhanced interrupt controller to a processor is also disclosed.

Abstract: The invention discloses a method for processing data in a memory for a computer system. The method comprises receiving a first interrupt for triggering a first job, backing up data corresponding to a second interrupt in the memory when a priority degree of the first interrupt is higher than a priority degree of the second interrupt corresponding to a second job currently being executed by the computer system, executing the first job corresponding to the first interrupt, and restoring the data corresponding to the second interrupt to the memory after the first job corresponding to the first interrupt is finished and continue executing the second job corresponding to the second interrupt.

Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.

Abstract: An interrupt control apparatus includes: an interrupt request supply unit that supplies interrupt request information; a processing unit that performs interrupt processing based on the interrupt request information supplied by the interrupt request supply unit; and a time measuring unit that is used to measure an elapse of a predefined time period from a time point when the interrupt request supply unit starts to supply the interrupt request information, wherein: even if new interrupt cause information is stored during the time when the time measuring unit is measuring the elapse of the predefined time period, the interrupt request supply unit does not supply interrupt request information based on the new interrupt cause information to the processing unit; and after the elapsed time measured by the time measuring unit reaches the predefined time period, the interrupt request supply unit supplies the interrupt request information to the processing unit.

Abstract: Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.