Programmable Interrupt Processing Patents (Class 710/266)
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Patent number: 8255603Abstract: A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.Type: GrantFiled: December 8, 2009Date of Patent: August 28, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Jaewoong Chung, Karin Strauss
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Patent number: 8234430Abstract: An embedded microcontroller system comprises a central processing unit, a system controller for receiving and handling an interrupt, a register having storage locations containing sets of predefined system data for different operating conditions of the system assigned to the interrupts coupled to set a system configuration. The system data in the register is defined and stored before receipt of an interrupt. On receipt of an interrupt the system controller transmits a selection signal to the register. The register selects a predefined storage location assigned to the received interrupt. The corresponding system configuration data is used to control system configuration of the embedded microcontroller system, such as allocation of CPU time to virtual CPUs and selection of clock frequency or power voltage for modules.Type: GrantFiled: December 17, 2009Date of Patent: July 31, 2012Assignee: Texas Instruments IncorporatedInventors: Johann Zipperer, Horst Diewald
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Patent number: 8201170Abstract: A method of enabling multiple different operating systems to run concurrently on the same computer, comprising selecting a first operating system to have a relatively high priority (the realtime operating system. such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.Type: GrantFiled: April 7, 2004Date of Patent: June 12, 2012Assignee: Jaluna SAInventors: Eric Lescouet, Vladimir Grouzdev
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Publication number: 20120084477Abstract: Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard L. Arndt, Harold W. Cain, III, Bradly G. Frey, Cathy May
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Patent number: 8151028Abstract: An information processing apparatus connected with an IO device, having a processing unit, a channel device transferring data between the information processing apparatus and the IO device having a activation controller activating the channel device, a storage device having a predetermined area storing a result operation executed by the channel device, an interrupt controller controlling an interrupt required by the channel device to the processing unit, a channel device controller controlling the channel device and a driver writing a request for a first interrupt in the area of the storage device through the channel device and requiring the first interrupt to the processing unit by using the interrupt controller, wherein the processing unit executes driver commands for reading information stored in the area and requesting the first interrupt when the processing unit detects the request for the first interrupt.Type: GrantFiled: February 13, 2009Date of Patent: April 3, 2012Assignee: Fujitsu LimitedInventor: Shuji Nishino
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Patent number: 8145819Abstract: A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block of memory from an interrupt vector memory location. In response to copying the operating system interrupt handlers into the reserved space in the allocated block of memory, custom interrupt handlers from the kernel module are copied over the operating system interrupt handlers in the interrupt vector memory location. The custom interrupt handlers after being copied into the interrupt vector memory location handle all interrupts received by the operating system.Type: GrantFiled: June 4, 2007Date of Patent: March 27, 2012Assignee: International Business Machines CorporationInventors: Sangram Alapati, Brad Lee Herold, Shakti Kapoor, Alexandru Adrian Patrascu
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Patent number: 8135884Abstract: A method and apparatus for a programmable interrupt routing system is described.Type: GrantFiled: May 4, 2010Date of Patent: March 13, 2012Assignee: Cypress Semiconductor CorporationInventors: Bert Sullam, Haneef Mohammed
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Patent number: 8131901Abstract: A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware 26 and virtual interface hardware 28. Hypervisor software responds to an interrupt received by the external interrupt interface hardware 26 to write data characterising that interrupt into list registers 18 of the virtual interface hardware 28. A guest operating system for the virtual machine of the virtual data processing apparatus being emulated may then read data from the virtual interface hardware 28 characterising the interrupt to be processed by that virtual machine. The virtual machine and the guest operating system interact with the virtual interface hardware 28 as if it were external interface hardware. The hypervisor software is responsible for maintaining the data within the virtual interface hardware 28 to properly reflect queued interrupts as received by the external interface 26.Type: GrantFiled: June 4, 2009Date of Patent: March 6, 2012Assignee: ARM LimitedInventors: David H Mansell, Richard R Grisenthwaite
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Publication number: 20120047390Abstract: An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined period of time, a hardware comparator to compare a number of write accesses counted by the hardware counter with at least one predetermined threshold value, the hardware comparator further to generate a control signal, the control signal being dependent on a result of a comparison of a number of write accesses counted by the hardware counter with at least one predetermined threshold value performed by the hardware comparator, and a clock frequency setting circuit to set a clock frequency of a processor depending on the control signal.Type: ApplicationFiled: August 19, 2010Publication date: February 23, 2012Inventor: Uwe HILDEBRAND
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Publication number: 20110307661Abstract: An integrated circuit chip having plural processors with a shared field programmable gate array (FPGA) unit, a design structure thereof, and method for allocating the shared FPGA unit. A method includes storing a plurality of data that define a plurality of configurations of a field programmable gate array (FPGA), wherein the FPGA is arranged in the execution pipeline of at least one processor; selecting one of the plurality of data; and programming the FPGA based on the selected one of the plurality of data.Type: ApplicationFiled: June 9, 2010Publication date: December 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jack R. SMITH, Sebastian T. VENTRONE
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Patent number: 8074006Abstract: An abnormal status detecting method of interrupt pins is provided. In the invention, an advanced configuration and power interface (ACPI) table is looked up for obtaining an interrupt status bit of each interrupt pin in a computer system. Afterwards, the interrupt status bit is continuously checked whether it is maintained at a specific value during a fixed time. When the interrupt status bit of one of the interrupt pins is maintained at the specific value during the fixed time, the interrupt pin is determined to be abnormal.Type: GrantFiled: November 9, 2009Date of Patent: December 6, 2011Assignee: Inventec CorporationInventors: Ying-Chih Lu, Szu-Hsien Lee
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Publication number: 20110283033Abstract: A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.Type: ApplicationFiled: May 12, 2011Publication date: November 17, 2011Inventors: Hiromichi YAMADA, Kotaro Shimamura, Nobuyasu Kanekawa, Yuichi Ishiguro
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Publication number: 20110267188Abstract: A server computer system includes a set of visual indicators for representing status of one or more data storage devices that are connected to one or more nodes of the server system. Control circuitry has at least first and second bus interfaces and is configured to set the state of the visual indicators responsive to signals received through the bus interfaces, and to operate in at least first and second configurable modes. In the first mode, both of the first and the second bus interfaces communicate with a single node. In the second mode, the first bus interface communicates with a first node and the second bus interface communicates with a second node.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Inventors: Larry E. Wilson, Masud M. Reza, Hank Dao
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Patent number: 8037227Abstract: Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is preferably implemented by a virtual priority module within a binary translator in a virtualized computer system and relates to interrupts directed to a virtualized processor by a virtualized local APIC.Type: GrantFiled: August 14, 2009Date of Patent: October 11, 2011Assignee: VMware, Inc.Inventor: Boris Weissman
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Publication number: 20110231590Abstract: In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a low power mobile device, General Purpose Input/Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.Type: ApplicationFiled: May 27, 2011Publication date: September 22, 2011Inventors: Jacob Pan, Vincent Zimmer
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Patent number: 8010726Abstract: A data processing apparatus and method for handling interrupts is provided, the apparatus having an interrupt controller operable to receive interrupts generated by a number of interrupt sources, and to determine based on predetermined criteria whether to output an interrupt request signal. A processing unit is provided which is operable upon receipt of the interrupt request signal to perform an interrupt service routine for a selected one of the received interrupts in order to generate an interrupt response for the corresponding interrupt source. Timer logic is also provided which is operable upon receipt of an interrupt generated by an associated interrupt source to produce a timing indication.Type: GrantFiled: March 1, 2004Date of Patent: August 30, 2011Assignee: ARM LimitedInventor: Hedley James Francis
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Publication number: 20110202796Abstract: A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.Type: ApplicationFiled: November 11, 2010Publication date: August 18, 2011Applicant: VIA TECHNOLOGIES, INC.Inventors: G. Glenn Henry, Darius D. Gaskins, Jason Chen
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Patent number: 8001309Abstract: A method of grouping interrupts from a time-dependent data storage means in accordance with the types of the interrupts, the method comprising the steps of providing each part of the data storage means with an indicator of an event associated with the part, generating interrupts upon the occurrence of events in different parts of the data storage means, allocating interrupts associated with substantially the same part of the data storage means to a same processing means.Type: GrantFiled: June 22, 2006Date of Patent: August 16, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Christoph Patzelt, Vladimir Litovtchenko, Dirk Moeller
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Patent number: 7996835Abstract: System, method and program product for managing a plurality of configurations of a first virtual machine. A command is received to set the configuration of the first virtual machine for processing a next incoming interaction and subsequent incoming interactions of at least one protocol from one or more other virtual machines to a configuration exhibited by the first virtual machine which first subsequently prepares to receive the next incoming interaction. The configuration exhibited by the first virtual machine which first prepared to receive the next incoming interaction is determined. The first virtual machine configuration which first prepared to receive the next incoming interaction processes the next incoming interaction.Type: GrantFiled: October 10, 2006Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Daniel M. Griffith, James P. McCormick, III, Damian L. Osisek, William Romney White
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Publication number: 20110191513Abstract: An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit.Type: ApplicationFiled: October 7, 2010Publication date: August 4, 2011Applicant: RDC Semiconductor Co., Ltd.Inventors: Chang-Cheng YAP, Ching-Yun CHENG
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Patent number: 7987464Abstract: A method, apparatus, and computer usable program code for logical partitioning and virtualization in heterogeneous computer architecture. In one illustrative embodiment, a portion of a first set of processors of a first type is allocated to a partition in a heterogeneous logically partitioned system and a portion of a second set of processors of a second type is allocated to the partition.Type: GrantFiled: July 25, 2006Date of Patent: July 26, 2011Assignee: International Business Machines CorporationInventors: Michael N. Day, Michael Karl Gschwind, Mark R. Nutter, James Xenidis
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Patent number: 7987307Abstract: In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.Type: GrantFiled: September 22, 2006Date of Patent: July 26, 2011Assignee: Intel CorporationInventors: Parthasarathy Sarangam, Anil Vasudevan
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Patent number: 7987283Abstract: A system (150) and method are disclosed that provide for the transfer of at least one packet (194) comprising data between a user space (152) and a kernel space (154) associated with a server (156) that is positioned in a distributed network arrangement (192) with a plurality of clients (158, 160, 162, 164). A distribution program (168) associated with the user space (152) is operable to accumulate the at least one packet (194). An application program interface (174) associated with the user space (152) transfers the at least one packet (194) to the kernel space (154) with a number of software interrupts (204). A driver (176) associated with the kernel space (154) is operable to distribute the at least one packet (194) to a subset of the plurality of clients (158, 160, 162, 164) in response to receiving the number of software interrupts (204). The number of software interrupts (204) is less than one software interrupt per packet per client.Type: GrantFiled: July 29, 2009Date of Patent: July 26, 2011Assignee: Charles Schwab & Co., Inc.Inventors: Andrew David Klager, Robert Lee Rhudy
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Patent number: 7984218Abstract: A processor 1 provided with a plurality of cores, an interrupt operation dedicated core 20 which is used only for an interrupt operation; a normal core 11 to 1n which outputs an interrupt request when an interrupt source is generated; and an interrupt control part 30 which, upon receipt of the interrupt request, assigns an operation by an interrupt vector to the interrupt operation dedicated core 20.Type: GrantFiled: January 23, 2009Date of Patent: July 19, 2011Assignee: NEC CorporationInventor: Kumiko Suzuki
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Patent number: 7979619Abstract: Methods, systems, apparatuses and program products are disclosed for managing interrupt services in hypervisor and hypervisor-related environments in Message Signaled Interrupts are emulated as other type(s) of interrupt. According to an aspect of the present invention, a method of executing a program includes receiving a MSI (message signaled interrupt). Responsively, a virtual interrupt is generated and an ISR (interrupt service routine) is invoked that handles a line-based virtual interrupt transaction. A surrogate or virtual peripheral device status may also be provided and may be associated with the virtual interrupt. A single device interrupt event may, in certain circumstances, be serviced both as a line-based interrupt and also as an MSI, or as either responsive to run-time context. Embodiments of the present invention enable superior tradeoffs in regards to the interrupt sharing to a greater and more flexible extent than with previous implementations.Type: GrantFiled: December 23, 2008Date of Patent: July 12, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kaushik Barde, Richard Bramley, Matthew Ryan Laue
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Patent number: 7975087Abstract: A control and communication unit is provided between a terminal and at least one microcircuit card. The unit includes a control module for a number of input signals to the card; a module for generation of a number of time diagrams for the card communication protocols; a request generation module for transmission and reception of characters based on information received from the control module, the requests being transmitted to an external module; and an interruption generation module for creating an interruption in the case of an error in a time diagram or a character received or transmitted, based on information received from the control module and for processing the interruption without a loss of characters. The generation of an interruption does not cause an interruption in the process of request generation.Type: GrantFiled: July 5, 2006Date of Patent: July 5, 2011Assignee: Compagnie Industrielle et Financiere D'Ingenierie “Ingenico”Inventor: Arnaud Simon
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Publication number: 20110161542Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Bruce L. Fleming, Arvind Mandhani
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Patent number: 7962679Abstract: A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts and/or interrupt sources are distributed among multiple physical sockets, i.e. multiple physical processors. However, if the interrupt activity is below a threshold for a number of periods, which denotes low interrupt activity, then a power save mode is selected. Here, interrupts and/or sources are primarily assigned to a single processor to allow other physical processors to save power. Furthermore, after interrupts are assigned to a physical processor, the interrupts may be further distributed among cache domains of the processor. In addition, high activity classes, interrupt sources, interrupts, or categories may be further assigned to specific processing elements for servicing.Type: GrantFiled: September 28, 2007Date of Patent: June 14, 2011Assignee: Intel CorporationInventor: Adriaan van de Ven
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Patent number: 7953914Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.Type: GrantFiled: June 3, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Marc A. Gollub, Zane C. Shelley, Alwood P. Williams, III
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Patent number: 7953915Abstract: Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.Type: GrantFiled: March 26, 2009Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Yi Ge, ChaoJun Liu, Wen Bo Shen, Yuan Ping
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Patent number: 7950013Abstract: A storage system has a single processor that operates in a multitasking operating system environment. An operation time manager adjusts the balance between processing time proportions for interrupt processing and task processing requested of the storage system internally and externally so that those processing time proportions become within respective predetermined ranges.Type: GrantFiled: April 21, 2006Date of Patent: May 24, 2011Assignee: Hitachi, Ltd.Inventors: Nakaba Sato, Toshiaki Terao, Hiroji Shibuya
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Publication number: 20110119445Abstract: A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.Type: ApplicationFiled: January 29, 2010Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas M. Gooding, David L. Satterfield, Burkhard Steinmacher-Burow
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Publication number: 20110072181Abstract: An abnormal status detecting method of interrupt pins is provided. In the invention, an advanced configuration and power interface (ACPI) table is looked up for obtaining an interrupt status bit of each interrupt pin in a computer system. Afterwards, the interrupt status bit is continuously checked whether it is maintained at a specific value during a fixed time. When the interrupt status bit of one of the interrupt pins is maintained at the specific value during the fixed time, the interrupt pin is determined to be abnormal.Type: ApplicationFiled: November 9, 2009Publication date: March 24, 2011Applicant: INVENTEC CORPORATIONInventors: Ying-Chih Lu, Szu-Hsien Lee
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Patent number: 7913017Abstract: An embedded system and an interruption handling method are provided. A plurality of interruption requests are received, and corresponding service routines are triggered with priority control. In the embedded system, a memory device comprises a plurality of service routines stored at different entry addresses, each related to an interruption request. A processor receives an enable signal to initialize one of the service routines through a branch instruction. A control unit buffers the interruption requests to schedule executions of corresponding service routines. When a specific service routine is to be executed, the control unit provides the branch instruction pointing to entry address of the specific service routine and asserts the enable signal to the processor, such that the processor executes the branch instruction to initialize the specific service routine.Type: GrantFiled: September 25, 2008Date of Patent: March 22, 2011Assignee: Mediatek Inc.Inventors: Tse-Hong Wu, Liang-Yun Wang
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Patent number: 7895382Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.Type: GrantFiled: January 14, 2004Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Jimmie Earl DeWitt, Jr., Frank Eliot Levine, Christopher Michael Richardson, Robert John Urquhart
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Patent number: 7873770Abstract: In one embodiment, an input/output memory management unit (IOMMU) comprises a control register and control logic coupled to the control register. The control register is configured to store a base address of a device table, wherein a given input/output (I/O) device has an associated device identifier that selects a first entry in the device table. The first entry comprises a pointer to an interrupt remapping table. The control logic is configured to remap an interrupt specified by an interrupt request received by the IOMMU from the given I/O device if the interrupt remapping table includes an entry for the interrupt.Type: GrantFiled: November 13, 2006Date of Patent: January 18, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Mark D. Hummel, Andrew W. Lueck, Andrew G. Kegel
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Patent number: 7845006Abstract: A method of reducing the window of malicious exploitation between vulnerability publication and the installation of a software patch. One or more probe points are inserted into a code path in an application (or operating system if applicable) that contains one or more vulnerabilities (or coding errors). The probe points mark locations of the security vulnerabilities utilizing software interrupts to enable the original code base of the code path to remain unmodified. A probe handler utility subsequently monitors the execution of the code path and generates an alert if the execution reaches a probe point in the code path, thus indicating whether the application exhibits a particular vulnerability. The probe handler selectively performs one of multiple customizable corrective actions, thereby securing the application until an applicable software patch can be installed.Type: GrantFiled: January 23, 2007Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Prasadarao Akulavenkatavara, Janice M. Girouard, Emily J. Ratliff
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Publication number: 20100299471Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.Type: ApplicationFiled: May 24, 2010Publication date: November 25, 2010Inventors: Pankaj Shrivastava, Gregory Goodhue, Ata khan, Zhimin Ding, Craig Mackenna
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Publication number: 20100299474Abstract: According to one embodiment, an information processing apparatus includes a first caching processing module which starts a caching moving image data stored in a storage medium in a memory device when the storage medium is loaded in a media drive, and a second caching processing module which erases all of moving image data items cached in the memory device when the storage medium is ejected from the media drive.Type: ApplicationFiled: May 19, 2010Publication date: November 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Gen WATANABE
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Patent number: 7836317Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.Type: GrantFiled: January 29, 2008Date of Patent: November 16, 2010Assignee: Altera Corp.Inventors: Patrick R. Marchand, Gerald George Pechanek, Edward A. Wolff
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Patent number: 7836450Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.Type: GrantFiled: January 11, 2006Date of Patent: November 16, 2010Assignee: MIPS Technologies, Inc.Inventor: Kevin D. Kissell
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Publication number: 20100274939Abstract: An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel.Type: ApplicationFiled: February 22, 2010Publication date: October 28, 2010Inventors: Bernhard Egger, Dong-hoon Yoo, Soo-jung Ryu, Il-hyun Park
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Publication number: 20100257297Abstract: Methods for processing more securely are disclosed. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of proprietary, confidential or otherwise secure data stored in SMRAM.Type: ApplicationFiled: October 6, 2009Publication date: October 7, 2010Inventor: David A. Dunn
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Patent number: 7809876Abstract: A distributed control system and methods of operating such a control system are disclosed. In one embodiment, the distributed control system is operated in a manner in which interrupts are at least temporarily inhibited from being processed to avoid excessive delays in the processing of non-interrupt tasks. In another embodiment, the distributed control system is operated in a manner in which tasks are queued based upon relative timing constraints that they have been assigned. In a further embodiment, application programs that are executed on the distributed control system are operated in accordance with high-level and/or low-level requirements allocated to resources of the distributed control system.Type: GrantFiled: February 6, 2009Date of Patent: October 5, 2010Assignee: Rockwell Automation Technologies, Inc.Inventor: Sivaram Balasubramanian
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Patent number: 7805725Abstract: A method and system is provided for automatically reassigning an interface card and devices associated with the interface card in a programmable logic controller system from a non-deterministic operating environment to a deterministic operating environment so that the change is performed essentially instantaneously to avoid disruption of operations of the PLC devices associated with the interface involved in the reassignment. All operating system registries and configurations are automatically performed. The move provides for an improved response time for devices associated with and controlled by the card.Type: GrantFiled: September 22, 2003Date of Patent: September 28, 2010Assignee: Siemens Industry, Inc.Inventors: Richard C. Schaftlein, Daniel F. Moon
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Patent number: 7802038Abstract: New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.Type: GrantFiled: November 21, 2008Date of Patent: September 21, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Ryan D. Bedwell, Arnold R. Cruz, John J. Vaglica, William C. Moyer
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Publication number: 20100217906Abstract: Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.Type: ApplicationFiled: February 20, 2009Publication date: August 26, 2010Applicant: QUALCOMM INCORPORATEDInventors: Martyn Ryan Shirlen, Richard Gerard Hofmann, Michael Egnoah Birenbach
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Patent number: 7783811Abstract: An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group.Type: GrantFiled: December 17, 2007Date of Patent: August 24, 2010Assignee: Microsoft CorporationInventors: Bruce Worthington, Vinod Mamtani, Brian Railing
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Patent number: 7765388Abstract: The present invention relates to a device for an interrupt verification support mechanism and the method for operating said device comprising a processor and an input for external interrupt requests or interrupt pseudo-instructions communicatively coupled to the processor. The method comprises the steps of processing at least one actual instruction in the processor in an instruction pipeline, and if an external interrupt request is received by the processor, the actual instruction is replaced with the pseudo-instruction. Pursuant to the method, instructions are concurrently processed in the processor in an instruction pipeline with several stages. In the instruction pipeline, instructions are processed by an instruction fetch stage, an instruction decode stage, an instruction issue stage, an execute stage and a result write-back stage. Thereby, interrupt requests are only processed at the fetch stage of the instruction pipeline.Type: GrantFiled: September 17, 2003Date of Patent: July 27, 2010Assignee: Broadcom CorporationInventors: Geoff Barrett, Richard Porter
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Patent number: 7761638Abstract: In a virtual computing machine, a system and method that dynamically patches the interrupt mechanism (in interrupt vector space) of a host computing architecture with guest mode software. Significant increases in performance are achieved without depending on the host code. A patching mechanism evaluates the operating system version, processor, and code to be patched. If patchable, low-level interfaces are created dynamically; a dispatcher is written into an unused location in vector space, and instructions copied from each interrupt vector to be patched to a guest interrupt vector. For an interrupt, the new, patched instructions branch to the dispatcher, which then branches to the appropriate patched interrupt guest code. If the processor is operating as a virtual machine, the guest interrupt code handles the interrupt, otherwise the original copied instructions are replayed, followed by execution at the original host instruction in vector space that exists after the copied and patched instructions.Type: GrantFiled: April 22, 2008Date of Patent: July 20, 2010Assignee: Microsoft CorporationInventors: Bradley S. Post, Rene A. Vega